TI SN74AVC2T872

SN74AVC2T872
www.ti.com........................................................................................................................................................................................... SCES710 – NOVEMBER 2008
VOLTAGE-LEVEL SHIFTER FOR IC-USB INTERFACE
FEATURES
1
•
•
•
•
•
•
YFP PACKAGE
(TOP VIEW)
VCCA, VCCB Supply Voltage: 1.1 V to 3.6 V
When VCCB = 0 V, A-Port is Disabled and
B-Port is Held at GND Through 120-kΩ
Pulldown
Crossover Skew of <1 ns
Meets All Requirements of the IC-USB
Standard
Small Package: 0.4 mm pitch WCSP
(1.2 mm × 1.6 mm)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II ESD Performance
– A-Port (Host Side)
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
– B-Port (Peripheral Side)
– 8000-V Contact Discharge
– 15000-V Air-Gap Discharge
1
2
3
A
B
C
D
1
2
3
A
PD_EN
VCCA
VCCB
D+(B)
B
D+(A)
VCCA
C
D–(A)
GND
D–(B)
D
DIR
GND
DIR_POL
DESCRIPTION/ORDERING INFORMATION
The SN74AVC2T872 is a 2-bit voltage level translator optimized for use in interchip USB (IC-USB) applications.
VCCA and VCCB can each operate over the full range of 1.1 V to 3.6 V. The device has been designed to maintain
crossover skew to be less than 1 ns. Each B-port has an integrated 120-kΩ pulldown resistor that can be
enabled and disabled using the PD_EN control signal. If VCCB = 0 V, the A-port I/Os are disabled (Hi-Z) and the
B-port I/Os are held to GND through the 120-kΩ resistors. If VCCA = 0 V, the A-port and B-port I/Os are disabled
(Hi-Z).
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE (1) (2)
WCSP – YFP
Reel of 3000
ORDERABLE PART NUMBER
SN74AVC2T872YFPR
TOP-SIDE MARKING (3)
_ _ _ TU _
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
SN74AVC2T872
SCES710 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
TYPICAL APPLICATION BLOCK DIAGRAM
1.8 V
3V
IEC ESD
Protection
D+
Host
Application
Processor
D–
TX_EN
PD_EN
A-Port
VCCA
VCCB
D+(A)
D+(B)
D–(A)
D–(B)
D+
D–
HD Sim Card
GND
DIR
PD_EN
DIR_POL
SN74AVC2T872
B-Port
LOGIC DIAGRAM
VCCA
VCCB
DIR_POL
DIR
D+(A)
PD_EN
D+(B)
Rpd(+) 120 kΩ
VCCB
Power-Down
Control
D–(A)
D–(B)
Rpd(–)
2
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120 kΩ
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AVC2T872
SN74AVC2T872
www.ti.com........................................................................................................................................................................................... SCES710 – NOVEMBER 2008
TERMINAL FUNCTIONS
BALL NO.
NAME
FUNCTION
A1
PD_EN
Input to enable pulldown resistors on B-side. PD_EN = Low will disconnect the pulldown resistors.
PD_EN = High will connect the pulldown resistors.
A2, B2
VCCA
A-side supply voltage (1.1 V to 3.6 V)
A3
VCCB
B-side supply voltage (1.1 V to 3.6 V)
B1
D+(A)
USB data signal connected to host.
B3
D+(B)
USB data signal connected to peripheral with internal 120 kΩ resistor to GND that can be
disconnected by PD_EN.
C1
D–(A)
USB data signal connected to host.
C2, D2
GND
Ground
C3
D–(B)
USB data signal connected to peripheral with internal 120 kΩ resistor to GND that can be
disconnected by PD_EN.
D1
DIR
D3
DIR_POL
Direction control input. If DIR_POL = Low, then DIR = Low allows A to B data flow.
If DIR_POL = High, then DIR = High allows A to B data flow.
Direction polarity chooser. If DIR_POL = Low, then DIR = Low allows A to B data flow.
If DIR_POL = High, then DIR = High allows A to B data flow.
FUNCTION TABLE
INPUTS
A-SIDE
B-SIDE
FUNCTION
L
Input
Output
A-to-B Data Flow
DIR_POL
DIR
L
L
H
Output
Input
B-to-A Data Flow
H
L
Output
Input
B-to-A Data Flow
H
H
Input
Output
A-to-B Data Flow
B-SIDE PULLDOWN RESISTOR BEHAVIOR
VCCA
VCCB
PD_EN
PULLDOWN RESISTOR
B-SIDE
0V
X
X
None
1.1 to 3.6 V
0V
X
120 kΩ to GND
1.1 to 3.6 V
1.1 to 3.6 V
L
None
1.1 to 3.6 V
1.1 to 3.6 V
H
120 kΩ to GND
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
4.6
I/O ports (A-Port)
–0.5
4.6
I/O ports (B-Port)
–0.5
4.6
Control inputs
–0.5
4.6
A-Port
–0.5
4.6
B-Port
–0.5
4.6
A-Port
–0.5
VCCA + 0.5
B-Port
–0.5
VCCB + 0.5
VCCA
Supply voltage range
VCCB
VI
Input voltage range (2)
UNIT
V
V
VO
Voltage range applied to any output in the high-impedance or
power-off state (2)
VO
Voltage range applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCCA, VCCB, or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
4
YFP package
–65
V
V
±100
mA
137.5
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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RECOMMENDED OPERATING CONDITIONS (1) (2) (3)
VCCI
VCCO
MIN
MAX
UNIT
VCCA
Supply voltage
1.1
3.6
V
VCCB
Supply voltage
1.1
3.6
V
High-level
input voltage
VIH
Low-level
input voltage
VIL
High-level
input voltage
VIH
VIL
Low-level
input voltage
VI
Input voltage
Data inputs (4)
Data inputs
(4)
DIR, DIR_POL, PD_EN
(referenced to VCCA) (5)
DIR, DIR_POL, PD_EN
(referenced to VCCA) (5)
1.1 V to 1.95 V
VCCI × 0.65
1.95 V to 2.7 V
1.65
2.7 V to 3.6 V
2
1.1 V to 1.95 V
VCCI × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
1.1 V to 1.95 V
VCCA × 0.65
1.95 V to 2.7 V
VCCA × 0.65
2.7 V to 3.6 V
VCCA × 0.65
Output voltage
IOH
VCCA × 0.35
1.95 V to 2.7 V
VCCA × 0.35
IOL
3.6
Active state
0
VCCO
3-state
0
3.6
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
(3)
(4)
(5)
V
VCCA × 0.35
0
High-level output current
V
V
1.1 V to 1.95 V
2.7 V to 3.6 V
VO
V
1.1 to 1.3 V
–2
1.4 V to 1.6 V
–6
1.65 V to 1.95 V
–8
2.3 V to 2.7 V
–9
3 V to 3.6 V
–12
1.1 V to 1.3 V
2
1.4 V to 1.6 V
6
1.65 V to 1.95 V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
–40
V
V
mA
mA
5
ns/V
85
°C
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. All unused control inputs of the
device must be held at VCCA or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating
CMOS Inputs, literature number SCBA004.
For data input values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For control input values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
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ELECTRICAL CHARACTERISTICS (1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.1 V to 3.6 V
1.1 V to 3.6 V
IOH = –2 mA
1.1 V
1.1 V
IOH = –6 mA
1.4 V
1.4 V
1
1.65 V
1.65 V
1.2
IOH = –9 mA
2.3 V
2.3 V
1.75
IOH = –12 mA
3V
3V
2.3
IOL = 100 µA
1.1 V to 3.6 V
1.1 V to 3.6 V
IOL = 3 mA
1.1 V
1.1 V
0.3
IOL = 6 mA
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
0.7
1.1 V to 3.6 V
1.1 V to 3.6 V
±0.025
±0.25
±1
µA
µA
IOH = –8 mA
VOL
IOL = 8 mA
VI = VIH
VI = VIL
II
Control
inputs
VI = VCCA or GND
Ioff
A port
VI or VO = 0 to 3.6 V
A port
DIR_POL = Low, DIR = Low
PD_EN = Low,
VI = VCCI to GND, DIR = High
IOZ
B port
ICCA
Control
inputs
Ci
A port
Cio
B port
Rpd(+),
Rpd(–)
(1)
(2)
6
TYP
MAX
MIN
MAX
UNIT
VCCO – 0.2
0.9
V
0.2
V
0V
0 V to 3.6 V
±0.02
±2.5
±5
3.6 V
±0.01
±2.5
±5
3.6 V
3.6 V
±0.14
±5
±15
1.1 V to 3.6 V
1.1 V to 3.6 V
0.02
0V
0 V to 3.6 V
0 V to 3.6 V
0V
0.01
10
1.1 V to 3.6 V
1.1 V to 3.6 V
0.13
30
0V
0 V to 3.6 V
0.07
15
0 V to 3.6 V
0V
1.1 V to 3.6 V
1.1 V to 3.6 V
0.15
40
µA
VI = 3.3 V or GND
3.6 V
3.6 V
1.5
2
pF
VO = 3.3 V or GND
3.6 V
3.6 V
5.5
7
27
32.5
DIR_POL = Low,
DIR = High,
PD_EN = High
3.6 V
3.6 V
VI = VCCI or GND, IO = 0
ICCA + ICCB
MIN
3.6 V
VI = VCCI or GND, IO = 0
ICCB
–40°C to 85°C
VCCB
IOH = –100 µA
VOH
TA = 25°C
VCCA
VI = VCCI or GND, IO = 0
µA
10
–2
µA
µA
–2
118
80
150
pF
kΩ
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.2 V ± 0.1 V, PD_EN = 0 V (unless otherwise noted)
PARAMETER
tPLH
tPHL
tPLH
Propagation
delay
tPHL
TO
(OUTPUT)
VCCB = 1.2 V
± 0.1 V
MIN
MAX
VCCB = 1.5 V
± 0.1 V
MIN
MAX
VCCB = 1.8 V
± 0.15 V
MIN
VCCB = 2.5 V
± 0.2 V
MAX
MIN
MAX
VCCB = 3.3 V
± 0.3 V
MIN
UNIT
MAX
D+(A) to D+(B) or
D–(A) to D–(B)
22
16
14
12
11
22
16
14
12
11
D+(B) to D+(A) or
D–(B) to D–(A)
19
17
17
16
15
19
17
17
16
15
ns
ns
tr
Output rise time
14
14
14
14
14
ns
tf
Output fall time
14
14
14
14
14
ns
24
24
24
24
24
24
24
24
24
24
28
22
19
15
14
28
22
19
15
14
47
39
36
31
29
47
39
36
31
29
46
40
38
36
35
46
40
38
36
35
tPHZ
tPLZ
tPHZ
tPZH
tPZL
tPZH
D+(A) or D–(A)
DIR or DIR_POL
D+(B) or D–(B)
DIR or DIR_POL
D+(A) or D–(A)
DIR or DIR_POL
D+(B) or D–(B)
Enable time (1)
tPZL
Fmax
DIR or DIR_POL
Disable time
tPLZ
(1)
FROM
(INPUT)
Max data rate
12
12
12
12
12
ns
ns
ns
ns
Mbps
The enable time is a calculated value derived using the formula shown in the enable times section.
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V, PD_EN = 0 V (unless otherwise noted)
PARAMETER
tPLH
tPH
tPLH
Propagation
delay
tPHL
VCCB = 1.2 V
± 0.1 V
MIN
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
D+(A) to D+(B) or
D–(A) to D–(B)
18
0.7
13.3
0.5
11.3
0.4
8.9
0.3
7.7
18
0.7
11.8
0.5
10.2
0.4
8.2
0.3
7.5
D+(B) to D+(A) or
D–(B) to D–(A)
13
0.8
11.2
0.7
10.5
0.6
9.7
0.5
9.3
13
0.8
10.9
0.7
10.2
0.6
9.4
0.5
9.1
UNIT
ns
ns
Output rise time
14
10
10
10
10
ns
tf
Output fall time
14
10
10
10
10
ns
tPLZ
tPHZ
tPZH
tPZL
tPZH
D+(A) or D–(A)
DIR or DIR_POL
D+(B) or D–(B)
DIR or DIR_POL
D+(A) or D–(A)
DIR or DIR_POL
D+(B) or D–(B)
Enable time (1)
tPZL
Fmax
DIR or DIR_POL
Disable time
tPLZ
8
TO
(OUTPUT)
tr
tPHZ
(1)
FROM
(INPUT)
Max data rate
12
17
1.3
14.2
1.3
13.4
1
11.8
1
11.1
17
1.3
14.2
1.3
14.3
1
14.4
1
14.4
22
1.1
14.5
1.4
13.3
1.2
10.6
1.7
10.1
22
1.1
16.8
1.4
13.5
1.2
9.8
1.7
9.3
35
28
24
19.5
18.5
35
25.3
23.5
20
19.2
35
27.5
25.5
23.2
22.1
35
26.1
23.6
20
18.6
12
12
12
12
ns
ns
ns
ns
Mbps
The enable time is a calculated value derived using the formula shown in the enable times section.
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V, PD_EN = 0 V (unless otherwise noted)
PARAMETER
tPLH
tPHL
tPLH
Propagation
delay
tPHL
TO
(OUTPUT)
VCCB = 1.2 V
± 0.1 V
MIN
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
D+(A) to D+(B) or
D–(A) to D–(B)
17
0.7
12.6
0.4
10.5
0.2
8.1
0.2
6.9
17
0.7
11.2
0.4
9.5
0.2
7.4
0.2
6.7
D+(B) to D+(A) or
D–(B) to D–(A)
11
0.5
9.5
0.4
8.8
0.5
7.9
0.4
7.5
11
0.5
9.3
0.4
8.7
0.5
7.9
0.4
7.6
UNIT
ns
ns
tr
Output rise time
14
10
10
10
10
ns
tf
Output fall time
14
10
10
10
10
ns
tPHZ
tPLZ
tPHZ
tPZH
tPZL
tPZH
D+(A) or D–(A)
DIR or
DIR_POL
D+(B) or D–(B)
DIR or
DIR_POL
D+(A) or D–(A)
DIR or
DIR_POL
D+(B) or D–(B)
Enable Time (1)
tPZL
Fmax
DIR or
DIR_POL
Disable time
tPLZ
(1)
FROM
(INPUT)
Max data rate
12
13
1.1
11.4
1
10.8
0.5
9.8
0.5
9
13
1.1
10.7
1
10.8
0.5
10.8
0.5
10.9
21
1.1
10.7
1.3
10.6
0.8
9
0.5
9
21
1.1
15.7
1.3
12.5
0.8
8.8
0.5
8.3
32
25.2
21.3
16.7
15.8
32
20.1
19.2
16.9
16.6
30
23.3
21.3
18.9
17.7
30
22.7
20.3
17.2
15.8
12
12
12
12
ns
ns
ns
ns
Mbps
The enable time is a calculated value derived using the formula shown in the enable times section.
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V, PD_EN = 0 V (unless otherwise noted)
PARAMETER
tPLH
tPHL
tPLH
Propagation
delay
tPHL
VCCB = 1.2 V
± 0.1 V
MIN
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
D+(A) to D+(B) or
D–(A) to D–(B)
16
0.5
11.7
0.2
9.7
0.2
7.2
0.2
6
16
0.5
10.5
0.2
8.7
0.2
7.2
0.2
5.8
D+(B) to D+(A) or
D–(B) to D–(A)
9
0.4
7.5
0.5
6.8
0.4
5.9
0.3
5.6
9
0.4
7.5
0.5
6.8
0.4
6
0.3
5.6
ns
ns
Output rise time
14
10
10
10
10
ns
tf
Output fall time
14
10
10
10
10
ns
tPLZ
tPHZ
tPZH
tPZL
tPZH
D+(A) or D–(A)
DIR or
DIR_POL
D+(B) or D–(B)
DIR or
DIR_POL
D+(A) or D–(A)
DIR or
DIR_POL
D+(B) or D–(B)
Enable time (1)
tPZL
Fmax
DIR or
DIR_POL
Disable time
tPLZ
10
TO
(OUTPUT)
tr
tPHZ
(1)
FROM
(INPUT)
Max data rate
12
11
0.7
7.8
0.7
7.5
0.7
6.9
0.5
6.4
11
0.7
6.8
0.7
6.8
0.7
6.8
0.5
6.8
19
0.6
8.4
0.5
7.4
0.5
6.3
1
7.2
19
0.6
14.4
0.5
11
0.5
7.4
1
6.9
29
21.9
17.8
13.3
12.5
29
15.9
14.2
12.2
12.8
27
18.5
16.4
14
12.8
27
18.2
16.2
14.1
12.2
12
12
12
12
ns
ns
ns
ns
Mbps
The enable time is a calculated value derived using the formula shown in the enable times section.
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SN74AVC2T872
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V, PD_EN = 0 V (unless otherwise noted)
PARAMETER
tPLH
tPHL
tPLH
Propagation
delay
tPHL
TO
(OUTPUT)
VCCB = 1.2 V
± 0.1 V
MIN
MAX
MIN
MAX
MIN
MAX
D+(A) to D+(B)
or D–(A) to D–(B)
15
0.6
11.3
0.4
9.2
0.3
6.8
0.3
5.6
15
0.6
10.2
0.4
8.4
0.3
6.2
0.3
5.5
D+(B) to D+(A)
or D–(B) to D–(A)
9
0.3
6.6
0.2
5.8
0.2
4.9
0.2
4.5
9
0.3
7
0.2
6.2
0.2
5.3
0.2
4.9
Output fall time
14
tPZL
tPZH
D+(A) or D–(A)
DIR or DIR_POL
D+(B) or D–(B)
DIR or DIR_POL
D+(A) or D–(A)
DIR or DIR_POL
D+(B) or D–(B)
Enable time (1)
tPZL
Fmax
DIR or DIR_POL
Disable time
tPZH
VCCB = 3.3 V
± 0.3 V
MIN
tf
tPLZ
VCCB = 2.5 V
± 0.2 V
MAX
14
tPHZ
VCCB = 1.8 V
± 0.15 V
MIN
Output rise
time
tPLZ
VCCB = 1.5 V
± 0.1 V
MAX
tr
tPHZ
(1)
FROM
(INPUT)
Max data rate
12
10
10
10
10
10
10
10
ns
6.6
1
6.5
1
6.1
1
5.8
9
1
5.7
1
5.7
1
5.7
1
5.7
19
0.5
7.4
0.3
6.5
0.3
5.2
0.3
5.3
19
0.5
13.8
0.3
10.6
0.3
7
0.3
6.4
28
20.4
16.4
11.9
10.9
28
14.4
12.7
10.4
10.2
24
17
14.9
12.5
11.3
24
16.7
14.9
12.3
11.3
12
ns
ns
1
12
ns
10
9
12
UNIT
12
ns
ns
ns
ns
Mbps
The enable time is a calculated value derived using the formula shown in the enable times section.
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SN74AVC2T872
SCES710 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
IC-USB INTERFACE CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V, PD_EN = 0 V (unless otherwise noted)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
MIN
VCCB = 3 V
± 0.3 V
MAX
MIN
UNIT
MAX
1
1
1
1
Consecutive
transitions jitter
2
2
tjitter_p
Paired transitions jitter
1
1
Fmax
Max data rate
tsko
Output crossover skew
tjitter_c
D+(A) to D–(A)
VCCB = 1.8 V
± 0.15 V
Opposite Transitions
D+(B) to D–(B)
12
12
ns
ns
Mbps
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
CpdA
CpdB
(1)
12
(1)
A-port input,
B-port output
B-port input,
A-port output
(1)
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
1
1
1
1
2
14
14
14
16
20
28
27
27
27
27
1
1
1
1
2
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
UNIT
pF
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
pF
Power dissipation capacitance per transceiver
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SN74AVC2T872
www.ti.com........................................................................................................................................................................................... SCES710 – NOVEMBER 2008
PARAMETER MEASURMENT INFORMATION
2 X V CCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 X V CCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
18 pF
18 pF
18 pF
18 pF
18 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCI
Input
VCCI/2
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
VCCI/2
tPZL
0V
tPLH
tPHL
Output
VCCI/2
VOH
VCCO/2
VOL
VCCO/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO
90%
90%
tPLZ
VCCO
Output
Waveform 1
S1 at 2 X V CCO
(see Note B)
VCCO/2
VOL + V TP
VOL
tPZH
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VCCO/2
VOH - V TP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
0V
tr
tf
OUTPUT RISE AND FALL TIMES
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W,
dv/dt ≥ 1 V/ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten. For the SN74AVC2T872, these delays are calculated per the Enable Times
forumulas shown in Table 1.
G.
tPLH and tPHL are the same as tpd.
H.
VCCI is the VCC associated with the input port.
I.
VCCO is the VCC associated with the output port.
Figure 1. Load Circuit and Voltage Waveforms
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SN74AVC2T872
SCES710 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
PARAMETER MEASURMENT INFORMATION (continued)
Input
Input
D+
D–
VCCI/2
VCCI/2
D–
D+
Outputs
Outputs
D+
D–
VCCO/2
VCCO/2
D+
D–
tSK(O)1
tSK(O)2
D+
D–
VCCO/2
VCCO/2
D+
D–
tSK(O)1
tSK(O)2
Figure 2. Output Crossover Skew
tjitter_p
tjitter_c
VCCO/2
D+ or D–
Integer
multiples of tw
Consecutive
Transitions
Paired Transitions
Figure 3. Output Jitter
14
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SN74AVC2T872
www.ti.com........................................................................................................................................................................................... SCES710 – NOVEMBER 2008
APPLICATION INFORMATION
Enable Times
Calculate the enable times for the SN74AVC2T872 using the following formulas shown in Table 1.
Table 1. Enable Times
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC2T872 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
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15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74AVC2T872YFPR
ACTIVE
DSBGA
YFP
Pins Package Eco Plan (2)
Qty
12
3000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
SNAGCU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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