ISO7420, ISO7420M ISO7421, ISO7421M www.ti.com SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 Low-Power Dual Digital Isolators Check for Samples: ISO7420, ISO7420M, ISO7421, ISO7421M FEATURES APPLICATIONS • • • 1 2 • • • • • • Highest Signaling Rate: up to 250 Mbps Low Power Consumption, Typical ICC per Channel: – 2.2 mA at 25 Mbps, 4.2 mA at 100 Mbps Very Low Propagation Delay – 9 ns Typ. and Very Low Skew – 300 ps Typ. Widest TA Range Specified: –55°C to 125°C 4-kVpeak Maximum Isolation, 2.5 kVrms per UL 1577, IEC/VDE and CSA Approved, IEC 60950-1, IEC 61010-1 End Equipment Standards Approved. All Approvals Pending. 50 kV/μs Transient Immunity, Typical Over 25-Year Isolation Integrity at Rated Voltage Operates From 3-V to 5.5-V Supply and Logic Levels Optocoupler Replacement in: – Industrial Fieldbus – Profibus – Modbus – DeviceNet™ Data Buses – Servo Control Interface – Motor Control – Power Supplies – Battery Packs DESCRIPTION The ISO7421 and ISO7421M provide galvanic isolation up to 2.5 kVrms for 1 minute per UL. These digital isolators have two isolated channels. Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL input thresholds and require two supply voltages from 3 V to 5.5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3-V supply. 1 INA 2 INB 3 GND1 4 ISO7421 D Package (Top View) 8 VCC2 VCC1 1 7 OUTA OUTA 2 6 OUTB INB 3 5 GND2 GND1 4 Isolation VCC1 Isolation ISO7420 D Package (Top View) 8 VCC2 7 INA 6 OUTB 5 GND2 P0066-08 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DeviceNet is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated ISO7420, ISO7420M ISO7421, ISO7421M SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TERMINAL FUNCTIONS TERMINAL NAME I/O NO. INA 7 INB GND1 DESCRIPTION I Input, channel A 3 I Input, channel B 4 – Ground connection for VCC1 GND2 5 – Ground connection for VCC2 OUTA 2 O Output, channel A OUTB 6 O Output, channel B VCC1 1 – Power supply, VCC1 VCC2 8 – Power supply, VCC2 Table 1. FUNCTION TABLE (1) INPUT SIDE VCC OUTPUT SIDE VCC PU PU PD (1) PU INPUT IN OUTPUT OUT H H L L Open H X H PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.4 V); X = Irrelevant; H = High level; L = Low level AVAILABLE OPTIONS PRODUCT RATED ISOLATION PACKAGE INPUT THRESHOLD RATED TA CHANNEL DIRECTION MARKED AS ISO7420 –40°C to 105°C IS7420 ISO7420M –55°C to 125°C I7420M –40°C to 105°C IS7421 Same direction 2.5 kVrms D-8 ISO7421 2 ~1.5 V (TTL) (CMOS compatible) –55°C to 125°C Submit Documentation Feedback ISO7420D (rail) ISO7420DR (reel) ISO7420MD (rail) Opposite directions ISO7421M (PREVIEW) ORDERING NUMBER ISO7420MDR (reel) ISO7421D (rail) ISO7421DR (reel) ISO7421MD (rail) I7421M ISO7421MDR (reel) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M ISO7420, ISO7420M ISO7421, ISO7421M www.ti.com SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) VALUE VCC Supply voltage (2), VCC1, VCC2 –0.5 V to 6 V VI Voltage at IN, OUT –0.5 V to 6 V IO Output current ESD Electrostatic discharge ±15 mA Human-body model JEDEC Standard 22, Test Method A114-C.01 Field-induced charged-device model JEDEC Standard 22, Test Method C101 Machine model ANSI/ESDS5.2-1996 ±4 kV All pins ±1.5 kV ±200 V TJ(Max) Maximum junction temperature (1) (2) 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX 3 5.5 VCC1, VCC2 Supply voltage IOH High-level output current IOL Low-level output current –4 VIH High-level input voltage 2 VIL Low-level input voltage TJ (1) Junction temperature (1) 4 VCC 0 0.8 –55 136 UNIT V mA V °C To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table and the Icc Equations section of this data sheet. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M 3 ISO7420, ISO7420M ISO7421, ISO7421M SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5 V ±10%; TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER VOH High-level output voltage VOL Low-level output voltage MIN TYP IOH = –4 mA; see Figure 1. TEST CONDITIONS VCC – 0.8 4.6 IOH = –20 μA; see Figure 1. VCC – 0.1 5 MAX V IOL = 4 mA; see Figure 1. 0.2 0.4 IOL = 20 μA; see Figure 1. 0 0.1 VI(HYS) Input threshold voltage hysteresis 400 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 3. μA μA –10 25 V mV 10 IN from 0 V or VCC UNIT 1.2 pF 50 kV/μs SUPPLY CURRENT ISO7420 ICC1 Supply current for VCC1 ICC2 Quiescent 0.4 0.8 25 Mbps 1.5 2.5 5 8 100 Mbps 200 Mbps 8 17 Quiescent 2.7 4.5 25 Mbps Supply current for VCC2 VI = VCC or 0 V, no load 100 Mbps VI = VCC or 0 V, no load 200 Mbps 3.8 6 7 11 15 20 2 3 mA mA ISO7421 Quiescent ICC1 25 Mbps Supply current for VCC1 ICC2 3.5 5 7.5 11 200 Mbps 12 17 Quiescent 2 3 3.5 5 7.5 11 12 17 100 Mbps 25 Mbps Supply current for VCC2 100 Mbps VI = VCC or 0 V, no load VI = VCC or 0 V, no load 200 Mbps mA mA SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5 V ±10%; TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER TEST CONDITIONS MIN MAX 9 12 ns 0.3 1.5 ns 2 ns 1.6 ns Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 5 4 1 / tui Signaling rate 0 250 (1) 4 See Figure 1. TYP tPLH, tPHL See Figure 1. See Figure 2. UNIT 1 ns 1 ns 6 μs ns 200 Mbps Also known as pulse skew. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M ISO7420, ISO7420M ISO7421, ISO7421M www.ti.com SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS VCC1 at 5 V ±10%, VCC2 at 3.3 V ±10%; TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER VOH TEST CONDITIONS IOH = –4 mA; see Figure 1. High-level output voltage ISO7421 (5-V side) MIN TYP MAX UNIT VCC – 0.8 V IOH = –20 μA; see Figure 1. VCC – 0.1 IOL = 4 mA; see Figure 1. 0.4 IOL = 20 μA; see Figure 1. 0.1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 3. V 400 mV μA 10 IN from 0 V or VCC μA –10 25 1.2 pF 40 kV/μs SUPPLY CURRENT ISO7420 Quiescent ICC1 25 Mbps Supply current for VCC1 100 Mbps VI = VCC or 0 V, no load 0.4 0.8 1.5 2.5 5 8 8 17 2 3.5 200 Mbps Quiescent ICC2 25 Mbps Supply current for VCC2 100 Mbps VI = VCC or 0 V, no load 2.7 5 4.5 7.5 7 12 200 Mbps mA mA ISO7421 Quiescent ICC1 25 Mbps Supply current for VCC1 ICC2 100 Mbps 3 5 7.5 11 200 Mbps 12 17 Quiescent 1.5 2.5 2.2 3.5 4.2 6 7.2 9 25 Mbps Supply current for VCC2 VI = VCC or 0 V, no load 2 3.5 100 Mbps VI = VCC or 0 V, no load 200 Mbps mA mA SWITCHING CHARACTERISTICS VCC1 at 5 V ±10%, VCC2 at 3.3 V ±10%; TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER TYP MAX 10 15 ns 0.5 2 ns Part-to-part skew time 3 ns Channel-to-channel output skew time 2 ns tPLH, tPHL Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) tsk(o) tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 1 / tui Signaling rate (1) TEST CONDITIONS MIN See Figure 1. See Figure 1. UNIT 2 See Figure 2. ns 2 ns 6 μs 10 5 0 200 ns 100 Mbps Also known as pulse skew. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M 5 ISO7420, ISO7420M ISO7421, ISO7421M SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 at 3.3 V ±10%, VCC2 at 5 V ±10%; TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER VOH TEST CONDITIONS IOH = –4 mA; see Figure 1. High-level output voltage ISO7421 (3.3-V side) IOH = –20 μA; see Figure 1. MIN TYP VCC – 0.4 Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 3. UNIT V VCC – 0.1 IOL = 4 mA; see Figure 1. VOL MAX 0.4 IOL = 20 μA; see Figure 1. 0 0.1 400 mV 10 IN from 0 V or VCC μA μA –10 25 V 1 pF 40 kV/μs SUPPLY CURRENT ISO7420 Quiescent ICC1 0.5 0.8 1.3 2.1 3.5 200 Mbps 4 7 Quiescent 2.7 4.5 25 Mbps 3.8 6 7 11 200 Mbps 15 20 Quiescent 1.5 2.5 25 Mbps 2.2 3.5 4.2 6 200 Mbps 7.2 9 Quiescent 2 3 25 Mbps Supply current for VCC1 ICC2 0.2 100 Mbps Supply current for VCC2 100 Mbps VI = VCC or 0 V, no load VI = VCC or 0 V, no load mA mA ISO7421 ICC1 Supply current for VCC1 ICC2 100 Mbps 25 Mbps Supply current for VCC2 100 Mbps VI = VCC or 0 V, no load VI = VCC or 0 V, no load 200 Mbps 3.5 5 7.5 11 12 17 mA mA SWITCHING CHARACTERISTICS VCC1 at 3.3 V ±10%, VCC2 at 5 V ±10%, TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER TYP MAX 10 15 ns 0.5 2 ns Part-to-part skew time 3 ns Channel-to-channel output skew time 2 ns tPLH, tPHL Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) tsk(o) tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 1 / tui Signaling rate (1) 6 TEST CONDITIONS MIN See Figure 1. See Figure 1. 2 See Figure 2. UNIT ns 2 ns 6 μs 10 5 0 200 ns 100 Mbps Also known as pulse skew. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M ISO7420, ISO7420M ISO7421, ISO7421M www.ti.com SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3 V ±10%, TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER TEST CONDITIONS VOH High-level output voltage VOL Low-level output voltage MIN TYP IOH = –4 mA; see Figure 1. VCC – 0.4 3 IOH = –20 μA; see Figure 1. VCC – 0.1 3.3 MAX V IOL = 4 mA; see Figure 1. 0.2 0.4 IOL = 20 μA; see Figure 1. 0 0.1 VI(HYS) Input threshold voltage hysteresis 400 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 3. μA μA –10 25 V mV 10 IN from 0 V or VCC UNIT 1 pF 40 kV/μs SUPPLY CURRENT ISO7420 Quiescent ICC1 25 Mbps Supply current for VCC1 100 Mbps VI = VCC or 0 V, no load 0.2 0.5 0.8 1.3 2.1 3.5 4 7 2 3.5 200 Mbps Quiescent ICC2 25 Mbps Supply current for VCC2 2.7 5 4.5 7.5 200 Mbps 7 12 Quiescent 1.5 2.5 25 Mbps 2.2 3.5 4.2 6 100 Mbps VI = VCC or 0 V, no load mA mA ISO7421 ICC1 Supply current for VCC1 ICC2 100 Mbps 200 Mbps 7.2 9 Quiescent 1.5 2.5 2.2 3.5 4.2 6 7.2 9 25 Mbps Supply current for VCC2 VI = VCC or 0 V, no load 100 Mbps VI = VCC or 0 V, no load 200 Mbps mA mA SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3 V ± 10%, TA = –55°C to 125°C for ISO7421M, TA = –40°C to 105°C for ISO7421 PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 1 / tui Signaling rate (1) TEST CONDITIONS MIN See Figure 1. TYP MAX 12 18 ns 1 3 ns 4 ns 3.5 ns 2 See Figure 1. See Figure 2. UNIT ns 2 ns 6 μs 10 5 0 200 ns 100 Mbps Also known as pulse skew. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M 7 ISO7420, ISO7420M ISO7421, ISO7421M SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 www.ti.com Isolation Barrier PARAMETER MEASUREMENT INFORMATION IN Input Generator (1) 50 W VI VCC1 VI OUT 1.4 V 1.4 V 0V VO CL tPLH (2) tPHL 90% 10% VCC/2 VO VCC/2 VOH VOL tr tf S0412-01 (1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. (2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI VCC1 VCC1 Isolation Barrier 0 V IN or VCC1 VI 2.7 V 0V OUT tfs VO VOH CL 50% VO (1) Fail-Safe HIGH VOL S0413-01 (1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms S1 IN C = 0.1 mF ±1% Isolation Barrier VCC1 GND1 VCC2 C = 0.1 mF ±1% Pass-fail criteria – output must remain stable. OUT + VOH or VOL GND2 (1) – + VCM – S0414-01 (1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M ISO7420, ISO7420M ISO7421, ISO7421M www.ti.com SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 DEVICE INFORMATION PACKAGE CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4.8 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4.3 mm CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 >175 V Minimum internal gap (internal clearance) Distance through the insulation 0.008 mm RIO Isolation resistance CIO Barrier capacitance, input to output Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, TA < 100°C >1012 Ω Input to output >1011 Ω 1 pF VI = 0.4 sin (4E6πt) NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. INSULATION CHARACTERISTICS (1) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIORM Maximum working insulation voltage VPR Input-to-output test voltage VIOTM Transient overvoltage VISO Isolation voltage per UL RS Insulation resistance t = 1 s (100% production), partial discharge 5 pC t = 60 s (qualification) t = 1 s (100% production) UNIT 560 V 1050 V 4000 V t = 60 s (qualification) 2500 t = 1 s (100% production) 3000 VIO = 500 V at TS >109 Pollution degree (1) SPECIFICATION Vrms Ω 2 Climatic Classification 40/125/21 Table 2. IEC 60664-1 RATINGS TABLE PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group III-a Rated mains voltage ≤ 150 Vrms I–IV Rated mains voltage ≤ 300 Vrms I–III Rated mains voltage ≤ 400 Vrms I–II Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M 9 ISO7420, ISO7420M ISO7421, ISO7421M SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 www.ti.com REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File number: pending (40016131) File number: pending (1698195) File number: pending (E181974) (1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577. LIFE EXPECTANCY vs WORKING VOLTAGE Life Expectancy – Years 100 VIORM at 560 V 28 Years 10 0 120 250 500 750 880 1000 VIORM – Working Voltage – V G001 Figure 4. Life Expectancy vs Working Voltage IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum case temperature MIN TYP MAX θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 124 θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 190 150 UNIT mA °C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. PACKAGE THERMAL CHARACTERISTICS (over recommended operating conditions unless otherwise noted) PARAMETER θJA (1) 10 TEST CONDITIONS Junction-to-air thermal resistance MIN TYP (1) 212 High-K thermal resistance (1) 122 Low-K thermal resistance MAX UNIT °C/W Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M ISO7420, ISO7420M ISO7421, ISO7421M www.ti.com SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS θJB Junction-to-board thermal resistance θJC Junction-to-case thermal resistance PD Device power dissipation MIN VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 150-Mbps 50% duty-cycle square wave TYP MAX UNIT 37 °C/W 69.1 °C/W 390 mW 200 Safety Limiting Current − mA 180 VCC1, VCC2 at 3.6 V 160 140 VCC1, VCC2 at 5.5 V 120 100 80 60 40 20 0 0 50 100 150 TC − Case Temperature − °C 200 G002 Figure 5. θJC Thermal Derating Curve per IEC 60747-5-2 ICC EQUATIONS ICC1,2 = ICC1,2_quiescent + Sum of all dynamic ICC inputs on side 1,2 + sum of all dynamic ICC outputs on side 1,2 (1) ICC_quiescent can be determined from the electrical specification tables for concerned product included in the datasheet for the appropriate VCC. Dynamic ICC can be calculated as follows. At VCC = 3.6, worst case ICC_input = 0.016 × f ICC_output = 0.02 × f + 0.002 × f × (CL – 0.5) (2) (3) At VCC = 5.5, worst case ICC_input = 0.036 × f ICC_output = 0.033 × f + 0.0032 × f × (CL – 0.5) (4) (5) where ICC is in mA, f = data rate in Mbps, CL = capacitive load in pF. VCC1 0.1mF OUTPUT INPUT GND1 VCC2 2 mm 2 mm max. max. ISO7421 from from VCC1 VCC2 8 1 OUTA INA 7 2 INB OUTB 6 3 5 4 0.1mF INPUT OUTPUT GND2 S0417-01 Figure 6. Typical ISO7421 Application Circuit Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M 11 ISO7420, ISO7420M ISO7421, ISO7421M SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 www.ti.com Input VCC1 VCC1 VCC1 Output VCC2 1 MW 500 W 8W IN OUT 13 W S0422-01 Figure 7. Device I/O Schematics 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M ISO7420, ISO7420M ISO7421, ISO7421M www.ti.com SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SIGNAL RATE (ALL CHANNELS) SUPPLY CURRENT vs SIGNAL RATE (ALL CHANNELS) 18 CL = 15 pF TA = 25°C 18 16 ICC1, ICC2 − Supply Current − mA ICC1, ICC2 − Supply Current − mA 20 14 VCC1, VCC2 at 5 V 12 10 8 6 VCC1, VCC2 at 3.3 V 4 2 0 14 VCC1, VCC2 at 5 V 12 10 8 6 VCC1, VCC2 at 3 V 4 2 0 0 20 40 60 80 100 120 140 160 180 200 Signal Rate − Mbps 0 40 60 80 100 120 140 160 180 200 Signal Rate − Mbps G011 Figure 8. ISO7421 Figure 9. ISO7420 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE INPUT VOLTAGE SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE Input Voltage Switching Threshold − V 1.6 12 VCC1, VCC2 at 3.3 V 10 8 VCC1, VCC2 at 5 V 6 4 2 0 −55 20 G003 14 tpd − Propagation Delay Time − ns CL = 15 pF TA = 25°C 16 −35 −15 5 25 45 65 85 TA − Free-Air Temperature − °C Figure 10. Copyright © 2009, Texas Instruments Incorporated 105 125 G004 1.5 VIT+, 5 V 1.4 VIT+, 3.3 V 1.3 1.2 1.1 VIT−, 5 V 1.0 VIT−, 3.3 V 0.9 0.8 −55 −35 −15 5 25 45 65 85 105 125 TA − Free-Air Temperature − °C G005 Figure 11. Submit Documentation Feedback Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M 13 ISO7420, ISO7420M ISO7421, ISO7421M SLLS984A – JUNE 2009 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) FAIL-SAFE VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 IOH − High-Level Output Current − mA Fail-Safe Voltage Threshold − V 2.62 2.61 FS+ 2.60 2.59 2.58 2.57 2.56 2.55 FS− 2.54 2.53 2.52 −55 TA = 25°C −10 −20 −30 −40 VCC1, VCC2 at 3.3 V −50 −60 −70 VCC1, VCC2 at 5 V −80 −90 −35 −15 5 25 45 65 85 105 TA − Free-Air Temperature − °C 125 0 1 2 3 4 5 6 VOH − High-Level Output Voltage − V G006 Figure 12. G007 Figure 13. LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE IOL − Low-Level Output Current − mA 80 TA = 25°C 70 60 VCC1, VCC2 at 5 V 50 40 VCC1, VCC2 at 3.3 V 30 20 10 0 0 1 2 3 4 VOL − Low-Level Output Voltage − V 5 6 G008 Figure 14. Figure 15. Eye Diagram at 250 MBPS, 5-V VCC, Typical 14 Submit Documentation Feedback Figure 16. Eye Diagram at 200 MBPS, 5-V VCC, 125°C Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): ISO7420, ISO7420M ISO7421, ISO7421M PACKAGE OPTION ADDENDUM www.ti.com 24-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ISO7420D ACTIVE SOIC D 8 ISO7420DR ACTIVE SOIC D 8 ISO7420MD ACTIVE SOIC D 8 ISO7420MDR ACTIVE SOIC D 8 ISO7421D ACTIVE SOIC D 8 ISO7421DR ACTIVE SOIC D 8 ISO7421MD PREVIEW SOIC D 8 75 TBD Call TI Call TI ISO7421MDR PREVIEW SOIC D 8 2500 TBD Call TI Call TI 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 75 75 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO7421DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7421DR SOIC D 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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