ISO7240CF www.ti.com ................................................................................................................................................ SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 QUAD DIGITAL ISOLATOR WITH SELECTABLE FAILSAFE OUTPUT FEATURES 1 • • • • 0-Mbps (DC) to 25 Mbps Signaling Rate – Low Channel-to-Channel Output Skew; 2 ns Max – Low Pulse-Width Distortion (PWD); 2.5 ns Max Typical 25-Year Life at Rated Working Voltage (see application note SLLA197 and Figure 11) 4000-Vpeak Isolation, 560 Vpeak VIORM – UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1 and CSA Approved 4 kV ESD Protection • • • Operates with 3.3-V or 5-V Supplies High Electromagnetic Immunity (see application note SLLA181) –40°C to 125°C Operating Range APPLICATIONS • • • • • Flat Plasma Display Panels Industrial Fieldbus Computer Peripheral Interface Servo Control Interface Data Acquisition DESCRIPTION The ISO7240CF is a quad-channel digital isolator with an input disable function and a selectable high or low failsafe-output function with the CTRL pin (pin 10). The device has logic input and output buffers separated by TI’s silicon dioxide (SiO2) isolation barrier. When used in conjunction with isolated power supplies, the device blocks high voltage, isolates grounds, and prevents noise currents from entering the local ground and interfering with or damaging sensitive circuitry. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to the logic state selected by the user. The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left unconnected. If a logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output state. The ISO7240CF also includes an input disable function that prevents data from being passed across the isolation barrier to the output. When the inputs are disabled, the outputs are set by the CTRL pin. This device may be powered from either 3.3-V or 5-V supplies on either side in any combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used. The device is characterized for operation over the ambient temperature range of –40°C to 125°C. ISO7240CF VCC1 GND1 INA INB INC IN D DISABLE GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB OUTC OUTD CTRL GND2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2008, Texas Instruments Incorporated ISO7240CF SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE FUNCTION TABLE (1) VCC1 VCC2 DATA INPUT (IN) DISABLE INPUT (DISABLE) FAILSAFE CONTROL INPUT (CTRL) DATA OUTPUT (OUT) PU PU H L or Open X H PU PU L L or Open X L X PU X H H or Open H X PU X H L L PD PU X X H or Open H PD PU X X L L (1) PU = Powered Up; PD = Powered Down; X = Irrelevant; H = High Level; L = Low Level ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT VCC Supply voltage (2), VCC1, VCC2 –0.5 to 6 V VI Voltage at IN, OUT, EN –0.5 to 6 V IO Output current ±15 mA Electrostatic discharge JEDEC Standard 22, Test Method A114-C.01 Human Body Model ESD Electrostatic discharge TJ Maximum junction temperature (1) (2) Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101 Machine Model ANSI/ESDS5.2-1996 ±4 All pins kV ±1 ±200 V 170 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX 4.5 5.5 3 3.6 VCC Supply voltage, VCC1, VCC2 IOH High-level output current IOL Low-level output current –4 tui Input pulse width 40 4 UNIT V mA mA ns 1/tui Signaling rate 0 VIH High-level input voltage (IN, DISABLE, CTRL) 2 VCC VIL Low-level input voltage (IN, DISABLE, CTRL) 0 0.8 V TJ Junction temperature 150 °C H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification 1000 A/m (1) 2 30 (1) 25 Mbps V Typical signaling rate under ideal conditions at 25°C. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF ISO7240CF www.ti.com ................................................................................................................................................ SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 Supply current ICC2 Supply current IOFF Sleep mode output current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, all channels, no load VI = VCC or 0 V, all channels, no load DISABLE at VCC, single channel TYP MAX 1 3 7 10.5 15 22 17 25 VCC – 0.4 IOH = –20 µA, See Figure 1 VCC – 0.1 0.4 IOL = 20 µA, See Figure 1 0.1 200 V mV 10 –10 35 mA V IOL = 4 mA, See Figure 1 IN, DISABLE, CTRL from 0 V to VCC mA µA 0 IOH = –4 mA, See Figure 1 UNIT µA 1 pF 50 kV/µs SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time twake Wake time from input disable See Figure 2 15 µs tfs Failsafe output delay time from input power loss See Figure 3 12 µs (1) (2) (3) 42 UNIT Propagation delay, low-to-high-level output See Figure 1 18 MAX tPLH, tPHL 2.5 (2) (3) 0 See Figure 1 ns 8 ns 2 ns 2 2 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF 3 ISO7240CF SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS VCC1 at 5 V and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 Supply current ICC2 Supply current IOFF Sleep mode output current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, all channels, no load VI = VCC or 0 V, all channels, no load DISABLE at Vcc, single channel TYP MAX 1 3 7 10.5 9.5 15 10.5 17 VCC – 0.4 IOH = –20 µA, See Figure 1 VCC – 0.1 0.4 IOL = 20 µA, See Figure 1 0.1 200 V mV 10 –10 25 mA V IOL = 4 mA, See Figure 1 IN, DISABLE, CTRL from 0 V to VCC mA µA 0 IOH = –4 mA, See Figure 1 UNIT µA 1 pF 50 kV/µs SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time twake Wake time from input disable See Figure 2 15 µs tfs Failsafe output delay time from input power loss See Figure 3 18 µs (1) (2) (3) 4 46 UNIT Propagation delay, low-to-high-level output See Figure 1 20 MAX tPLH, tPHL 3 (2) (3) 0 See Figure 1 2 2 ns 10 ns 2.5 ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF ISO7240CF www.ti.com ................................................................................................................................................ SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ELECTRICAL CHARACTERISTICS VCC1 at 3.3-V, VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 Supply current ICC2 Supply current IOFF Sleep mode output current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, all channels, no load VI = VCC or 0 V, all channels, no load DISABLE at VCC, single channel TYP MAX 0.5 1 3 5 15 22 17 25 VCC – 0.4 IOH = –20 µA, See Figure 1 VCC – 0.1 0.4 0 0.1 200 IN, DISABLE, CTRL from 0 V to VCC V mV 10 –10 25 mA V IOL = 4 mA, See Figure 1 IOL = 20 µA, See Figure 1 mA µA 0 IOH = –4 mA, See Figure 1 UNIT µA 1 pF 50 kV/µs SWITCHING CHARACTERISTICS VCC1 at 3.3-V and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time twake Wake time from input disable See Figure 2 15 µs tfs Failsafe output delay time from input power loss See Figure 3 12 µs (1) (2) (3) 51 UNIT Propagation delay, low-to-high-level output See Figure 1 22 MAX tPLH, tPHL 3 (2) (3) 0 See Figure 1 ns 10 ns 2.5 ns 2 2 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF 5 ISO7240CF SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent ICC1 Supply current ICC2 Supply current IOFF Sleep mode output current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 25 Mbps Quiescent 25 Mbps MIN VI = VCC or 0 V, all channels, no load VI = VCC or 0 V, all channels, no load DISABLE at VCC, single channel TYP MAX 0.5 1 3 5 9.5 15 10.5 17 VCC – 0.4 IOH = –20 µA, See Figure 1 VCC – 0.1 0.4 IOL = 20 µA, See Figure 1 0.1 200 V mV 10 –10 25 mA V IOL = 4 mA, See Figure 1 IN, DISABLE, CTRL from 0 V to VCC mA µA 0 IOH = –4 mA, See Figure 1 UNIT µA 1 pF 50 kV/µs SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time twake Wake time from input disable See Figure 2 15 µs tfs Failsafe output delay time from input power loss See Figure 3 18 µs (1) (2) (3) 6 56 UNIT Propagation delay, low-to-high-level output See Figure 1 25 MAX tPLH, tPHL 4 (2) (3) 0 See Figure 1 2 2 ns 10 ns 3 ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF ISO7240CF www.ti.com ................................................................................................................................................ SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH VO CL NOTE B VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. IN DISABLE Input Generator (Note A) VI 0V IN VI VI VCC2 /2 0V t wake CL (Note B) OUT VCC2 50% VO 0V VCC2 VO VI VCC2 /2 0V CTRL t wake CL (Note B) 3V 50 W VCC2 VO CTRL 50 W DISABLE Input Generator (Note A) OUT 0V ISOLATION BARRIER 3V ISOLATION BARRIER Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VO VCC2 50% 0V NOTE: Which ever test yields the longest time is used in this data sheet. A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Wake Time From Input Disable VCC1 0V or VCC1 IN ISOLATION BARRIER VI VCC1 OUT VI VO CL NOTE B 2.7 V 0V VOH tfs VO 50% FAILSAFE HIGH VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF 7 ISO7240CF SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC1 VCC2 C = 0.1 mF± 1% S1 ISOLATION BARRIER C = 0.1 mF± 1% IN Pass-fail criteria: Output must remain stable OUT NOTE B GND1 VOH or VOL GND2 VCM A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 4. Common-Mode Transient Immunity Test Circuit DEVICE INFORMATION PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 7.7 mm L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface 8.1 mm Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, TA < 100°C >1012 Ω Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max >1011 Ω CIO Barrier capacitance Input to output VI = 0.4 sin (4E6πt) 1 pF CI Input capacitance to ground VI = 0.4 sin (4E6πt) 1 pF DEVICE I/O SCHEMATICS DISABLE INPUT CTRL OUTPUT VCC1 VCC2 VCC2 VCC2 VCC 2 VCC 2 1 MW 500 W 500 W EN VCC1 VCC2 500 W 8W IN OUT EN 1 MW 13 W 1 MW 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF ISO7240CF www.ti.com ................................................................................................................................................ SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Low-K Thermal Resistance (1) 168 High-K Thermal Resistance 96.1 UNIT θJA Junction-to-air θJB Junction-to-Board Thermal Resistance 61 °C/W θJC Junction-to-Case Thermal Resistance 48 °C/W PD Device Power Dissipation (1) VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty cycle square wave °C/W 220 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. REGULATORY INFORMATION UL Recognized under 1577 Component Recognition Program (1) File Number: E181974 (1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. TYPICAL CHARACTERISTIC CURVES PROPAGATION DELAY vs FREE-AIR TEMPERATURE INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE 1.4 45 40 30 5V 25 1.35 3.3 V, Vth+ tPHL Input Voltage Threshold - V Propagation Delay - ns 35 tPLH 3.3 V tPLH tPHL 20 15 10 5 5 V, Vth+ 1.3 1.25 Air Flow at 7 cf/m, Low-K Board 1.2 1.15 5 V, Vth- 1.1 3.3 V, Vth- Load = 15 pF, Air Flow at 7 cf/m, Low-K Board 0 -40 -25 -10 5 20 35 50 65 80 95 TA - Free-Air Temperature - °C 110 125 1.05 1 -40 -25 -10 5 20 35 50 65 80 95 TA - Free-Air Temperature - °C Figure 5. 110 125 Figure 6. Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF 9 ISO7240CF SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTIC CURVES (continued) HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT vs SUPPLY VOLTAGE VCC1 FAILSAFE THRESHOLD vs Vout (Vout vs VCC1 ACROSS TEMPERATURE) 50 3 VCC1 Failsafe Threshold - V 2.8 2.7 TA = 25°C, Load = 15 pF 40 IO - Output Current - mA 2.9 VCC at 5 V or 3.3 V, Load = 15 pF, Air Flow at 7/cf/m, Low-K Board Vfs+ 2.6 2.5 Vfs2.4 2.3 2.2 VCC = 5 V 30 VCC = 3.3 V 20 10 2.1 2 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - °C 0 0 1 2 3 4 5 6 VO - Output Voltage - V Figure 7. Figure 8. LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 50 TA = 25°C, Load = 15 pF 45 IO - Output Current - mA 40 VCC = 3.3 V 35 30 VCC = 5 V 25 20 15 10 5 0 0 1 2 3 VO - Output Voltage - V 4 5 Figure 9. 10 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF ISO7240CF www.ti.com ................................................................................................................................................ SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 APPLICATION INFORMATION 20 mm max. from VCC2 20 mm max. from VCC1 VCC1 VCC2 0.1 mF 0.1 mF 1 16 2 15 IN A 3 14 OUT A IN B 4 13 OUT B IN C 5 12 OUT C 6 11 GND2 GND1 IN D OUT D CTRL DISABLE 7 10 8 9 GND 2 GND 1 ISO7240CF NOTE: It is recommended that the DISABLE pin not be left floating if unused in an application. Figure 10. Typical ISO7240CF Failsafe-Low Application Circuit WORKING LIFE -- YEARS 100 VIORM at 560 V 28 Years 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (V IORM ) -- V Figure 11. Time Dependent Dielectric Breakdown Test Results Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s) :ISO7240CF 11 PACKAGE OPTION ADDENDUM www.ti.com 22-Apr-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ISO7240CFDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CFDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CFDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CFDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Apr-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO7240CFDWR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.9 10.78 3.0 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Apr-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7240CFDWR SOIC DW 16 2000 406.0 348.0 63.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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