ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com Low-Power 5 KV(rms) Dual Digital Isolators Check for Samples: ISO7520C, ISO7521C FEATURES 1 • • • • • • • Highest Signaling Rate: 1 Mbps Propagation Delay Less Than 20 ns Low Power Consumption Wide Ambient Temperature: –40°C to 105°C Safety and Regulatory Approvals – UL 1577 Approved with 4243 Vrms Rating – CSA CA Notice 5A, IEC 60747-5-2, IEC 60601-1, 60950-1, and 61010-1 Approved 50 kV/µs Transient Immunity Typical Operates From 3.3V or 5V Supply and Logic Levels APPLICATIONS • Opto-Coupler Replacement in: – Medical Applications for IEC 60601-1 (5 KVrms Rated) – Industrial Field-Bus – ProfiBus – ModBus – DeviceNetTM Data Buses – Servo Control Interface – Motor Control – Power Supply – Battery Packs The devices have TTL input thresholds and require two supply voltages, 3.3V or 5V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply. Note: The ISO7520C and ISO7521C are specified for signaling rates up to 1 Mbps. Due to their fast response time, under most cases, these devices will also transmit data with much shorter pulse widths. Designers should add external filtering to remove spurious signals with input pulse duration < 20 ns if desired. ISO7520C GND 1 NC VCC 1 INA INB NC GND 1 NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND 2 NC VCC 2 OUTA OUTB NC NC GND 2 GND 1 NC VCC 1 OUTA INB NC GND 1 NC 1 2 3 4 5 6 7 8 ISO7521C 16 15 14 13 12 11 10 9 GND 2 NC VCC 2 INA OUTB NC NC GND 2 NC = No Internal Connection DESCRIPTION The ISO7520C and ISO7521C provide galvanic isolation of up to 4243 Vrms for 1 minute per UL. These devices are also certified to 5000 Vrms reinforced insulation per end equipment standards IEC 60950-1, 61010-1, and 60601-1. These digital isolators have two isolated channels with uni-directional (ISO7520C) and bi-directional (ISO7521C) channel configurations. Each isolation channel has a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. PIN DESCRIPTIONS PIN NAME I/O DESCRIPTION ISO7520C ISO7521C INA 4 13 I Input, channel A INB 5 5 I Input, channel B GND1 1, 7 1, 7 – Ground connection for VCC1 GND2 9, 16 9, 16 – Ground connection for VCC2 OUTA 13 4 O Output, channel A OUTB 12 12 O Output, channel B VCC1 3 14 – Power supply, VCC1 VCC2 3 14 – Power supply, VCC2 2, 6, 8, 10, 11, 15 2, 6, 8, 10, 11, 15 - No Connect Pin NC DEVICE FUNCTION TABLE INPUT SIDE (VCC) (1) OUTPUT SIDE (VCC) (1) PU PU PD (1) INPUT (IN) (1) OUTPUT (OUT) (1) H H PU L L Open H X H PU = Powered Up (Vcc ≥ 3.15V); PD = Powered Down (Vcc ≤ 2.4V); X = Irrelevant; H = High Level; L = Low Level AVAILABLE OPTIONS PRODUCT RATED TA MARKED AS ISO7520C –40°C to 105°C ISO7520CDW ISO7521C –40°C to 105°C ISO7521CDW ORDERING NUMBER ISO7520CDW (rail) ISO7520CDWR (reel) ISO7521CDW (rail) ISO7521CDWR (reel) ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT VCC Supply voltage (2), VCC1, VCC2 –0.5 V to 6 V VI Voltage at IN, OUT –0.5 V to 6 V IO Output Current ±15 mA ±4 kV ±1 kV Human Body Model JEDEC Standard 22, Test Method A114-C.01 Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101 Machine Model ANSI/ESDS5.2-1996 ESD Electrostatic discharge TJ Maximum junction temperature (1) (2) 2 All pins ±200 V 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com THERMAL INFORMATION ISO752xC THERMAL METRIC DW UNITS 16 PINS Junction-to-ambient thermal resistance (1) θJA 79.9 (2) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (3) 51.2 ψJT Junction-to-top characterization parameter (4) 18.0 ψJB Junction-to-board characterization parameter (5) 42.2 θJCbot Junction-to-case (bottom) thermal resistance (6) n/a PD Device power dissipation, Vcc1 = Vcc2 = 5.25 V, TJ = 150°C, CL = 15 pF, Input a 0.5 MHz 50% duty cycle square wave 42 (1) (2) (3) (4) (5) (6) 44.6 °C/W mW The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC1, VCC2 MIN TYP MAX UNIT Supply voltage - 3.3V Operation 3.15 3.3 3.45 V Supply voltage - 5V Operation 4.75 5 5.25 –4 IOH High-level output current IOL Low-level output current VIH High-level output voltage 2 VCC VIL Low-level output voltage 0 0.8 V TA Ambient Temperature -40 105 °C TJ (1) Junction temperature –40 136 1/tui Signaling rate 0 1 tui Input pulse duration 1 (1) mA 4 mA V °C Mbps µs To maintain the recommended operating conditions for TJ, see the Thermal Information table Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C Submit Documentation Feedback 3 ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 105°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP IOH = –4 mA; See Figure 1 VCC –0.8 4.6 IOH = –20 µA; See Figure 1 VCC –0.1 5 MAX V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 400 –10 VI = VCC or 0 V; See Figure 3 25 V mV 10 INx at 0 V or VCC UNIT µA µA 50 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.4 1 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 3 6 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 2 4 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 2 4 mA TYP MAX SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5 V ± 5%, TA = –40°C to 105°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 4 MIN See Figure 1 See Figure 1 9 14 ns 0.3 3.7 ns 4.9 ns 3.6 ns 1 See Figure 2 UNIT ns 1 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C PARAMETER VOH High-level output voltage TEST CONDITIONS IOH = –4 mA; See Figure 1 MIN TYP ISO7521C (5-V side) VCC –0.8 4.6 ISO7520C/7521C(3.3-V side) VCC –0.4 3 VCC –0.1 VCC IOH = –20 µA; See Figure 1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity MAX UNIT V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 V 400 mV µA 10 INx at 0 V or VCC –10 VI = VCC or 0 V; See Figure 3 25 µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.4 1 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 2 4.5 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 2 4 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 1.5 3.5 mA SWITCHING CHARACTERISTICS VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) See Figure 1 See Figure 1 See Figure 2 MIN TYP MAX 10 17 UNIT ns 0.5 5.6 ns 6.3 ns 4 ns 2 ns 2 ns 6 µs Also known as pulse skew. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C Submit Documentation Feedback 5 ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 105°C PARAMETER VOH High-level output voltage TEST CONDITIONS IOH = –4 mA; See Figure 1 MIN TYP ISO7520C/7521C (5-V side) VCC –0.8 4.6 ISO7521C (3.3-V side) VCC –0.4 3 VCC –0.1 VCC IOH = –20 µA; See Figure 1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity MAX V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 400 –10 VI = VCC or 0 V; See Figure 3 25 V mV 10 INx at 0 V or VCC UNIT µA µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.2 0.7 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 3 6 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 1.5 3.5 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 2 4 mA TYP MAX 10 17 ns 0.5 4 ns 8.5 ns 4 ns SWITCHING CHARACTERISTICS VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%, TA = –40°C to 105°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) 6 See Figure 1 See Figure 1 See Figure 2 MIN UNIT 2 ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C PARAMETER VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity TEST CONDITIONS MIN TYP IOH = –4 mA; See Figure 1 VCC –0.4 3 IOH = –20 µA; See Figure 1 VCC –0.1 3.3 MAX UNIT V IOL = 4 mA; See Figure 1 0.2 0.4 IOL = 20 µA; See Figure 1 0 0.1 V 400 mV µA INx at 0 V or VCC –10 VI = VCC or 0 V; See Figure 3 25 µA 40 kV/µs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 0.2 0.7 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 2 4.5 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 1.5 3.5 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCC or 0 V, 15 pF load 1.5 3.5 mA TYP MAX UNIT 12 20 ns 1 5 ns 6.8 ns 5.5 ns SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) See Figure 1 See Figure 1 See Figure 2 MIN 2 ns 2 ns 6 µs Also known as pulse skew. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C Submit Documentation Feedback 7 ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W VCC1 VI 1.4V 1.4V OUT 0V t PHL tPLH VO CL VOH 90% NOTE B NOTE A Vcc/2 VO 10% tf tr Vcc/2 VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3ns, tf ≤ 3ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI Vcc1 ISOLATION BARRIER Vcc1 0V IN or Vcc1 2.7 V VI OUT VO 0V tfs CL VOH 50% VO FAILSAFE HIGH VOL NOTE B A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms IN S1 C = 0.1 µF +1 % ISOLATION BARRIER V CC1 GND 1 V CC2 C = 0.1 µ F +1 % Pass-fail criteria – output must remain stable . OUT NOTE B V OH or V OL GND 2 V CM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit 8 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal to terminal distance through air 8.34 mm L(I02) Minimum external tracking (Creepage) Shortest terminal to terminal distance across the package surface 8.1 mm CTI Tracking resistance (Comparative Tracking DIN IEC 60112 / VDE 0303 Part 1 Index) ≥400 V Minimum internal gap (Internal Clearance) Distance through the insulation 0.014 mm RIO Isolation resistance, input to output (1) Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device CIO Barrier capacitance input to output (1) CI Input capacitance to ground (2) (1) (2) >1012 Ω VIO = 0.4 sin(2πft), f = 1 MHz 2 pF VI = Vcc/2 + 0.4 sin(2πft), f = 1 MHz, Vcc = 5 V 2 pF All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. empty para for space above the NOTE NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. IEC 60664-1 RATINGS TABLE PARAMETER Basic Isolation Group Installation Classification TEST CONDITIONS Material Group SPECIFICATION II Rated mains voltages <= 150 Vrms I - IV Rated mains voltages <= 300 Vrms I - IV Rated mains voltages <= 600 Vrms I - III Rated mains voltages <= 1000 Vrms I - II Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C Submit Documentation Feedback 9 ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com INSULATION CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIORM VPR TEST CONDITIONS SPECIFICATION Maximum working insulation voltage 1414 Input to output test voltage VIOTM Transient overvoltage VISO Isolation voltage per UL 1577 RS Insulation resistance Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial discharge < 5 pC 2262 Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC 2651 After Input/Output Safety Test Subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 1697 t = 60 sec (qualification) 6000 VTEST = VISO, t = 60 sec (qualification) 4243 VTEST = 1.2 × VISO, t = 1 sec (100% production) 5092 VTEST = 500 V at TS = 150°C >109 Pollution degree (1) (1) UNIT Vpeak Vpeak Vpeak Vrms Ω 2 For applications that require DC working voltages between GND1 and GND2, please contact Texas Instruments for further details. REGULATORY INFORMATION VDE TUV CSA UL Certified according to IEC 60747-5-2 Certified according to EN/UL/CSA 60950-1 & 61010-1 Recognized under 1577 Approved under CSA Component Component Recognition Acceptance Notice Program Basic Insulation Maximum Transient Overvoltage, 6000 VPK Maximum Working Voltage, 1414 VPK 5000 VRMS Reinforced Insulation, 400 VRMS maximum working voltage 5000 VRMS Basic Insulation, 600 VRMS maximum working voltage 5000 VRMS Reinforced insulation, 2 Means of Patient Protection at Single Protection, 4243 VRMS 125 VRMS per IEC 60601-1 (3rd Isolation Voltage Ed.) File Number: 40016131 Certificate Number: U8V 11 08 77311 006 File Number: 220991 File Number: E181974 IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER Is Safety input, output, or supply current Ts Maximum Case Temperature TEST CONDITIONS MIN TYP MAX θJA =79.9°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C 298 θJA =79.9°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C 453 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com Safety Limiting Current - mA 500 VCC1 and VCC2 at 3.45 V 400 300 VCC1 and VCC2 at 5.25 V 200 100 0 0 50 100 150 200 250 Case Temperature - °C Figure 4. DW-16 Theta-JC Thermal Derating Curve per IEC 60747-5-2 GND1 NC 0.1m F 2 mm max. from VCC1 VCC1 INA INB NC GND1 NC GND2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC 0.1m F 2 mm max. from VCC2 VCC2 OUTA OUTB NC NC GND2 ISO7520C Figure 5. Typical ISO7520C Application Circuit EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Figure 6. I/O Schematic Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C Submit Documentation Feedback 11 ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS INPUT VOLTAGE SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE FAIL-SAFE VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE 2.62 VIT+, 5 V 1.5 Fail-Safe Voltage Threshold − V Input Voltage Switching Threshold − V 1.6 1.4 VIT+, 3.3 V 1.3 1.2 1.1 VIT−, 5 V 1.0 VIT−, 3.3 V 0.9 0.8 −55 −35 −15 5 25 45 65 85 105 TA − Free-Air Temperature − °C FS+ 2.60 2.59 2.58 2.57 2.56 2.55 FS− 2.54 2.53 2.52 −55 125 −35 −15 25 45 65 85 105 125 G006 Figure 7. Figure 8. HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 80 IOL − Low-Level Output Current − mA TA = 25°C −10 −20 −30 −40 VCC1, VCC2 at 3.3 V −50 −60 −70 VCC1, VCC2 at 5 V −80 −90 TA = 25°C 70 60 VCC1, VCC2 at 5 V 50 40 VCC1, VCC2 at 3.3 V 30 20 10 0 0 1 2 3 4 5 VOH − High-Level Output Voltage − V 6 0 1 Submit Documentation Feedback 2 3 4 VOL − Low-Level Output Voltage − V G007 Figure 9. 12 5 TA − Free-Air Temperature − °C G005 0 IOH − High-Level Output Current − mA 2.61 5 6 G008 Figure 10. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com REVISION HISTORY Changes from Original (June 2010) to Revision A Page • Added PIN DESCRIPTION table .......................................................................................................................................... 2 • Changed tfs units in Switching Characteristics Table ............................................................................................................ 4 • Changed tfs units in Switching Characteristics Table ............................................................................................................ 5 • Changed tfs units in Switching Characteristics Table ............................................................................................................ 6 • Changed tfs units in Switching Characteristics Table ............................................................................................................ 7 • Changed Minimum internal gap limit from 0.016 to 0.014 mm. ............................................................................................ 9 • Deleted VIORM test conditions from INSULATION CHARACTERSISTCS table ................................................................. 10 • Added VPR parameter and Specifications in INSULATION CHARACTERSISTCS table ................................................... 10 • Changed VIOTM row of the INSULATION CHARACTERISTICS tables ............................................................................... 10 • Changed VISO Specifications in INSULATION CHARACTERISTICS table ........................................................................ 10 Changes from Revision A (September 2010) to Revision B Page • Changed 5th Features subbullets ......................................................................................................................................... 1 • Changed the first SWITCHING CHAR table, MAX value, 2nd row from 3.5 to 3.7 and third row from 4 to 4.9 .................. 4 • Changed the second SWITCHING CHAR table, MAX value, 2nd row from 4 to 5.6 and third row from 5 to 6.3 ............... 5 • Changed the third SWITCHING CHAR table, MAX value, 3rd row from 5 to 8.5 ................................................................ 6 • Changed the fourth SWITCHING CHAR table, MAX value, 3rd row from 6 to 6.8 .............................................................. 7 • Changed REGULATORY INFORMATION table , from: File Number: pending, to: File Number: E181974 ...................... 10 Changes from Revision B (June 2011) to Revision C Page • Changed all the devices numbers by adding a 'C' to the end .............................................................................................. 1 • Changed the Safety and Regulatory Approvals Feature ...................................................................................................... 1 • Changed the Description section .......................................................................................................................................... 1 • Changed the IEC 60664-1 Ratings Table ............................................................................................................................. 9 • Changed the INSULATION CHARACTERISTICS table ..................................................................................................... 10 • Changed the REGULATORY INFORMATION table .......................................................................................................... 10 Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7520C ISO7521C Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 26-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ISO7520CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7520CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7521CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7521CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO7521CDWR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7521CDWR SOIC DW 16 2000 533.4 186.0 36.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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