TI ISO7140FCC

ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
4242-VPK Small-Footprint and Low-Power Triple and Quad Channels Digital Isolators
Check for Samples: ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
FEATURES
APPLICATIONS
•
•
1
2
•
•
•
•
•
•
•
•
•
Maximum Signaling Rate: 50 Mbps (with 5V
Supplies)
Robust Design With Integrated Noise Filter
Default Output Low Option (Suffix F)
Low Power Consumption, Typical ICC per
Channel (with 3.3 V Supplies):
– ISO7131: 1.5 mA at 1 Mbps, 2.6 mA at 25
Mbps
– ISO7140: TBD at 1 Mbps, TBD at 25 Mbps
– ISO7141: TBD at 1 Mbps, TBD at 25 Mbps
Low Propagation Delay: 23 ns Typical (3.3 V
Supplies)
Wide Temperature Range: –40°C to 125°C
50 kV/µs Transient Immunity, Typical
Long Life with SiO2 Isolation Barrier
Operates From 2.7 V, 3.3 V and 5 V Supply and
Logic Levels
Small QSOP-16 Package
General-Purpose Isolation
– Industrial Fieldbus
– Profibus
– Modbus™
– DeviceNet Data Buses
– RS-232, RS-485
– Serial Peripheral Interface
SAFETY AND REGULATORY
APPROVALS
•
•
•
•
•
2500 VRMS Isolation for 1 minute per UL 1577
4242 VPK Isolation per DIN EN 60747-5-2 (VDE
0884 Teil 2), 566 VPK Working Voltage
CSA Component Acceptance Notice 5A
IEC 60950-1 and IEC 61010-1 End Equipment
Standard Approvals
All Approvals Pending
DESCRIPTION
ISO7131, ISO7140, and ISO7141 provide galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK
per VDE. ISO7131 has three channels with two forward and one reverse-direction channels. ISO7140 and
ISO7141 are quad-channel isolators; ISO7140 has four forward, ISO7141 has three forward and one reversedirection channel. These devices are capable of 50 Mbps maximum data rate with 5V supplies and 40Mbps
maximum data rate with 3.3V or 2.7V supplies, with integrated filters on the inputs for noise-prone applications.
The suffix F indicates that default output state is low; otherwise, the default output state is high (see Table 1).
Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier.
Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other
circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL
input thresholds and can operate from 2.7 V, 3.3 V, and 5 V supplies.
PRODUCT
STATUS
ISO7131CC
Released
ISO7140CC
Product Preview
ISO7140FCC
Product Preview
ISO7141CC
Product Preview
ISO7141FCC
Product Preview
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Modbus is a trademark of Gould Inc.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DEVICE INFORMATION
PIN CONFIGURATIONS
(TOP VIEW)
ISO7131
ISO7140
VCC2
VCC1
1
16
15
GND2
GND1
2
15
GND2
14
OUTA
3
14
OUTA
4
13
OUTB
INA
INB
4
13
OUTB
5
12
INC
INC
5
12
OUTC
6
11
NC
IND
6
11
OUTD
EN1
7
10
EN2
NC
7
10
EN
GND1
8
9
GND1
8
9
VCC1
1
16
GND1
2
INA
INB
3
OUTC
NC
GND2
VCC2
GND2
ISO7141
VCC1
1
16
GND1
2
15
GND2
VCC2
INA
INB
3
14
OUTA
4
13
OUTB
INC
5
12
OUTC
OUTD
6
11
IND
EN1
7
10
GND1
8
9
EN2
GND2
Space
2
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
Table 1. FUNCTION TABLE (1)
INPUT
VCC
OUTPUT
VCC
INPUT
(INx)
OUTPUT ENABLE
(ENx)
H
L
OUTPUT
(OUTx)
ISO71xxCC
ISO71xxFCC
H or open
H
H
H or open
L
L
X
L
Z
Z
L
PU
PU
Open
H or open
H
PD
PU
X
H or open
H
L
PD
PU
X
L
Z
Z
PU
PD
X
X
Undetermined
Undetermined
PU = Powered Up (VCC ≥ 2.7 V); PD = Powered Down (VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L
= Low Level; Z = High Impedance
(1)
AVAILABLE OPTIONS
RATED
ISOLATION
PRODUCT
INPUT
THRESHOLD
DEFAULT
OUTPUT
MAX DATA RATE
and
INPUT FILTER
ISO7131CC
CHANNEL
DIRECTION
MARKED
AS
2 forward,
1 reverse
7131CC
ORDERING
NUMBER
ISO7131CCDBQ (tube)
ISO7131CCDBQR (reel)
High
ISO7140CC (1)
ISO7140FCC
(1)
ISO7140CCDBQ (tube)
7140CC
4242 VPK
1.5-V TTL
(CMOS
compatible)
ISO7141CC (1)
Low
50 Mbps,
with noise filter
integrated
ISO7140CCDBQR (reel)
4 forward,
0 reverse
7140FC
High
ISO7140FCCDBQ (tube)
ISO7140FCCDBQR (reel)
ISO7141CCDBQ (tube)
7141CC
ISO7141CCDBQR (reel)
3 forward,
1 reverse
ISO7141FCC (1)
(1)
Low
7141FC
ISO7141FCCDBQ (tube)
ISO7141FCCDBQR (reel)
Product Preview
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
3
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
PARAMETER
VALUE
Supply voltage (2)
VCC1, VCC2
Voltage
INx, OUTx, ENx
Output current
IO
Electrostatic discharge
±15 mA
ESDA / JEDEC JS-001-2012
Field-induced charged device
model
JEDEC JESD22-C101E
Machine model
JEDEC JESD22-A115-A
TJ
Storage temperature
TSTG
(2)
–0.5 V to VCC+ 0.5 V
Human-body model
Maximum junction
temperature
(1)
–0.5 V to 6 V
±4 kV
All pins
±1.5 kV
±200 V
150°C
–65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
VCC1, VCC2
IOH
MIN
Supply voltage
2.7
High-level output current (VCC ≥ 3.0 V)
–4
High-level output current (VCC < 3.0 V)
–2
TYP
MAX
5.5
UNIT
V
mA
mA
IOL
Low-level output current
4
VIH
High-level input voltage
2
VCC
mA
V
VIL
Low-level input voltage
0
0.8
V
tui
Input pulse duration (VCC ≥ 4.5V)
20
tui
Input pulse duration (VCC < 4.5V)
25
1 / tui
Signaling rate (VCC ≥ 4.5V)
1 / tui
Signaling rate (VCC < 4.5V)
TJ
Junction temperature
TA
Ambient temperature
–40
ns
ns
0
50
Mbps
0
40
Mbps
–40
136
°C
125
°C
25
THERMAL INFORMATION
ISO7131, ISO714x
THERMAL METRIC (1)
DBQ (16 Pins)
UNIT
θJA
Junction-to-ambient thermal resistance
104.5
°C/W
θJC(top)
Junction-to-case(top) thermal resistance
57.8
°C/W
θJB
Junction-to-board thermal resistance
46.8
°C/W
ψJT
Junction-to-top characterization parameter
18.3
°C/W
ψJB
Junction-to-board characterization parameter
46.4
°C/W
θJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
°C/W
PD
Device power dissipation
150
mW
(1)
4
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF
Input a 25-MHz, 50% duty cycle square wave
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 1
VCCx
(1)
IOH = –20 μA; see Figure 1
VCCx
(1)
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage
hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCC or 0 V; see Figure 4
(1)
MIN
TYP
– 0.5
4.8
– 0.1
5
MAX
UNIT
V
IOL = 4 mA; see Figure 1
0.2
0.4
IOL = 20 μA; see Figure 1
0
0.1
V
450
mV
10
μA
–10
25
75
kV/μs
VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
PWD
tsk(o)
(1)
(2)
tsk(pp)
(3)
Propagation delay time
Pulse width distortion |tPHL – tPLH|
Channel-to-channel output skew time
Output signal rise time
tf
Output signal fall time
tPHZ, tPLZ
Disable propagation delay, high/low-to-high impedance output
tPZH, tPZL
Enable propagation delay, high impedance-to-high/low output
tfs
Fail-safe output delay time from input data or power loss
tGR
Input glitch rejection time
(3)
See Figure 1
MIN
TYP
12
19
MAX UNIT
35
3
Same-direction
channels
2
Opposite-direction
channels
4
Part-to-part skew time
tr
(1)
(2)
TEST CONDITIONS
ns
12
2
See Figure 1
ns
2
See Figure 2
See Figure 3
6
10
5
10
μs
9.5
8
11
ns
18
ns
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
5
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
SUPPLY CURRENT
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.2
3.7
UNIT
ISO7131
ICC1
Disable
ICC2
ICC1
EN1 = EN2 = 0V
DC to 1 Mbps
ICC2
ICC1
10 Mbps
ICC2
ICC1
25 Mbps
ICC2
ICC1
DC signal: VI = VCC or 0 V
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
50 Mbps
ICC2
3.7
5
2.2
3.7
3.7
5
3.4
4.8
4.9
6.6
4.9
6.6
6.8
9
7.1
10
10.5
13
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
ISO7140
ICC1
Disable
ICC2
ICC1
EN = 0 V
DC to 1 Mbps
ICC2
ICC1
10 Mbps
ICC2
ICC1
25 Mbps
ICC2
ICC1
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave
clock input; CL = 15 pF
50 Mbps
ICC2
mA
ISO7141
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
6
Disable
EN1 = EN2 = 0V
DC to 1 Mbps
10 Mbps
25 Mbps
50 Mbps
Submit Documentation Feedback
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square wave
clock input; CL = 15 pF
mA
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –4 mA; see Figure 1
VCCx
IOH = –20 μA; see Figure 1
VCCx
(1)
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCC or 0 V; see Figure 4
(1)
MIN
(1)
TYP
– 0.5
3
– 0.1
3.3
MAX
V
IOL = 4 mA; see Figure 1
0.2
0.4
IOL = 20 μA; see Figure 1
0
0.1
425
V
mV
10
–10
25
UNIT
50
μA
kV/μs
VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
Channel-to-channel output skew time
Output signal rise time
tf
Output signal fall time
tPHZ, tPLZ
Disable propagation delay, from high/low to
high-impedance output
tPZH, tPZL
Enable propagation delay, from highimpedance to high/low output
tfs
Fail-safe output delay time from input data or
power loss
tGR
Input glitch rejection time
(3)
See Figure 1
MIN
TYP
MAX
15
23
45
UNIT
3
Same-direction Channels
2
Opposite-direction
Channels
4
Part-to-part skew time
tr
(1)
(2)
TEST CONDITIONS
ns
19
2.5
See Figure 1
ns
2.5
6.5
15
6.5
15
See Figure 2
ns
See Figure 3
μs
8
9
12.5
22
ns
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
7
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
SUPPLY CURRENT
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.9
2.7
2.6
3.8
1.9
2.7
2.6
3.8
2.4
3.5
3.5
4.7
3.2
4.6
4.7
6.2
5
7
7
9
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
UNIT
ISO7131
ICC1
Disable
ICC2
ICC1
EN1 = EN2 = 0 V
DC to 1 Mbps
ICC2
ICC1
10 Mbps
ICC2
ICC1
25 Mbps
ICC2
ICC1
DC signal: VI = VCC or 0 V
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
ICC2
mA
ISO7140
ICC1
Disable
ICC2
ICC1
EN = 0 V
DC to 1 Mbps
ICC2
ICC1
10 Mbps
ICC2
ICC1
25 Mbps
ICC2
ICC1
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
ICC2
mA
ISO7141
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
8
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
40 Mbps
Submit Documentation Feedback
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
mA
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –2 mA; see Figure 1
VCC
(1)
IOH = –20 μA; see Figure 1
VCC
(1)
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 4
(1)
MIN
TYP
– 0.3
2.5
– 0.1
2.7
MAX
UNIT
V
IOL = 4 mA; see Figure 1
0.2
0.4
IOL = 20 μA; see Figure 1
0
0.1
V
350
mV
10
μA
-10
25
50
kV/μs
MIN
TYP
MAX
15
27
50
VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
Channel-to-channel output skew time
Output signal rise time
tf
Output signal fall time
tPHZ, tPLZ
Disable propagation delay, from high/low to highimpedance output
tPZH, tPZL
Enable propagation delay, from high-impedance to
high/low output
tfs
Fail-safe output delay time from input data or power loss
tGR
Input glitch rejection time
(3)
See Figure 1
UNIT
3
Same-direction Channels
2
Opposite-direction
Channels
4
Part-to-part skew time
tr
(1)
(2)
TEST CONDITIONS
ns
22
3
See Figure 1
ns
3
9
15
9
15
See Figure 2
ns
See Figure 3
μs
8.5
10
14
22.5
ns
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
9
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
SUPPLY CURRENT
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.2
2.4
2.3
3.3
1.2
2.4
2.3
3.3
2.1
3
2.9
4
3
3.8
4
5.2
4.2
5.3
5.8
7
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
UNIT
ISO7131
ICC1
Disable
ICC2
ICC1
EN1 = EN2 = 0 V
DC to 1 Mbps
ICC2
ICC1
10 Mbps
ICC2
ICC1
25 Mbps
ICC2
ICC1
DC signal: VI = VCC or 0 V
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
ICC2
mA
ISO7140
ICC1
Disable
ICC2
ICC1
EN = 0 V
DC to 1 Mbps
ICC2
ICC1
10 Mbps
ICC2
ICC1
25 Mbps
ICC2
ICC1
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
ICC2
mA
ISO7141
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
10
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
40 Mbps
Submit Documentation Feedback
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
mA
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
NOTE A
50 W
VI
VCC1
VI
VCC/2
OUT
VCC/2
0V
tPHL
tPLH
VO
CL
NOTE
B
VOH
90%
VO
50%
10%
tf
tr
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the input-generator signal. It is not
needed in an actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching-Characteristics Test Circuit and Voltage Waveforms
VCC
VCC
ISOLATION BARRIER
0V
R L = 1 k W ± 1%
IN
Input
Generator
VI
OUT
EN
VO
0V
tPLZ
tPZL
VO
CL
VCC/2
VCC/2
VCC
0.5 V
50%
VOL
NOTE
B
VI
50 W
ISOLATION BARRIER
NOTE A
IN
3V
Input
Generator
NOTE A
VI
VCC
OUT
VO
VCC/2
VI
VCC/2
0V
EN
CL
NOTE
B
50 W
tPZH
R L = 1 k W ± 1%
VO
VOH
50%
0.5 V
tPHZ
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
0V
Figure 2. Enable/Disable Propagation Delay-Time Test Circuit and Waveform
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
11
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VI
IN
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
A.
VCC
ISOLATION BARRIER
VCC
2.7 V
VI
OUT
0V
t fs
VO
fs high
VO
CL
NOTE A
VOH
50%
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay-Time Test Circuit and Voltage Waveforms
VCC1
VCC2
IN
S1
ISOLATION BARRIER
C = 0.1 mF ±1%
GND1
C = 0.1 mF ±1%
OUT
CL
NOTE A
Pass/Fail Criterion –
the output must
remain stable.
VOH or VOL
GND2
VTEST
A.
CL = 15pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit
12
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
DEVICE INFORMATION
INSULATION AND SAFETY-RELATED SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIOTM
Maximum transient overvoltage per
DIN EN 60747-5-2 (VDE 0884 Teil
2)
4242
VPK
VIORM
Maximum working voltage per DIN
EN 60747-5-2 (VDE 0884 Teil 2)
566
VPK
VTEST = VISO, t = 60 sec (qualification)
2500
VRMS
VTEST = 1.2 * VISO, t = 1 sec (100% production)
3000
VRMS
VISO
VPR
Isolation Voltage per UL 1577
Input-to-output test voltage
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
679
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial discharge < 5 pC
906
Method b1, 100% production test,
VPR = VIORM x 1.875, t = 1 s,
Partial discharge < 5 pC
VPK
1061
L(I01)
Minimum air gap (clearance)
Shortest terminal to terminal distance through air
3.7
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal to terminal distance across the
package surface
3.7
mm
Minimum internal gap (internal
clearance)
Distance through the insulation
0.014
mm
Pollution degree
Tracking resistance (comparative
tracking index)
CTI
RIO
(1)
CIO
(1)
CI
(1)
(2)
2
(2)
DIN IEC 60112 / VDE 0303 Part 1
Isolation Resistance, Input to Output
≥400
V
VIO = 500 V, TA < 100oC
>1012
o
Ω
>1011
VIO = 500 V, 100 C ≤ TA ≤ max
Barrier capacitance, input to output
VI = 0.4 sin (2πft), f = 1 MHz
2.3
pF
Input capacitance
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
2.8
pF
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
spacer
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
Table 2. IEC 60664-1 RATINGS TABLE
PARAMETER
Basic Isolation Group
Installation classification
TEST CONDITIONS
SPECIFICATION
Material Group
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
Rated mains voltage ≤ 400 VRMS
I–II
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
13
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
REGULATORY INFORMATION
VDE
UL
Certified according to DIN EN 60747-5-2
CSA
Recognized under 1577 Component
Recognition Program
Basic Insulation
Maximum Transient Overvoltage, 4242 VPK Single protection, 2500 VRMS
Maximum Working Voltage, 566 VPK
File number: 40016131 (approval pending)
(1)
Approved under CSA Component Acceptance
Notice
Reinforced Insulation per CSA 60950-1-03
and IEC 60950-1 (2nd Ed.), 150 VRMS
maximum working voltage
Basic Insulation per CSA 60950-1-03 and IEC
60950-1 (2nd Ed.), 380 VRMS maximum
working voltage
Reinforced Insulation per CSA 61010-1-04
and IEC 61010-1 (2nd Edition), 150 VRMS
maximum working voltage
(1)
File number: E181974 (approval pending)
File number: 220991 (approval pending)
Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
IS
TS
TEST CONDITIONS
Safety input, output, or supply
current
DBQ-16
MIN
TYP MAX
θJA = 104.5°C/W, VI = 5.5V, TJ = 150°C, TA = 25°C
217
θJA = 104.5°C/W, VI = 3.6V, TJ = 150°C, TA = 25°C
332
θJA = 104.5°C/W, VI = 2.7V, TJ = 150°C, TA = 25°C
443
Maximum case temperature
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the
ambient temperature plus the power times the junction-to-air thermal resistance.
Safety Limiting Current (mA)
500
Vcc1,2
2.7VV
V
2.7
CC1,2 atat
Vcc1,2
3.6VV
V
3.6
CC1,2 atat
V
5.5
Vcc1,2
5.5VV
CC1,2 atat
400
300
200
100
0
0
50
100
150
Tc - Case Temperature (ƒC)
200
C008
Figure 5. DBQ-16 θJC Thermal Derating Curve
14
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
2 mm
max. from
VCC1
2 mm
max. from
VCC2
VCC2
VCC1
ISO7131
0.1 mF
GND1
INA
0.1 mF
1
16
2
15
3
14
OUTA
OUTB
INB
4
13
OUTC
5
12
NC
EN1
GND2
INC
NC
6
11
7
10
8
9
EN2
GND1
GND 2
VCC1
2 mm
max. from
2 mm
max. from
VCC1
VCC2
VCC2
ISO7140
0.1 mF
GND1
0.1 mF
1
16
GND2
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
IND
6
11
NC
OUTD
EN
7
10
8
9
GND 2
GND1
Figure 6. Typical Application Circuits for ISO7131 and ISO7140
VCC1
2 mm
max. from
2 mm
max. from
VCC1
VCC2
VCC2
ISO7141
0.1 mF
0.1 mF
1
16
2
15
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
GND1
INA
OUTD
EN1
6
11
7
10
8
9
GND2
IND
EN2
GND1
GND 2
Figure 7. Typical Application Circuit for ISO7141
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
15
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
Note: For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
ISO71xxFCC Input
VCC1
VCC1
Output
500Q
IN
VCC2
7.5 uA
8Q
OUT
13Q
ISO71xxCC Input
VCC1
VCC1
VCC1
7.5 uA
500Q
IN
Figure 8. Device I/O Schematics
16
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
www.ti.com
SLLSE83 – APRIL 2013
TYPICAL CHARACTERISTICS
12.00
5.00
High-Level Output Voltage (V)
10.00
Supply Current (mA)
6.00
ICC1
3.3VV
ICC1 atat3.3
ICC2 atat3.3
ICC2
3.3VV
ICC1 atat5 5VV
ICC1
ICC2 atat5 5VV
ICC2
8.00
6.00
4.00
2.00
4.00
3.00
2.00
1.00
3.3V V
VVCC
3.3
CC atat
0.00
VVCC
5 5V V
CC atat
0.00
±1.00
-10
0
10
20
30
40
50
Data Rate (Mbps)
60
±15
Low-Level Output Voltage (V)
VCC
3.3VV
V
CC atat3.3
1.75
V
VCC
CC atat55VV
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0
5
10
15
Low-Level Output Current (mA)
VCC
Rising
V
CC Rising
2.46
2.42
2.40
2.38
2.36
2.34
±50
Pk-Pk Output Jitter (ns)
Propagation Delay Time (ns)
1
20
15
ttpLH
3.3
3.3VV
pLH atat
ttpHL
3.3
3.3VV
pHL atat
ttpLH
5 5VV
pLH atat
ttpHL
5 5VV
pHL atat
0
50
100
Free-Air Temperature (ƒC)
Figure 13. PROPAGATION DELAY TIME vs
FREE-AIR TEMPERATURE
Copyright © 2013, Texas Instruments Incorporated
50
100
150
C004
Figure 12. VCC UNDERVOLTAGE THRESHOLD vs
FREE-AIR TEMPERATURE
25
±50
0
Free-Air Temperature (ƒC)
C003
1.2
0
V
VCC
Falling
CC Falling
2.44
30
5
C002
2.48
Figure 11. LOW-LEVEL OUTPUT VOLTAGE vs
LOW-LEVEL OUTPUT CURRENT
10
0
±5
Figure 10. HIGH-LEVEL OUTPUT VOLTAGE vs
HIGH-LEVEL OUTPUT CURRENT
Power Supply Under Voltage Threshold (V)
Figure 9. ISO7131 SUPPLY CURRENT FOR ALL CHANNELS
vs DATA RATE
2.00
±10
High-Level Output Current (mA)
C001
0.8
0.6
0.4
0.2
Output Jitter at 5 V
Output Jitter at 3.3 V
0
150
C005
0
20
40
Data Rate (Mbps)
60
C006
Figure 14. OUTPUT JITTER vs DATA RATE
Submit Documentation Feedback
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
17
ISO7131CC, ISO7140CC, ISO7140FCC
ISO7141CC, ISO7141FCC
SLLSE83 – APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Input Glitch Rejection Time (ns)
18
16
14
12
10
8
6
4
ttGR
2.7VV
GR atat2.7
ttGR
3.3VV
GR atat3.3
ttGR
GR atat55VV
2
0
±50
0
50
100
150
Free-Air Temperature (ƒC)
18
C007
Figure 15. INPUT GLITCH REJECTION vs
FREE-AIR TEMPERATURE
Figure 16. TYPICAL EYE DIAGRAM AT 40 MBPS,
2.7-V OPERATION
Figure 17. TYPICAL EYE DIAGRAM AT 40 MBPS,
3.3-V OPERATION
Figure 18. TYPICAL EYE DIAGRAM AT 50 MBPS,
5-V OPERATION
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ISO7131CCDBQ
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7131CC
ISO7131CCDBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7131CC
ISO7140CCDBQ
PREVIEW
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7140CC
ISO7140CCDBQR
PREVIEW
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7140CC
ISO7141CCDBQ
PREVIEW
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7141CC
ISO7141CCDBQR
PREVIEW
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7141CC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated