AG8888 CALL WAITING DECODER I. GENERAL DESCRIPTION This is a Call Waiting decoder used on the telephone. Call Waiting service works by alerting a customer engaged in a telephone call to a new incoming call. Thus, the customer can still receive important calls while engaged in a current call. The Call Waiting decoder can detect dual-tone (2130Hz and 2750Hz) alert tone and generate a valid timing on the data pins for micro controller. II. FEATURES • • • • • • • Compatible with Bellcore special report SR-TSV-002476 3.6V ~ 6.0V supply voltage Call-Waiting (2130Hz plus 2750Hz) alert tone detector Sensitivity compensated by adjusting OP Amp Internal buffer Detection block for alert tone detected and digital algorithm detection Package series --- 14-pin DIP or 16-pin SOP (150 mil) AG8888AP for 14-pin DIP AG8888N for 16-pin SOP (150 mil) III. APPLICATION Feature phones, cordless phones and stand-alone product IV. PIN CONFIGURATION AG8888AP AG8888N TI/RI 1 14 OPO BO 2 13 AVDD F1 3 12 AVSS 4 OE TI/RI 1 16 OPO BO 2 15 AVDD DO F1 3 14 DO 11 NC AVSS 4 13 NC 5 10 DVDD OE 5 12 DVDD NC 6 9 OSCI NC 6 11 OSCI DVSS 7 8 OSCO DVSS 7 10 OSCO NC 8 9 * This specification are subject to be changed without notice. NC 8.8.2000 1 AG8888 CALL WAITING DECODER V. FUNCTIONAL BLOCK DIAGRAM OPO BO TI/RI Buffer FI Tone Filter Vdd/2 OSCI OSCO DO Detection Block OE Clock Generator Voltage Reference VI. PIN DESCRIPTIONS Pin TI/RI OE OSCI OSCO DO I/O I I I O O OPO BO FI AVDD DVDD AVSS DVSS NC O O I Description Tip in or Ring in should be connected with twisted pair Output enable for alert tone detected. High is enable. Low is for factory test. 480KHz crystal in 480KHz crystal out Alert tone detected output. Normal low. Under OE pin set to high, when call waiting alert tone is detected, this pin goes to high. Output of OP Amp Internal buffer output Band pass filer input Analog power. Digital power. Analog Ground. Digital Ground. Non connected VII. FUNCTIONAL DESCRIPTIONS Call Waiting service works by alerting a customer engaged in a telephone call to a new incoming call. Thus, the customer can still receive important calls while engaged in a current call. The call waiting decoder can detect alert tone (Call-Waiting Alerting Signal 2130Hz plus 2750Hz) and generate a valid timing on the data pins. The call waiting decoder is designed to support the Caller Number Deliver feature, which is offered by regional Bell Operating Companies. The call waiting decoder has four blocks, including OP Amp, band pass filter, and detection block. In a typical application, this IC receives Tip/Ring signals from twisted pairs. The signals as inputs of single-ended pre-amplifier (OP Amp and Buffer Amp), and the amplifier sends input signal to a band pass filter. Once the * This specification are subject to be changed without notice. 8.8.2000 2 AG8888 CALL WAITING DECODER signal is filtered, the detection block decodes the information and sends a valid timing to DO pin. The output data made available at DO pin. There is a OE pin to control DO pin's output enable. There is an external clamp circuit between internal buffer amplifier and filter. In order to get great alert tone detection and avoid false triggering while speech signal is coming, the external clamp circuit can restrict speech signal to (0.6Vp-p from TIP/RING. The input signal is call waiting alert tone signals. The DO pin is normal low. When OE pin set to high and this IC detects 2130Hz and 2750Hz frequency, then DO pin goes to high. Because OE pin set to low be for factory test, you should notice that the users don't set it to low. For this decoder, we put some external elements for performance concern. * This specification are subject to be changed without notice. 8.8.2000 3 AG8888 CALL WAITING DECODER DC ELECTRICAL CHARACTERISTIC VDD=5V, Vss=0V, Ta=25°C, fOSC=480KHz Sym. VDD Description operating supply voltage IDD VIL operating supply current low level input voltage VIH VOL high level input voltage low level output voltage Condition Min. 3.6 Typ. Max. 6 Unit V 3.3 1.5 1.5 mA V 3.5 load=1mA V V 0.4 VOH high level output voltage load=1mA Note: 1.both tones in the composite signal have equal amplitude. 4.6 V 2.tone pair is deviated by 0.5%. 3.addes a 0.1uf capacitor between Power and Ground. AC ELECTRICAL CHARACTERISTIC (VDD=+5V,Ta=+25°C) CHARACTERISTIC Input sensitivity ,VDD=+5V, Input G=1 Input frequency tolerance for 2130Hz Input frequency tolerance for 2750Hz * This specification are subject to be changed without notice. Min. Typ. -36 ±1.2 ±1.2 Max. Unit dBm % % 8.8.2000 4 AG8888 CALL WAITING DECODER WAVE FORM TIMING DO timing: line event normal on hook off hook engaged call alert tone (~80ms) Tvd Tinvd Tfinvd CAS Tvd=Tfvd+Tdvd Tinvd=Tfinvd+Tdinvd Tfvd Tdvd Tdinvd OSC timing: power off power on Power on/off Tosc OSC off OSCI OSC on (OSCO) Sym. Tfvd Tfinvd Tdvd Tdinvd Tvd Tinvd alert tone Tosc Description filter output signal valid delay filter output signal invalid delay digital delay of valid signal digital delay of invalid signal total delay of valid signal total delay of invalid signal input alert tone length (2130 ,2750 Hz @ -20dBm ) Oscillator enable delay time Min. Typ. 6 6 36 20 42 26 80 Max. Unit ms ms ms ms ms ms ms 10 ms Note: detected alert tone length shown above is assumed that no speech signals input. This test is under alert tone signal = -22dBm (600Ω) * This specification are subject to be changed without notice. 8.8.2000 5 AG8888 CALL WAITING DECODER APPLICATION CIRCUIT VDD DVDD 10 14 OPO 0.1u 100p AVDD 13 180k TIP 3300p 250V 5.6k 4700p 120k 1 1M 180k 0.1u RING 0.1u 56k 250V 4700p 4700p TI/RI DO 12 2 BO C1 3 FI OSCI 9 7 DVSS OSCO 8 4 AVSS 1M OE 5 150p Y1 480KHz C2 VDD 150p Note : Y1 KYOCERA KBR-480BKTS C1 150p C2 150p Analog Ground Digital Ground * This specification are subject to be changed without notice. Controller 8.8.2000 6 AG8888 CALL WAITING DECODER APPLICATION NOTE 1. VDD, GND To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the respective GND's. 2. OE pin Always connect OE to VDD for normal use. 3. 14 OPO R2 C1 TIP 250V 3300p 5.6k R1 RING C2 C6 100p R3 C3 4700p 180k 1N4148 R4 1 TI/RI 120k R6 56k R5 C4 1M 250V 0.1u 180k 2 BO 4700p C5 1N4148 3 FI 4700p In the application circuit above , some of the external element values are crucial. C2 value could not be less than 0.1uF. R2 = 5.6k is proper and you had better not to change it. The diode has to use Si type diode for noise consideration. There are an OP Amp. External resistors R3 and R4 can adjust the gain of OP Amp. The gain for OP Amp = -R4/ R3. 4. OPO pin This pin is the gain adjustment of OP Amp. See the partial application above. For high frequency noise immunity, the user can connect a 100pF capacitor between TI/RI pin and OPO pin. 5. OSCI pin, OSCI pin The clock generator input XIN pin and output XOUT need to connect a feedback resistor 1M( between them for proper operation. 6. About latch up It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON. * This specification are subject to be changed without notice. 8.8.2000 7