CXD1175AM/AP 8-bit 20MSPS Video A/D Converter (CMOS) Description The CXD1175A is an 8-bit CMOS A/D converter for video use. The adoption of a 2-step parallel system achieves low consumption at a maximum conversion speed of 20MSPS minimum, 35MSPS typical. Features • Resolution: 8 bit ± 1/2LSB (DL) • Maximum sampling frequency: 20MSPS • Low power consumption: 60mW (at 20MSPS typ.) (reference current excluded) • Built-in sampling and hold circuit • Built-in reference voltage self-bias circuit • 3-state TTL compatible output • Power supply: 5V single • Low input capacitance: 11pF • Reference impedance: 300Ω (typ.) Applications TV, VCR digital systems and a wide range of fields where high speed A/D conversion is required. Structure Silicon gate CMOS monolithic IC CXD1175AM 24 pin SOP (Plastic) CXD1175AP 24 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 7 V • Supply voltage VDD • Reference voltage VRT,VRB VDD + 0.5 to Vss – 0.5V • Input voltage VIN VDD + 0.5 to Vss – 0.5V (Analog) • Input voltage VI VDD + 0.5 to Vss – 0.5V (Digital) • Output voltage VO (Digital) • Storage temperature Tstg VDD + 0.5 to Vss – 0.5V –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVss 4.75 to 5.25 V DVDD, DVss | DVss – AVss | 0 to 100 mV • Reference input voltage VRB 0 and above V VRT 2.8 and below V • Analog input VIN 1.8Vp-p above • Clock pulse width TPW1, TPW0 23ns (min) to 1.1µs (max) • Operating ambient temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89321F78-PS CXD1175AM/AP Block Diagram and Pin Configuration 24 DVSS OE 1 Reference voltage 23 VRB DVSS 2 22 VRBS D0 (LSB) 3 D1 4 Lower data latches D2 5 Lower comparators with S/H (4 bit) Lower encoder (4 bit) D4 7 Lower comparators with S/H (4 bit) Lower encoder (4 bit) Upper data latches D6 9 Upper comparators with S/H (4 bit) Upper encoder (4 bit) D7 (MSB) 10 18 AVDD 17 VRT 16 VRTS 15 AVDD 14 AVDD DVDD 11 CLK 12 20 AVSS 19 VIN D3 6 D5 8 21 AVSS 13 DVDD Clock generator –2– CXD1175AM/AP Pin Description and Equivalent Circuits No. Symbol Equivalent circuit Description DVDD 1 OE When OE = Low, Data is output. When OE = High, D0 to D7 pins turn to High impedance. 1 DVSS 2, 24 Digital ground DVSS 3 to 10 D0 to D7 11, 13 DVDD Di D0 (LSB) to D7 (MSB) output Digital +5V DVDD 12 CLK Clock input 12 DVSS AVDD 16 Shorted with VRT generates, +2.6V. VRTS 16 AVDD 17 VRT Reference voltage (Top) 23 17 23 Reference voltage (Bottom) VRB AVSS 14, 15, 18 AVDD Analog +5V AVDD 19 VIN 19 Analog input AVSS 20, 21 Analog GND AVSS AVSS 22 Shorted with VRB generates +0.6V. VRBS 22 –3– CXD1175AM/AP Digital output Compatibility between analog input voltage and the digital output code is indicated in the chart below. Input signal voltage Step Digital output code MSB LSB VRT : : : : VRB 0 : 127 128 : 255 11111111 : 10000000 01111111 : 00000000 TPW1 TPW0 Clock Amalog input Data output N N+1 N–3 N–2 N+2 N–1 N+3 N N+4 N+1 Td = 18ns : Point for analog signal sampling. Timing Chart 1 tr = 4.5ns tf = 4.5ns 5V 90% OE input 2.5V 10% tPLZ 0V tPZL VOH Output 1 1.3V 10% VOL (≠DVSS) tPHZ tPZH VOH (≠DVDD) 90% Output 2 1.3V VOL Timing Chart 2 –4– CXD1175AM/AP Electrical Characteristics (Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Analog characteristics Item Symbol Conditions Min. Typ. Max. Unit 20 MSPS Conversion speed Fc VDD = 4.75 to 5.25V Ta = –40 to +85°C VIN = 0.5 to 2.5V fIN = 1kHz ramp Analog input band width (–1dB) BW Envelope Offset voltage∗1 EOT Potential difference to VRT –10 –35 –60 EOB Potential difference to VRB 0 +15 +45 Integral non-linearity error EL +0.5 +1.3 ±0.3 ±0.5 End point Differential non-linearity error ED Differential gain error DG Differential phase error DP Aperture jitter taj tsd Sampling delay NTSC 40 IRE mod ramp Fc = 14.3MSPS 0.5 MHz 18 mV LSB 1.0 % 0.5 deg 30 ps 4 ns ∗1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”. EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2LSB of the voltage when the output data changes from “11111111” to “11111110”. –5– CXD1175AM/AP (Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) DC characteristics Item Symbol Supply current IDD Reference pin current IREF Analog input capacitance CIN Reference resistance (VRT to VRB) RREF VRB1 Self-bias I VRT1 – VRB1 Self-bias II VRT2 Digital input voltage Digital input current VIH VIL IIH IIL IOL IOZH IOZL Min. Fc = 20MSPS NTSC ramp wave input 4.5 Shorts VRB and VRBS Shorts VRT and VRTS VRB = AGND Shorts VRT and VRTS VDD = 4.75 to 5.25V Ta = –40 to +85°C OE = VSS VDD = min OE = VDD VDD = max Typ. Max. Unit 12 17 mA 6.6 8.7 mA pF 11 VIN = 1.5V + 0.07Vrms VDD = max IOH Digital output current Conditions 230 300 450 0.60 0.64 0.68 1.96 2.09 2.21 2.25 2.39 2.53 3.5 1.0 VIH = VDD 5 VIL = 0V 5 VOH = VDD – 0.5V –1.1 VOL = 0.4V 3.7 Ω V V V µA mA VOH = VDD 16 VOL = 0V 16 µA (Fc = 20MSPS, VDD = 4.75 to 5.25V, VRB = 0.5V, VRT = 2.5V, Ta = –40 to +85°C) Timing Item Symbol Conditions Min. Typ. Max. Unit 18 30 ns Output data delay TDL With TTL 1 gate and 10pF load Tri-state output enable time tPZH tPZL tPHZ tPLZ RL = 1kΩ, CL = 20pF OE = 5V → 0V 3 7 13 ns RL = 1kΩ, CL = 20pF OE = 0V → 5V 7 15 26 ns Tri-state output disable time –6– CXD1175AM/AP Electrical Characteristics Measurement Circuit Integral non-linearity error Differential non-linearity error Offset voltage } 3-state output measurement circuit measurement circuit +V Measurement point DVDD S2 S1: ON IF A < B S2: ON IF B > A RL S1 To output pin –V VIN A<B A>B COMPARATOR A8 B8 to to A1 B1 A0 B0 8 DUT CXD1175A "0" DVM CL 8 BUFFER Note) CL includes the capacitance of the probe and others. "1" 8 CLK (20MHz) CONTROLLER Maximum operational speed Differential gain error Differential phase error } 000 · · · 00 to 111 · · · 10 measurement circuit 2.5V ERROR RATE Fc – 1kHz CX20202A-1 S.G. COUNTER H.P.F 0.5V 1 AMP VIN 8 CXD 1175A SIGNAL SOURCE IAE NTSC 40 IRE MODULATION TTL 1 10bit D/A 8 ECL 2 100 620 2 2.5V –5.2V BURST VECTOR SCOPE CLK 0 0.5V –40 S.G. (CW) SYNC 620 D.G D.P. TTL FC –5.2V ECL Digital output current measurement circuit 2.5V 0.5V RL VDD VRT VIN VRB CLK OE GND 2.5V IOL 0.5V VOL VDD VRT VIN VRB CLK OE GND + – –7– IOH VOH + – CXD1175AM/AP Timing Chart 3 Vi (1) Vi (2) Vi (3) Vi (4) Analog input External clock Upper comparators block S (1) Upper data Lower data B Digital output C (2) S (3) MD (1) RV (0) H (1) C (3) C (1) C (0) RV (3) S (3) H (3) C (3) LD (1) S (2) LD (–2) Out (–2) C (4) MD (3) RV (2) LD (–1) H (0) S (4) MD (2) RV (1) S (1) Lower data A Lower comparators B block S (2) MD (0) Lower reference voltage Lower comparators A block C (1) H (2) C (2) LD (0) Out (–1) S (4) H (4) LD (2) Out (0) Out (1) Operation (See Block Diagram and Timing Chart) 1. The CXD1175AM/AP is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom). –8– CXD1175AM/AP 2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. 3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. Operation Notes 1. VDD, VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the respective GND’s. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VRT and VRTS, VRB and VRBS, the self-bias function that generates VRT = 2.6V and VRB = 0.6V, is activated. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 18ns. 6. OE pin By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained. 7. About latch up It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON. –9– CXD1175AM/AP Application Circuit +5V R11 1k R12 1k IC1 µPC254 Q4 HC04 +5V Q5 R13 500 C6 47µ +5V C5 0.1µ R6 500 R3 Q2 500 R8 100 R7 500 R1 120 C3 47µ R4 1k R2 180 C12 0.1µ Q3 Q1 C1 470µ C10 0.1µ +12V C2 10µ V IN C9 47µ IC2 µPC254 +12V R5 2k –12V 13 12 14 11 15 10 D7 (MSB) 16 9 D6 17 8 D5 7 D4 6 D3 20 5 D2 21 4 D1 D0 (LSB) 18 19 C13 10p C4 0.1µ –12V C8 ∗ R10 75 R9 5k –12V CLK CLOCK IN C11 0.1µ ∗ : Ceramic Chip Condenser 0.1µF C7 47µ CXD1175AM/AP 22 3 23 2 24 1 +5V : Analog GND : Digital GND Note) It is necessary that AVDD and DVDD pins the common source of power supply. The gain of analog input signal can be variable by adjustment of value of R3. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXD1175AM/AP 8-bit 20MSPS ADC and DAC Evaluation Board The CXD1175AP/CXA1106P PCB is evaluation PCB for the 8-bit high speed and low power consumption CMOS A/D converter CXD1175AP and the 8-bit high speed bipolar D/A converter CXD1106P. This PCB features a high speed and low power consumption CMOS A/D converter, analog input buffer, clock buffer, latch and high speed bipolar D/A converter designed to fully enhance the performance of A/D and D/A converters. Block Diagram 8 CXD1175AP V REF ANALOG INPUT BUFFER/DRIVER V IN 8 DIGITAL CIRCUIT MOUNT PORTION ANALOG CIRCUIT MOUNT PORTION DATA LATCH CXA1106P V OUT CLOCK BUFFER ANALOG CIRCUIT MOUNT PORTION OSC SW Characteristics • Resolution • Maximum conversion rate • Digital input level • Supply voltage GND +5V CLOCK –5V 8bit 20MHz TTL level ±5.0V Supply voltage Item Min. Typ. +5V –5V Max. Unit 150 20 mA Analog input AC input voltage Item Gain (VIN = 2Vp-p input) Offset voltage Clock input TTL compatible Pulse width TCW1 TCW0 Min. Typ. Max. 0.5 2 0 5 25ns (min.) 25ns (min.) – 11 – Unit V Unnecessary during self-bias usage CXD1175AM/AP Analog Output (CXA1106) Item Analog output (RL > 10kΩ) Min. Typ. Max. Unit 0.9 1.0 1.1 V Output Format (CXD1175A) The table shows the output format of A/D converter. Input signal voltage Step VRT : : : : VRB 0 : 127 128 : 255 Digital output code MSB LSB 1 1 1 1 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 : 1 0 0 1 0 0 1 1 0 0 0 0 : Timing Chart Analog input Tpw0 External clock Tpw1 Tdc AD clock tPD (AD) AD output tDD Latch output DA input ts th DA clock DA output Item tPD (DA) Symbol Min. Typ. Max. Unit Clock high time TPW1 25 ns Clock low time TPW0 25 ns Clock delay Tdc Data delay AD tPD (AD) tDD tS th tPD (DA) Data delay (latch) Set up time Hold time Data delay DA 18 24 ns 30 ns 17 ns 10 ns 2 ns 11 – 12 – ns – 13 – R1 51 VR1 100 E C B C2785 R2 120 C1 470µ/6.3 INPUT GAIN ADJUST Q1 to Q5 (C2785) (RIN = 75Ω) VIDEO INPUT VRB ADJUST VR3 2k R5 390 R4 510 Q4 R3 680 Q1 R9 510 R6 2.2k Q2 R10 510 VR2 10k C12 47µ/10 C11 47µ/10 AVSS C2 22µ /16 R7 75 R8 2.2k Q3 AVSS Q5 AVDD INPUT BIAS ADJUST VR4 2k VRT ADJUST DAC OUTPUT C7 0.1 OUTPUT GAIN ADJUST C8 0.1µ CLK 9 10 DVSS VRB VRBS AVSS AVSS VIN AVDD VRT VRTS AVDD AVDD 24 23 22 21 20 19 18 17 16 15 14 13 NC 11 D6 12 DVDD AVDD 7 6 5 4 3 2 1 NC 8 VSS VDD VDD AVdl AVtl Vief AVSS (MSB) D7 C10 0.1 C13 47µ/10 C7 0.1 C5 0.1 C6 0.1 10µ/16 VR5 5k –5V +5V GND AVDD DVDD CXA1106 (DAC) CXD1175A (ADC) AVSS AVSS Vsel CLK 22µ/16 DVDD 11 D7 (MSB) 10 D6 9 D5 8 D4 7 D3 6 D2 5 D1 4 D0 (LSB) 3 DVSS 2 OE 1 12 13 NC 14 NC 21 NC D0 (LSB) 20 D1 19 D2 18 D3 17 D4 16 D5 15 22 23 24 DVSS DVDD C14 0.1µ DVSS DVDD CLK VDD CLK 14 13 12 11 10 9 8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 0.1µ 74S174 (Latch) 0.1µ 1 2 3 4 5 6 7 8 0.1µ 74S174 (Latch) 74S04 or 74HC04 (INV Buffer) Peripheral Circuit Board (Top View) VSS Clear VSS Clear VSS OSC SWITCH EXT/INT VDD OSC OUT 1 R11 75 EXTERNAL CLOCK INPUT 14 0.1 8 7 VSS (RIN = 75Ω) CXD1175AM/AP CXD1175AM/AP List of Parts resistor R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 VR1 VR2 VR3 VR4 VR5 51Ω 120Ω 680Ω 510Ω 390Ω 2.2kΩ 75Ω 2.2kΩ 510Ω 510Ω 75Ω 100Ω 10kΩ 2kΩ 2kΩ 5kΩ transistor Q1 Q2 Q3 Q4 Q5 2SC2785 2SC2785 2SC2785 2SC2785 2SC2785 IC IC1 IC2 IC3 74S174 74S174 74S04 oscillator OSC others connector BNC071 SW AT1D2M3 capacitor C1 470µF/6.3V (chemical) C2 22µF/16V (chemical) C3 0.01µF C4 10µF/16V (tamtalate) C5 0.1µF C6 0.1µF C7 0.1µF C8 0.1µF C9 0.1µF C10 0.1µF C11 47µF/10V (chemical) C12 47µF/10V (chemical) C13 47µF/10V (chemical) C14 0.1µF Method of Adjustment 1. Vgain (VR1) Gain adjustment of the analog input. 2. Voffset (VR2) Offset adjustment of the analog input. 3. Vref (VR3, VR4) Adjustment of the A/D converter reference voltage. VRB is adjusted at VR3, and VRT at VR4. Reference voltage is given with self-bias for PCB shipment. 4. Analog output gain (VR5) Full-scale voltage of the D/A converter output is adjusted. – 14 – CXD1175AM/AP Points on the PCB Pattern Layout 1. Layout so that digital current does not flow to analog GND (part 1). (See Component Side on page 19 for part 1.) 2. Capacitor C6 (between AVSS and AVDD) and capacitor C14 (between DVSS and DVDD) are important factors to enhance the CXD1175A performance. Those capacitors should feature good high frequency characteristics over 0.1µF (ceramic capacitor). Layout as close to the IC as possible. 3. Analog GND (AVSS) and Digital GND (DVSS) have a common voltage and a supply source. The DVSS of A/D converter (part 2) location as close to the voltage source is possible will give even better results. That is, a layout where the A/D converter is close to the voltage source is recommended. (See Component Side on page 19 for part 2.) 4. AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13) are provided in the CXD1175A, and a common voltage source should be used for them as for part 3. (See the paragraph for Latch Up Prevention.) (See Soldering Side on page 19 for part 3.) 5. The A/D converter samples analog signals at the falling edge of clock. Accordingly, clocks fed to the A/D converter should not be affected by jitter. 6. In this PCB, to evaluate A/D and D/A converters independently, an independent layout has been adopted for the analog GND of A/D and D/A converters, from the voltage generation source. For the user’s actual PCB even a common source poses no problems. For the CXA1106, as analog signals are output with the supply voltage as reference, take care not to let noise interfere with the analog VDD of D/A converter. – 15 – CXD1175AM/AP Notes on Operation 1. Reference voltage The self-bias function where VRT = 2.6V and VRB = 0.6V is available by shorting VRT and VRTS, VRB and VRBS in the CXD1175A. At the PCB, either self-bias or external reference voltage can be selected according to the way the jumper wire is connected. For shipment, the reference voltage is provided by the self-bias. Also, when reference voltage is to be provided from the exterior, adjust the dynamic range (VRT – VRB) to 1.8Vp-p or over. 2. Clock input There are two modes for the PCB clock input. 1) Through an external signal generator (external clock) 2) Using a crystal oscillator (internal clock) These two modes can be selected with a switch on the PCB. They are given from the external clock for shipment. 3. Peripheral through hole There is a number of through holes at the analog input, output and LOGIC areas. Those are used when additional circuits are to be mounted on the PCB circuit. 4 The two latch ICs (74S174) on the circuit diagram are not absolutely necessary for the A/D and D/A converter evaluation. That is, when the A/D converter output data is directly input to D/A converter input, normal operation is maintained. However, as A/D converter output data is hardly ever subject to D/A conversion without the digital signal processing, the PCB has been fitted with the 74S174 to show a layout example for digital signal processing IC. 5. Analog input buffer & driver block is designed to handle conventional video band signals. Accordingly, for tests involving frequencies higher than that, methods shown in the figure below are recommended. R7 75Ω 19 V IN 50Ω D1175A S.G. High frequency input measurement circuit – 16 – CXD1175AM/AP Latch Up Prevention The CXD1175A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources DVDD AVDD 14 11 13 18 15 AVDD +5V +5V DVDD C14 CXD1175A C6 AVSS DVSS 2 21 20 DIGITAL IC 24 AVSS DVSS b. When analog and digital supplies are from a common source (i) DVDD 14 11 13 18 15 AVDD DVDD C14 +5V CXD1175A C6 DIGITAL IC AVSS 20 21 DVSS 2 24 AVSS DVSS (ii) DVDD 14 11 13 18 15 AVDD DVDD C14 +5V CXD1175A C6 DIGITAL IC AVSS AVSS 20 DVSS 2 21 24 DVSS – 17 – CXD1175AM/AP 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources DVDD AVDD 14 11 13 18 15 AVDD +5V +5V DVDD CXD1175A C6 AVSS DVSS 2 21 20 AVSS DIGITAL IC 24 DVSS b. When analog and digital supplies are from common source (i) DVDD AVDD 14 11 13 18 15 AVDD +5V DVDD CXD1175A C6 DIGITAL IC AVSS DVSS 2 20 21 AVSS 24 DVSS (ii) DVDD AVDD 14 15 18 11 AVDD +5V CXD1175A AVSS AVSS 13 DVDD DIGITAL IC DVSS 2 20 21 24 DVSS – 18 – CXD1175AM/AP Silk Side Component side 1 Soldering side – 19 – CXD1175AM/AP Package Outline Unit: mm CXD1175AM 24PIN SOP (PLASTIC) + 0.4 15.0 – 0.1 + 0.4 1.85 – 0.15 24 13 6.9 + 0.2 0.1 – 0.05 12 0.45 ± 0.1 + 0.1 0.2 – 0.05 1.27 0.5 ± 0.2 1 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 ± 0.12 M PACKAGE STRUCTURE SONY CODE SOP-24P-L01 EIAJ CODE ∗SOP024-P-0300-A JEDEC CODE MOLDING COMPOUND EPOXY/PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER ALLOY / 42ALLOY PACKAGE WEIGHT 0.3g CXD1175AP + 0.1 05 0.25 – 0. 24PIN DIP(PLASTIC) + 0.4 30.2 – 0.1 10.16 13 1 + 0.3 8.5 – 0.1 24 0° to 15° 12 0.5 ± 0.1 + 0.4 3.7 – 0.1 Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. 3.0 MIN 0.5 MIN 2.54 1.2 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-24P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP024-P-0400 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 2.0g JEDEC CODE – 20 –