MP8775 CMOS 20 MSPS, 8-Bit, High Speed Analog-to-Digital Converter March 1999-4 FEATURES · · · · · · · · · · 8-Bit Resolution 20 MHz Sampling Rate DNL = +1/2 LSB, INL = +1 LSB (typ) Internal S/H Function Single Supply: 5 V VIN DC Range: 0 V to VDD VREF DC Range: 1 V to VDD Low Power: 85 mW typ. (excluding reference) Latch-Up Free ESD Protection: 2000 V Minimum · Power Down Available: MP8776 · 3 V Version: MP87L75 · Small 20 Pin SOIC Package APPLICATIONS · · · · · GENERAL DESCRIPTION Digital Color Copiers Cellular Telephones CCD’s Based Systems Hardware Scanners Video Capture Boards The designer can choose the internally generated reference voltages by connecting VRB to VRBS and VRT to VRTS, or provide external reference voltages to the VRB and VRT pins. The internal reference generates 0.6 V at VRB and 2.6 V at VRT. Providing external reference voltages allows easy interface to any input signal range between GND and VDD. This also allows the system to adjust these voltages to cancel zero scale and full scale errors, or to change the input range as needed. The MP8775 is an 8-bit Analog-to-Digital Converter in a small 20 pin SOIC package. Designed using an advanced 5 V CMOS process, this part offers excellent performance, low power consumption and latch-up free operation. This device uses a two-step flash architecture to maintain low power consumption at high conversion rates. The input circuitry of the MP8775 includes an on-chip S/H function and allows the user to digitize analog input signals between GND and VDD. Careful design and chip layout have achieved a low analog input capacitance. This reduces “kickback” and eases the requirements of the buffer/amplifier used to drive the MP8775. The device operates from a single +5 V supply. Power consumption is 85 mW at Fs = 20 MHz. Specified for operation over the commercial / industrial (--40 to +85°C) temperature range, the MP8775 is available in Surface Mount (SOIC), Shrunk Small Outline (SSOP) and Plastic dual-in-line (PDIP) packages. SIMPLIFIED BLOCK AND TIMING DIAGRAM VDD AVDD DVDD VRTS VRT MSB Comp. LSB Comp. VRB VRBS GND Latch Latch Encoder + Error Correction DB7 (MSB) F/F DB0 (LSB) Sample S/H Clock Logic VIN CLK CLK DB7DB0 AGND N N-3 N-2 DGND Rev. 3.01 E1999 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017 N-1 N MP8775 ORDERING INFORMATION Package Type Temperature Range Part No. DNL (LSB) INL (LSB) SOIC --40 to +85°C MP8775AS ¦3/4 ¦1 1/2 PDIP --40 to +85°C MP8775AN ¦3/4 ¦1 1/2 SSOP --40 to +85°C MP8775AQ ¦3/4 ¦1 1/2 PIN CONFIGURATIONS See Packaging Section for Package Dimensions DGND DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) DVDD 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 DGND VRB VRBS AGND VIN AVDD VRT VRTS DVDD CLK DGND DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) DVDD 20 Pin PDIP (0.300”) 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 DGND VRB VRBS AGND VIN AVDD VRT VRTS DVDD CLK 20 Pin SOIC (Jedec, 0.300”) 20 Pin SSOP PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. 11 NAME 1 DGND Digital Ground 2 DB0 Data Output Bit 0 (LSB) 12 DVDD Digital Power Supply 3 DB1 Data Output Bit 1 13 VRTS Generates 2.6 V if tied to VRT 4 DB2 Data Output Bit 2 14 VRT Top Reference 5 DB3 Data Output Bit 3 15 AVDD Analog Power Supply 6 DB4 Data Output Bit 4 16 VIN Analog Input 7 DB5 Data Output Bit 5 17 AGND Analog Ground 8 DB6 Data Output Bit 6 18 VRBS Generates 0.6 V if tied to VRB 9 DB7 Data Output Bit 7 (MSB) 19 VRB Bottom Reference 10 DVDD Digital Power Supply 20 DGND Digital Ground Rev. 3.01 2 CLK DESCRIPTION Sample Clock 03 (/(&75,&$/ &+$5$&7(5,67,&6 7$%/( 8QOHVV 2WKHUZLVH 6SHFLILHG $9 '9 9 9 9 9 7 q& '' 57 5% 9 )6 0+] 'XW\ &\FOH '' $ q& 3DUDPHWHU 6\PERO 0LQ )6 7\S 0D[ 8QLWV 7HVW &RQGLWLRQV&RPPHQWV .(< )($785(6 5HVROXWLRQ 0D[LPXP 6DPSOLQJ 5DWH %LWV 0+] $&&85$&< $ *UDGH 'LIIHUHQWLDO 1RQ/LQHDULW\ '1/ 'LIIHUHQWLDO 1RQ/LQHDULW\ '1/ ,QWHJUDO 1RQ/LQHDULW\ p p ,1/ =HUR 6FDOH (UURU (=6 )XOO 6FDOH (UURU ()6 p p /6% # 0+] /6% # 0+] /6% %HVW )LW /LQH 0D[ ,1/ 0LQ ,1/ /6% /6% 5()(5(1&( 92/7$*(6 3RVLWLYH 5HI 9ROWDJH 957 1HJDWLYH 5HI 9ROWDJH 95% 'LIIHUHQWLDO 5HI 9ROWDJH /DGGHU 5HVLVWDQFH $*1' 95() 5/ $9'' $9'' 9 9 57&2 6KRUW 95% DQG 95%6 95% 9 6KRUW 957 DQG 9576 95795% 9 957 9 /DGGHU 7HPS &RHIILFLHQW 95() 9 : 957 95% q SSP & 6HOI %LDV 6HOI %LDV 95% $*1' 6KRUW 957 DQG 9576 $1$/2* ,1387 ,QSXW %DQGZLGWK G% %: ,QSXW 9ROWDJH 5DQJH 9,1 ,QSXW &DSDFLWDQFH &,1 S) $SHUWXUH 'HOD\ W$3 QV 95% 0+] 957 9 ',*,7$/ ,13876 /RJLFDO ´µ 9ROWDJH 9,+ /RJLFDO ´µ 9ROWDJH 9,/ '& /HDNDJH &XUUHQWV 9 ,,1 &/. ,QSXW &DSDFLWDQFH 9 P$ S) 9,1 '*1' WR '9'' &ORFN 7LPLQJ 6HH )LJXUH )6 QV +LJK 3XOVH :LGWK &ORFN 3HULRG W3:+ QV /RZ 3XOVH :LGWK W3:/ QV ',*,7$/ 2873876 &287 S) /RJLFDO ´µ 9ROWDJH 92+ /RJLFDO ´µ 9ROWDJH 92/ 'DWD 9DOLG 'HOD\ 'DWD +ROG 7LPH 9 ,/2$' P$ 9 ,/2$' P$ W'/ QV W+/ QV 5HY MP8775 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Description Symbol 25°C Typ Min Max Units Conditions % ° FS = 4 x NTSC FS = 4 x NTSC V mA Does not include ref. current AC PARAMETERS Differential Gain Error Differential Phase Error dG dPH 2 1 VDD IDD 5 17 POWER SUPPLIES Operating Voltage (AVDD, DVDD)9 Current (AVDD + DVDD) 25 Notes: 1 Tester measures code transitions by dithering the voltage of the analog input (VIN ). The difference between the measured and the ideal code width (VREF /256) is the DNL error (Figure 2.). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 3.). Accuracy is a function of the sampling rate (FS). 2 Guaranteed. Not tested. 3 Specified values guarantee functionality. Refer to other parameters for accuracy. 4 --1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 See VIN input equivalent circuit (Figure 4.). Switched capacitor analog input requires driver with low output resistance. 6 All inputs have diodes to DVDD and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD . 7 tR , tF should be limited to >5 ns for best results. 8 Depends on the RC load connected to the output pin. 9 AGND and DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VRT & VRB . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5 V VIN . . . . . . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5 V All Inputs . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5 V All Outputs . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND --0.5 V Storage Temperature . . . . . . . . . . . . . . . . . . . --65 to +150°C Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C Package Power Dissipation Rating @ 75°C SOIC, SSOP, PDIP . . . . . . . . . . . . . . . . . . . . . . . 700 mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . . 9 mW/°C Notes: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. 3 VDD refers to AVDD and DVDD . GND refers to AGND and DGND. 1/FS tPWH tPWL N+1 CLK PIPELINE DELAY Sample “N” DATA N+2 N -- 3 N -- 2 N -- 1 t HL t DL Figure 1. MP8775 Timing Diagram Rev. 3.01 4 DATA N MP8775 DNL Output Codes LSB Best Fit Line 7 V(N+1) Real Transfer Line Analog Input 6 V(N) 5 N+1 Output Codes EFS INL 4 N Ideal Transfer Line 3 N--1 Code Width (N) = V(N+1) -- V(N) LSB = [ VRT -- VRB ] / 256 2 LSB 1 DNL(N) = [ V(N+1) -- V(N) ] -- LSB Analog Input (Volt) EZS Figure 3. INL Error Calculation Figure 2. DNL Measurement +5 V CLK CLK 5pF Analog Input 1.5pF VRT + VRB 2 AVDD 50W 0.1mF CLK VIN CLK 6 pF 0.1mF CLK 10mF VDD DB7 DB6 DB5 VRTS DB4 VRT DB3 MP8775 DB2 DB1 VRB DB0 VRBS VIN 0.1mF Digital Outputs 5pF AGND GND 1.5pF CLK Clock VIN [N--2] CLK Figure 4. Equivalent Input Circuit Figure 5. Typical Circuit Connections APPLICATION NOTES Signals should not exceed AVDD +0.5V or go below AGND --0.5V or DVDD +0.5 V or DGND --0.5 V. All pins have internal protection diodes that will protect them from short transients (<100ms) outside the supply range. capacitive coupling and reflections will contribute noise to the conversion. It is possible for the data valid delay (tDL) to be equal to or greater than the high pulse width of the sampling clock (tPWH), See Figure 1. This can cause timing related errors. For sample rates above 14 MSPS use only the rising edge of the sample clock (CLK) to latch data from the MP8775 to other parts of the system. The reference can be biased internally by shorting VRT to VRTS and VRB to VRBS. This will generate 0.6 V at VRB and 2.6 V at VRT (see Figure 5.). If the internal reference pins VRTS and/or VRBS are not used they should be left unconnected. AGND and DGND pins are connected internally through the P-- substrate. DC voltage differences between these pins will cause undesirable internal substrate currents. The power supply (AVDD) and reference voltage (VRT & VRB) pins should be decoupled with 0.1mF and 10mF capacitors to AGND, placed as close to the chip as possible. The digital outputs should not drive long wires or buses. The Rev. 3.01 5 MP8775 PERFORMANCE CHARACTERISTICS Graph 1. DNL vs. Sampling Frequency Graph 2. INL vs. Sampling Frequency Graph 3. Supply Current vs. Sampling Frequency Graph 4. Supply Current vs. Temperature Graph 5. Reference Resistance vs. Temperature Graph 6. SNR vs. Input Frequency Rev. 3.01 6 MP8775 Graph 7. SINAD vs. Input Frequency Graph 8. ENOB vs. Input Frequency Graph 9. THD vs. Input Frequency Rev. 3.01 7 MP8775 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1999 EXAR Corporation Datasheet March 1999 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 3.01 8