XRD87L75 Low-Voltage CMOS 8-Bit High-Speed Analog-to-Digital Converter April 2==2 1 FEATURES · ESD Protection: 2000V Minimum · 8-Bit Resolution · Small 20-Pin SOIC/SSOP Packages · Up to 10MHz Sampling Rate · Internal S/H Function · Single Supply: 3.3V · VIN DC Range: 0V to VDD · VREF DC Range: 1V to VDD · Low Power: 25mW typ. (excluding reference) APPLICATIONS · Digital Color Copiers · Cellular Telephones · CCD-Based Systems · Hardware Scanners · Video Capture Boards · Latch-Up Free GENERAL DESCRIPTION The XRD87L75 is an 8-bit Analog-to-Digital Converter in a small 20-pin SOIC/SSOP package. Designed using an advanced 3.3V CMOS process, this part offers excellent performance, low power consumption and latch-up free operation. This device uses a two-step flash architecture to maintain low power consumption at high conversion rates. The input circuitry of the XRD87L75 includes an on-chip S/H function and allows the user to digitize analog input signals between AGND and AVDD. Careful design and chip layout have achieved a low analog input capacitance. This reduces “kickback” and eases the requirements of the buffer/amplifier used to drive the XRD87L75. The designer can choose the internally generated reference voltages by connecting VRB to VRBS and VRT to VRTS , or provide external reference voltages to the VRB and VRT pins. The internal reference generates 0.4V at VRB and 1.72V at VRT. Providing external reference voltages allows easy interface to any input signal range between GND and VDD. This also allows the system to adjust these voltages to cancel zero scale and full scale errors, or to change the input range as needed. The device operates from a single +3.3V supply. Power consumption is 25mW at FS = 6MHz. Specified for operation over the commercial / industrial (-40 to +85°C) temperature range, the XRD87L75 is available in Surface Mount (SOIC), Shrink Small Outline (SSOP) and Plastic Dual-In-line (PDIP) Packages. SIMPLIFIED BLOCK AND TIMING DIAGRAM Rev. 1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 XRD87L75 ORDERING INFORMATION Package Type Temperature Range Part No. DNL (LSB) INL (LSB) SOIC -40 to +85°C XRD87L75AID +/-0.5 +/-1.5 PDIP -40 to +85°C XRD87L75AIP +/-0.5 +/-1.5 SSOP -40 to +85°C XRD87L75AIU +/-0.5 +/-1.5 PIN CONFIGURATIONS See Packaging Section for Package Dimensions 20-Pin PDIP (300 MIL) - P20 20-Pin SOIC (Jedec, 300 MIL) - D20 20-Pin SSOP (5.3mm) - U20 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 DGND Digital Ground 11 CLK Sample Clock 2 DB0 3 DB1 Data Output Bit 0 (LSB) 12 DVDD Digital Power Supply Data Output Bit 1 13 VRTS Generates 1.72V if tied to VRT 4 DB2 Data Output Bit 2 14 VRT Top Reference 5 DB3 Data Output Bit 3 15 AVDD Analog Power Supply 6 DB4 Data Output Bit 4 16 VIN Analog Input 7 DB5 Data Output Bit 5 17 AGND Analog Ground VRBS Generates 0.4V if tied to VRB 8 DB6 Data Output Bit 6 18 9 DB7 Data Output Bit 7 (MSB) 19 VRB Bottom Reference 10 DVDD Digital Power Supply 20 DGND Digital Ground Rev. 1.00 2 XRD87L75 ELECTRICAL CHARACTERISTICS TABLE UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 3.3V, FS = 6MHz (50% DUTY CYCLE), VRT = 2.5V, VRB = 0.5V, TA = 25°C 25°C Parameter Symbol Min FS 0.1 Typ Max Units 6 10 MHz Test Conditions/Comments KEY FEATURES Resolution 8 Sampling Rate Bits ACCURACY Differential Non-Linearity DNL +/-0.3 +/-0.5 LSB Integral Non-Linearity INL +/-0.75 +/-1.5 LSB Zero Scale Error EZS +3 LSB Full Scale Error EFS -2 LSB Best Fit Line (Max INL – Min INL)/2 REFERENCE VOLTAGES Positive Ref. Voltage VRT Negative Ref. Voltage VRB Differential Ref. Voltage3 Ladder Resistance Ladder Temp. Coefficient 2.5 AGND V REF 1.0 RL 245 AVDD V AVDD V 550 Ω 0.5 350 V RTCO 2000 ppm/°C Short VRB and VRBS VRB 0.4 V Short VRT and VRTS VRT-VRB 1.72 V VRT 1.5 V VREF = VRT – VRB Self Bias 1 Self Bias 2 VRB = AGND, Short VRT and VRTS ANALOG INPUT Input Bandwidth (–1 dB)2, 4 BW Input Voltage Range VIN Input Capacitance Aperture Delay 5 2 50 VRB MHz VRT V CIN 16 pF tAP 4 ns DIGITAL INPUTS Logical “1” Voltage VIH Logical “0” Voltage VIL DC Leakage Current 6 IIN 2.5 V 0.5 V VIN =DGND to DVDD CLK Input Capacitance 5 µA 5 pF Clock Timing ( See Figure 1.)7 Clock Period 1/FS 100 166 ns High Pulse Width tPWH 50 83 ns Low Pulse Width tPWL 50 83 ns Logical “1” Voltage VOH 2.5 Logical “0” Voltage VOL Data Valid Delay 8 t DL C OUT =15 pF DIGITAL OUTPUTS 0.5 12 Rev. 1.00 3 V I LOAD = 1 mA V I LOAD = 1 mA ns XRD87L75 ELECTRICAL CHARACTERISTICS TABLE (CONT'D) UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 3.3V, FS = 6MHz (50% DUTY CYCLE), VRT = 2.5V, VRB = 0.5V, TA = 25°C 25°C Parameter Symbol Min Typ Max Units Test Conditions/Comments AC PARAMETERS Differential Gain Error dG 2 % FS = 4 x NTSC Differential Phase Error dPH 1 Degree FS = 4 x NTSC POWER SUPPLIES Operating Voltage (AVDD, DVDD)9 VDD Current (AGND + DGND) I DD 3 3.3 3.6 V 8 12 mA Does not include ref. current NOTES 1. The difference between the measured and the ideal code width (VREF/256) is the DNL error (Figure 3). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 4). Accuracy is a function of the sampling rate (FS). 2. Guaranteed, not tested. 3. Specified values guarantee functionality. Refer to other parameters for accuracy. 4. –1dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5. See VIN input equivalent circuit (Figure 5). Switched capacitor analog input requires driver with low output resistance. 6. All inputs have diodes to DVDD and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD . 7. tR , tF should be limited to >5ns for best results. 8. Depends on the RC load connected to the output pin. 9. AGND & DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 VDD to GND ....................................................... 5.5V Storage Temperature .........................–65 to +150°C VRT & V RB ......................... VDD +0.5 to GND –0.5V Lead Temperature (Soldering 10 seconds) ... +300°C VIN ..................................... VDD +0.5 to GND –0.5V Package Power Dissipation Rating @ 75°C All Inputs ............................ VDD +0.5 to GND –0.5V PDIP, SOIC, SSOP .............................. 650mW All Outputs ......................... VDD +0.5 to GND –0.5V Derates above 75°C ............................. 9mW/°C NOTES: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100µA for less than 100ms. 3. VDD refers to AVDD and DVDD. GND refers to AGND and DGND. Rev. 1.00 4 XRD87L75 Figure 1. XRD87L75 Timing Diagram Figure 2. DNL Measurement Figure 3. INL Error Calculation Figure 4. Equivalent Input Circuit Figure 5. Typical Circuit Connections Rev. 1.00 5 XRD87L75 APPLICATION NOTES The digital outputs should not drive long wires or buses. The capacitive coupling and reflections will contribute noise to the conversion. Signals should not exceed AVDD +0.5V or go below AGND -0.5V or DVDD +0.5V or DGND -0.5V. All pins have internal protection diodes that will protect them from short transients (<100µs) outside the supply range. To avoid timing errors, use the rising edge of the sample clock (CLK) to latch data from the XRD87L75 to other parts of the system. AGND and DGND pins are connected internally through the P- substrate. DC voltage differences between these pins will cause undesirable internal substrate currents. The reference can be biased internally by shorting VRT to VRTS and VRB to VRBS. This will generate 0.4V at VRB and 1.72V at VRT (see Figure 5.). The power supply (AVDD) and reference voltage (VRT & VRB) pins should be decoupled with 0.1µF and 10µF capacitors to AGND, placed as close to the chip as possible. If the internal reference pins VRTS and/or VRBS are not used they should be left unconnected. 1.0 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz o Ta = 25 C 0.8 0.6 DNL (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 Code Graph 1. DNL vs. Code Rev. 1.00 6 160 192 224 256 XRD87L75 1.0 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz o Ta = 25 C 0.8 0.6 0.4 INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 Code Graph 2. INL vs. Code 1.0 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Ta = 25 oC 0.8 0.6 0.4 POS DNL DNL (LSB) 0.2 0.0 -0.2 NEG DNL -0.4 -0.6 -0.8 -1.0 0.10 1.00 10.00 Fs (MHz) Graph 3. DNLvs. Sampling Frequency Rev. 1.00 7 100.00 XRD87L75 1.0 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V o Ta = 25 C 0.8 INL (LSB) 0.6 0.4 0.2 0.0 0.10 1.00 10.00 100.00 Fs (MHz) Graph 4. Best Fit INL vs. Sampling Frequency 20 Ta = 25 oC 16 Vdd = 3.6V Vdd = 3.3V Idd (mA) 12 Vdd = 3.0V 8 Vdd = 2.7V 4 0 0 5 10 15 20 Fs (MHz) Graph 5. IDD vs. Sampling Frequency Rev. 1.00 8 25 30 XRD87L75 14 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V 12 10 Idd (mA) Fs = 10MHz 8 Fs = 6MHz Fs = 2MHz 6 4 2 0 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Graph 6. Supply Current vs. Temperature 550 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Ladder Resistance (ohm) 500 450 400 350 300 250 -60 -40 -20 0 20 40 Temperature (C) Graph 7. Ladder Resistance vs. Temperature Rev. 1.00 9 60 80 100 XRD87L75 50 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz Ta = 25oC 45 40 35 SNR (dB) 30 25 20 15 10 5 0 0.01 0.1 1 10 Fin (MHz) Graph 8. SNR vs. Input Frequency 50 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz Ta = 25oC 45 40 35 SINAD (dB) 30 25 20 15 10 5 0 0.01 0.1 1 Fin (MHz) Graph 9. SINAD vs. Input Frequency Rev. 1.00 10 10 XRD87L75 Graph 10. FFT Plot 80 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz Fin = 500KHz 60 40 Amplitude (dB) 20 0 -20 -40 -60 -80 -100 -120 0.0 0.5 1.0 1.5 Frequency (MHz) Graph 10. FFT Plot Rev. 1.00 11 2.0 2.5 3.0 XRD87L75 20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) REV. 1.00 20 11 1 10 E1 E D A2 Seating Plane A L α A1 B B1 e eA eB Note: The control dimension is the inch column INCHES SYMBOL MIN MAX MIN MILLIMETERS MAX A 0.145 0.210 3.68 5.33 A1 0.015 0.070 0.38 1.78 A2 0.115 0.195 2.92 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 0.925 1.060 23.50 26.92 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC eB 0.310 0.430 7.87 10.92 L 0.115 0.160 2.92 4.06 a 0° 15° 0° 15° Rev. 1.00 12 C XRD87L75 20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) REV. 1.00 D 20 11 E H 1 10 C A Seating Plane α e B A1 L NOTE: The control dimension is the millimeter column INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.496 0.512 12.60 13.00 E 0.291 0.299 7.40 7.60 e 0.050 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 a 0° 8° 0° 8° Rev. 1.00 13 XRD87L75 20 LEAD SHRINK SMALL OUTLINE PACKAGE (5.3 mm SSOP) REV. 2.00 D 20 11 E H 1 10 C A A2 Seating Plane α e B A1 L Note: The control dimension is the millimeter column INCHES SYMBOL MIN MAX MIN MILLIMETERS MAX A 0.067 0.079 1.70 2.00 A1 0.002 0.006 0.05 0.15 A2 0.065 0.073 1.65 1.85 B 0.009 0.015 0.22 0.38 C 0.004 0.010 0.09 0.25 D 0.272 0.296 6.90 7.50 E 0.197 0.221 5.00 e 0.0256 BSC 5.60 0.65 BSC H 0.292 0.323 7.40 8.20 L 0.022 0.037 0.55 0.95 a 0° 8° 0° 8° Rev. 1.00 14 XRD87L75 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2002 EXAR Corporation Datasheet April 2002 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00 15