FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • PERFORMANCE (1850 MHz) ♦ 27.5 dBm Output Power (P1dB) ♦ 17 dB Small-Signal Gain (SSG) ♦ 1.2 dB Noise Figure ♦ 42 dBm Output IP3 ♦ 50% Power-Added Efficiency ♦ Evaluation Boards Available ♦ Available in Lead Free Finish: FPD1500SOT89E • DESCRIPTION AND APPLICATIONS The FPD1500SOT89 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 x 1500 μm Schottky barrier Gate, defined by highresolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD1500 is available in die form and in other packages. Typical applications include drivers or output stages in PCS/Cellular base station highintercept-point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems. • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL Power at 1dB Gain Compression P1dB VDS = 5.0V; IDS = 50% IDSS 26.0 27.5 dBm Small-Signal Gain SSG VDS = 5.0V; IDS = 50% IDSS 15.5 17 dB Power-Added Efficiency PAE VDS = 5.0V; IDS = 50% IDSS 50 % NF VDS = 5.0V; IDS = 50% IDSS 1.2 POUT = P1dB Noise Figure VDS = 5.0V; IDS = 50% IDSS Output Third-Order Intercept Point IP3 (from 15 to 5 dB below P1dB) 38 1.5 dB 40 Matched for best P1dB dBm Matched for best IP3 at 50% IDSS 42 Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 750 mA Transconductance GM VDS = 1.3 V; VGS = 0 V 400 mS Gate-Source Leakage Current IGSO VGS = -5 V 1 15 μA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 1.5 mA 0.7 1.0 1.3 V Gate-Source Breakdown Voltage |VBDGS| IGS = 1.5 mA 12 16 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 1.5 mA 12 16 V Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis 375 465 550 mA Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Drain-Source Voltage VDS Gate-Source Voltage Max Units -3V < VGS < +0V 8 V VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward or reverse current 15 mA RF Input Power PIN Under any acceptable bias state 350 mW Channel Operating Temperature TCH Under any acceptable bias state 175 ºC Storage Temperature TSTG Non-Operating Storage 150 ºC Total Power Dissipation PTOT See De-Rating Note below 2.3 W Comp. Under any bias conditions 5 dB 2 or more Max. Limits 80 % 2 Gain Compression 3 Simultaneous Combination of Limits 1 Min -40 2 TAmbient = 22°C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Users should avoid exceeding 80% of 2 or more Limits simultaneously 3 Notes: • Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. • Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power • Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 2.3W – (0.015W/°C) x TPACK where TPACK = source tab lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65°C source lead temperature: PTOT = 2.3W – (0.015 x (65 – 22)) = 1.66W • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. • APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • BIASING GUIDELINES ¾ Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. ¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD1500SOT89. ¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 2.6 Ω for a 50% of IDSS operating point. ¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. • PACKAGE OUTLINE (dimensions in mm) PCB Foot Print Units in inches All information and specifications subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • TYPICAL TUNED RF PERFORMANCE Power Transfer Characteristic 3.50 29.00 Pout Comp Point 3.00 27.00 2.50 2.00 23.00 1.50 21.00 1.00 19.00 17.00 .50 15.00 .00 13.00 -2.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 Gain Compression (dB) Output Power (dBm) 25.00 -.50 16.00 Input Power (dBm) Drain Efficiency and PAE 70.00% 70.00% 60.00% 60.00% Eff. 50.00% 50.00% 40.00% 40.00% 30.00% 30.00% 20.00% 20.00% 10.00% 10.00% .00% -2.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 Drain Efficiency (%) PAE (%) PAE .00% 16.00 Input Power (dBm) Typical power, efficiency, and intermodulation performance is shown above. The devices were biased nominally at VDS = 5V, IDS = 50% of IDSS, at a test frequency of 2 GHz. The test devices were tuned (input and output tuning) for maximum output power at 1dB gain compression. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT Typical Intermodulation Performance VDS = 5V IDS = 50% IDSS at f = 1.85GHz -10.00 25.00 -20.00 Output Power (dBm) 23.00 -25.00 -30.00 21.00 -35.00 19.00 -40.00 -45.00 3rd Oder IM Poroducts (dBc) -15.00 17.00 -50.00 15.00 -55.00 -1.00 1.00 3.00 5.00 7.00 9.00 11.00 Input Power (dBm) Pout Im3, dBc Note: pHEMT devices exhibit non-classical intermodulation performance, with equivalent IPvalues exceeding 14 dB above P1dB. This IMD enhancement is affected by the quiescent bias current, the Drain-Source voltage, and the tuning or matching applied to the device. Maximum Stable Gain & S21 FPD1500SOT89 5V / 50%IDSS 35 MSG 30 MSG & 20 Mag S21 S21 25 15 10 5 0 0.5 Phone: +1 408 850-5790 Fax: +1 408 850-5766 1.5 2.5 3.5 4.5 5.5 Frequency (GHz) http://www.filtronic.co.uk/semis 6.5 7.5 8 Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5V, IDS = 50% IDSS) 0. 6 0. 8 Swp Max 159 1. 0 2. 0 0.4 3.0 22dBm 4.0 5.0 0.2 23dBm 24dBm 0 25dBm 10.0 0. 2 0. 0. 26dBm 6 4 0. 1. 8 0 2. 0 10 .0 3. 4. 5. 0 0 0 27dBm -10.0 28dBm -0.2 -5.0 -4.0 -3.0 -0.4 0. 6 0. 6 0. 8 0. 8 2. 0 1. 0 Swp Min 1 1. 0 Swp Max 123 2. 0 0.4 3.0 0.2 0. 2 0 4.0 5.0 23dBm 24dBm 25dBm 26dBm 0. 27dBm 4 0. 6 0. 1. 0 8 10.0 2. 0 10 .0 3. 4. 5. 0 0 0 28dBm -10.0 -0.2 -5.0 -4.0 22dBm -0.4 0. 6 Phone: +1 408 850-5790 Fax: +1 408 850-5766 0. 8 -3.0 2. 0 1. 0 1850 MHz Contours swept with a constant input power, set so that nominal P1dB is achieved at the point of optimum output match. Input (Source plane) Γs: 0.74 ∠ 168.2º 0.15 + j0.1 (normalized) 7.5 + j5.0 Ω Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown. 900 MHz Contours swept with a constant input power, set so that nominal P1dB is achieved at the point of optimum output match. Input (Source plane) Γs: 0.67 ∠ 103.6º 0.30 + j0.74 (normalized) 15 + j37.0 Ω Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown. Swp Min 1 http://www.filtronic.co.uk/semis Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • TYPICAL SCATTERING PARAMETERS (50Ω SYSTEM) See Website “More Info” for S-parameter design files. Swp Max 8GHz 6 GHz 5 GHz 2. 0 6 0. 0.8 1.0 FPD1500SOT89 5V / 50%IDSS 7 GHz 4 GHz 3. 0. 4 3.5 GHz 0 0 4. 3 GHz 5.0 0.2 10.0 5.0 4.0 3.0 2.0 1.0 0.8 0.6 2 GHz 0.4 10.0 0.2 0 2.5 GHz -10.0 1.52GHz -0. -4 .0 -5. 0 -3 .0 GHz Swp Min 0.5GHz -1.0 S11 -0.8 -0 .6 -2 .0 .41 -0 FPD1500SOT89 5V / 50%IDSS Swp Max 8GHz 1. 0 0. 8 0. 6 2. 0 0.4 3.0 5 GHz 4 GHz 0.2 6 GHz 4.0 7 GHz 5.0 3 GHz 0. 2 0 0. 10.0 0. 24 GHz 6 0. 8 1. 0 2. 0 10 .0 3. 4. 5. 0 0 0 1 GHz -10.0 -0.2 -5.0 -4.0 -3.0 -0.4 S22 Phone: +1 408 850-5790 Fax: +1 408 850-5766 0. 6 0. 8 2. 0 1. 0 Swp Min 0.5GHz http://www.filtronic.co.uk/semis Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • TYPICAL I-V CHARACTERISTICS DC IV Curves FPD1500SOT89 0.60 Drain-Source Current (A) 0.50 0.40 VG=-1.5V VG-1.25V VG=-1.00V VG=-0.75V VG=-0.5V VG=-0.25V VG=0V 0.30 0.20 0.10 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Drain-Source Voltage (V) Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits. Recommendation: Traditionally a device’s IDSS rating (IDS at VGS = 0V) was used as a predictor of RF power, and for MESFETs there is a correlation between IDSS and P1dB (power at 1dB gain compression). For pHEMTs it can be shown that there is no meaningful statistical correlation between IDSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression fails the F-statistic test. IDSS is sometimes useful as a guide to circuit tuning, since the S22 does vary with the quiescent operating point IDS. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • REFERENCE DESIGNS (0.9 & 1.85GHZ) Frequency Gain P1dB IP3 S11 S22 Vd Vg Id GHz dB dBm dBm dB dB V V mA Component Values 0.9 1.85 20 16 27 27 38 40 -5 -9 -15 -14 5 5 -0.4 to -0.6 -0.4 to -0.6 200 200 Component Lg Ld L1 L2 C1 0.9GHz 47nH 47nH 12nH 4.7nH 5.6pF 1.85GHz 27nH 27nH 1.5nH 4.7nH 2.2pF Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides ● Negative gate voltage required to be established before drain bias ● Use test clips at the bias vias at the top and bottom of the board for biasing Eval Board Layout Vg Vd + 1.0uF + 33pF 0.01uF 20O Lg 33pF 0.01uF 33pF Ld Q1 L1 C1 33pF L2 Eval board Schematic DCVS ID=V1 V=5 V DCVS ID=V2 V=-0.5 V RES ID=R1 R=20 Ohm CAP ID=C6 C=33 pF CAP ID=C2 C=33 pF IND ID=L4 L=Lg nH MLIN ID=TL9 W=98 mil L=105 mil IND ID=L2 L=Ld nH MLIN ID=TL13 W=35 mil L=95 mil IND ID=L3 L=L1 nH 3 2 PORT P=1 Z=50 Ohm Phone: +1 408 850-5790 Fax: +1 408 850-5766 MLIN ID=TL4 W=10 mil L=30 mil MLIN ID=TL11 W=10 mil L=30 mil MLIN ID=TL7 W=73 mil L=60 mil 1 MTEE ID=TL12 W1=98 mil W2=98 mil W3=40 mil MLIN ID=TL2 W=73 mil L=60 mil MLIN ID=TL6 W=35 mil L=153 mil 3 1 2 2 1 MTEE ID=TL5 W1=98 mil W2=98 mil W3=40 mil SUBCKT ID=S1 NET="FPD1500SOT89" http://www.filtronic.co.uk/semis CAP ID=C5 C=33 pF MTEE ID=TL1 W1=98 mil W2=98 mil W3=105 mil 1 CAP ID=C4 C=C1 pF CAP ID=C1 C=33 pF 2 PORT P=2 Z=50 Ohm 3 IND ID=L1 L=L2 nH Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • REFERENCE DESIGNS (2.4 & 2.6GHZ) Frequency Gain P1dB IP3 S11 S22 Vd Vg Id GHz dB dBm dBm dB dB V V mA Component Values 2.4 2.6 12 11.5 28 27.5 41 40 -6 -16 -5 -5 5 5 -0.4 to -0.6 -0.4 to -0.6 200 200 Component Lg Ld L1 L2 C1 C2 2.4GHz 22nH 22nH 1.0nH 3.3nH 1.8pF 1.0pF 2.6GHz 18nH 18nH Tab 3.9nH 1.0pF 1.0pF Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides ● Negative gate voltage required to be established before drain bias ● Use test clips at the bias vias at the top and bottom of the board for biasing Eval Board Layout Vg Vd 33pF 0.01uF 20O Lg 33pF 0.01uF 33pF Q1 L1 + 1.0uF + Ld C2 33pF L2 C1 Eval board Schematic DCVS ID=V1 V=5 V DCVS ID=V2 V=-0.5 V RES ID=R1 R=20 Ohm CAP ID=C6 C=33 pF CAP ID=C2 C=33 pF IND ID=L4 L=Lg nH MTEE ID=TL3 W1=98 mil W2=98 mil W3=105 mil 1 PORT P=1 Z=50 Ohm 3 CAP ID=C3 C=C1 pF Fax: +1 408 850-5766 MLIN ID=TL13 W=35 mil L=95 mil IND ID=L3 L=L1 nH 2 Phone: +1 408 850-5790 IND ID=L2 L=Ld nH 3 2 MLIN ID=TL4 W=10 mil L=30 mil MLIN ID=TL11 W=10 mil L=30 mil MLIN ID=TL7 W=73 mil L=60 mil 1 MTEE ID=TL12 W1=98 mil W2=98 mil W3=40 mil MLIN ID=TL2 W=73 mil L=60 mil CAP ID=C5 C=33 pF MLIN ID=TL6 W=35 mil L=153 mil 3 1 2 MTEE ID=TL1 W1=98 mil W2=98 mil W3=105 mil 1 CAP ID=C1 C=33 pF 2 2 1 MTEE ID=TL5 W1=98 mil W2=98 mil W3=40 mil SUBCKT ID=S1 NET="FPD1500SOT89" http://www.filtronic.co.uk/semis CAP ID=C4 C=C2 pF PORT P=2 Z=50 Ohm 3 IND ID=L1 L=L2 nH Revised11/11/05 Email: [email protected] FPD1500SOT89 LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT • STATISTICAL SAMPLE OF RF PERFORMANCE Noise Figure Small Signal Gain 5000 4000 Count Count 6000 14000 12000 10000 8000 6000 4000 2000 0 3000 2000 1000 13 14 15 16 17 0 18 0.6 Gain (dB) 0.7 0.9 1 1.1 1.2 1.3 NF (dB) rd Output Power at 1dB Gain Compression Output 3 -Order Intercept Point 14000 6000 12000 5000 10000 4000 Count Count 0.8 8000 6000 3000 2000 4000 1000 2000 0 0 23 24 25 26 27 30 28 32 34 36 38 40 42 44 IP3 (dBm) P1dB (dBm) The histograms above represent a sample of over 20,000 representative devices. The devices were tested by a high-speed automatic test system, in a matched circuit based on the EB1500SOT89AA Evaluation Board design (see the Website for a schematic). This circuit is a dual-bias single-pole lowpass topology, and the devices were biased at VDS = 4.5V, IDS = 120mA. The performance data is summarized below: Parameter Median Standard Deviation Test Limit CPK Small-Signal Gain 15.5 0.20 14.5 1.7 Noise Figure 0.91 0.03 1.20 3.2 Output Power (P1dB) 25.2 0.25 24.5 0.93 3rd-Order Intercept 38.7 1.1 36.5 0.67 Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised11/11/05 Email: [email protected]