FPD4000AS 2.5W PACKAGED POWER PHEMT • • PERFORMANCE (1.8 GHz) ♦ 34.5 dBm Output Power (P1dB) ♦ 12 dB Power Gain (G1dB) ♦ 45 dBm Output IP3 ♦ 8V Operation ♦ 50% Power-Added Efficiency ♦ Evaluation Boards Available ♦ Design Data Available on Website ♦ Suitable for applications to 5 GHz SEE PACKAGE OUTLINE FOR MARKING CODE DESCRIPTION AND APPLICATIONS The FPD4000AS is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), optimized for power applications in L-Band. The surface-mount package has been optimized for low parasitics. Typical applications include drivers or output stages in PCS/Cellular base station transmitter amplifiers, as well as other power applications in WLL/WLAN amplifiers. • ELECTRICAL SPECIFICATIONS AT 22°C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 1.8 GHz USING CW SIGNAL Power at 1dB Gain Compression P1dB VDS = 8V; IDQ = 700 mA 33.5 34.5 10.5 12 dBm ΓS and ΓL tuned for Optimum IP3 Power Gain at dB Gain Compression G1dB VDS = 8V; IDQ = 700 mA ΓS and ΓL tuned for Optimum IP3 Maximum Stable Gain MSG S21/S12 VDS = 8V; IDQ = 700 mA 18 dB 50 % -46 dBc PIN = 0dBm, 50Ω system Power-Added Efficiency PAE VDS = 8V; IDQ = 700 mA ΓS and ΓL tuned for Optimum IP3 at 1dB Gain Compression rd 3 -Order Intermodulation Distortion IM3 ΓS and ΓL tuned for Optimum IP3 VDS = 8V; IDQ = 700 mA POUT = 23 dBm (single-tone level) Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V Maximum Drain-Source Current IMAX Transconductance 1.9 2.3 2.65 mA VDS = 1.3 V; VGS ≅ +1 V 3.6 mA GM VDS = 1.3 V; VGS = 0 V 2.4 mS Gate-Source Leakage Current IGSO VGS = -3 V 70 170 µA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 8 mA 0.9 1.4 V 0.7 Gate-Source Breakdown Voltage |VBDGS| IGS = 8 mA 6 10 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 8 mA 20 22 V Thermal Resistivity (channel-to-case) ΘCC See Note on following page 16 °C/W Phone: +1 408 850-5790 Fax: +1 408 850-5766 http:// www.filtronic.co.uk/semis Revised: 05/26/05 Email: [email protected] FPD4000AS 2.5W PACKAGED POWER PHEMT • RECOMMENDED OPERATING BIAS CONDITIONS Drain-Source Voltage: From 5V to 8V Quiescent Current: From 400 mA to 750 mA • ABSOLUTE MAXIMUM RATINGS1 Parameter Symbol Test Conditions Drain-Source Voltage VDS Gate-Source Voltage Max Units -3V < VGS < +0V 12 V VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward / Reverse current +20/-20 mA PIN Under any acceptable bias state 575 mW Channel Operating Temperature TCH Under any acceptable bias state 175 ºC Storage Temperature TSTG Non-Operating Storage 150 ºC Total Power Dissipation PTOT See De-Rating Note below 9.0 W Comp. Under any bias conditions 5 dB RF Input Power 2 Gain Compression 3 Min -40 Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22°C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously % 1 Notes: • Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. • Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power • Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 9.0 - (0.0625W/°C) x TPACK where TPACK = source tab lead temperature above 22°C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 55°C source lead temperature: PTOT = 9.0 - (0.0625 x (55 – 22)) = 6.94W • For optimum heatsinking, metal-filled through (Source) via holes should be used directly below the central metallized ground pad on the bottom of the package. • Note on Thermal Resistivity: The nominal value of 16°C/W is measured with the package mounted on a large heatsink with thermal compound to ensure adequate (unsoldered) contact. The package temperature is referred to the Source leads. • HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. This product has be tested to Class 1A (> 250V but < 500V) using JESD22 A114, Human Body Model, and to Class A, (< 200V) using JESD22 A115, Machine Model. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http:// www.filtronic.co.uk/semis Revised: 05/26/05 Email: [email protected] FPD4000AS 2.5W PACKAGED POWER PHEMT • BIASING GUIDELINES ¾ Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. ¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD1000AS. ¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 3.25 Ω for the recommended 200mA operating point. ¾ The recommended 200mA bias point is nominally a Class AB mode. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. • PACKAGE OUTLINE AND RECOMMENDED PC BOARD LAYOUT (dimensions in millimeters – mm) PACKAGE MARKING CODE Example: f1ZD P1F f = Filtronic 1ZD = Lot / Date Code P1F = Status, Part Code, Part Type All information and specifications subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http:// www.filtronic.co.uk/semis Revised: 05/26/05 Email: [email protected]