TPS62510 www.ti.com SLVS651 – MAY 2006 1.5-A, LOW VI HIGH EFFICIENCY STEP-DOWN CONVERTER FEATURES • • • • • • • • • DESCRIPTION 1.8-V to 3.8-V Input Voltage Range Up to 96% High Efficiency Synchronous Step-Down Converter 1.5-MHz Fixed Frequency PWM Operation 1% Output Voltage Accuracy in Fixed Frequency PWM Mode Power Save Mode Operation for High Efficiency Over the Entire Load Current Range 22-µA Quiescent Current Fixed and Adjustable Output Voltage Output Voltage Tracking (OVT) for Reliable Sequencing Available in a 10-Pin QFN (3 x 3 mm) Package The TPS62510 family are high-efficiency step-down converters targeted for operation from a 1.8-V to 3.8-V input voltage rail, ideally suited for 2-cell Alkaline or NiMHd applications. The TPS62510 is also ideal as a point-of-load regulator running from a fixed 3.3-V, 2.5-V or 1.8-V input voltage rail. The converter operates in fixed frequency PWM mode switching at 1.5 MHz with the MODE pin high. Pulling the MODE pin low enables the high efficiency mode. In high efficiency mode, the device operates with a 1.5 MHz fixed frequency PWM at nominal load current, and automatically enters the Power Save Mode at light load currents. For maximum system reliability, the converter features Output Voltage Tracking using the OVT pin to allow sequencing, and to allow for the output voltage to track an external voltage applied to this pin. APPLICATIONS Portable Devices (Mobile Phone, PDA) 2-Cell NiMHd/Alkaline Applications Hard Disc Drives Point-Of-Load Regulation Notebook Computers WiMAX and WLAN Applications VI 1.8 V to 3.8 V C1 22 mF TPS62510 10 Rf 1 W Cf 100 nF 9 6 5 7 PVIN SW AVIN FB EN PG OVT MODE AGND PGND L1 1 2.2 mH 4 C3 22 pF 8 3 2 VO 1.5 V to 1.5 A 95 VI = 1.9 V (Mode Low) 90 R1 300 kW R2 200 kW C2 22 mF 85 Efficiency - % • • • • • • VI = 2.4 V (Mode Low) 80 75 VI = 1.9 V (Mode High) 70 VI = 2.4 V (Mode High) VI = 3.2 V (Mode Low) 65 VI = 3.2 V (Mode High) 60 55 VO = 1.2 V 50 0.01 0.1 1 10 100 1k 10 k IL - Load Current- mA Figure 1. Typical Application Figure 2. Efficiency vs Load Current Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPS62510 www.ti.com SLVS651 – MAY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA VOLTAGE OPTION 10-PIN QFN PACKAGE (1) (DRC) PACKAGE MARKING Adjustable TPS62510DRC BQA -40°C to 85°C (1) (2) Fixed (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Contact the local sales office for fixed output voltage options. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VS (1) VALUE UNIT Supply voltage at PVIN, AVIN –0.3 to 4 V Voltage at EN, MODE, OVT, FB, PG (2) –0.3 to 4 V -0.3 to VI + 0.3 V Voltage at SW (2) Continuous total power dissipation See the Dissipation Rating Table Continuous Power Dissipation TJ Operating junction temperature range -40 to 150 °C Tstg Storage temperature, -65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS (1) (1) PACKAGE RTHJA TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING DRC 50 °C/W 2W 1.1 W 0.8 W See the electrical graphs regarding power dissipation. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VI Input voltage range on pins PVIN and AVIN 1.8 3.8 V VO Output voltage range 0.6 VI V IO Output current, VI = 1.8 V to 3.6 V L Inductor value 2.2 µH CI Input capacitor value (1) 10 µF 1500 value (1) mA µF CO Output capacitance TA Operating ambient temperature -40 85 °C TJ Operating junction temperature –40 125 °C (1) See the application section for more information. 2 22 Submit Documentation Feedback TPS62510 www.ti.com SLVS651 – MAY 2006 ELECTRICAL CHARACTERISTICS VIN = 3.3 V, OVT = EN = VIN, MODE = GND, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage range I(q) Power Save Mode quiescent current AVIN + PVIN 1.8 FB = FB nominal + 5%, MODE = low 3.8 V 22 30 µA PWM Mode quiescent current into AVIN MODE = high 4.4 5 mA I(SD) Shutdown current into PVIN + AVIN EN = low, SW = GND 0.1 5 µA UVLO Undervoltage lockout threshold on AVIN V(AVIN) falling 1.55 1.58 (1) Undervoltage lockout hysteresis Thermal shutdown threshold T(SD) Increasing junction temperature Thermal shutdown hysteresis V 150 mV 160 °C 20 °C CONTROL SIGNALS EN, MODE VIH High level input voltage VIL Low level input voltage IIB Input bias current VI = 1.8 V to 3.8 V V 0.01 MODE synchronization range f(sync) 1.2 1.15 Duration of high or low level for synchronization signal (2) 0.4 V 0.1 µA 2.25 MHz 75 ns OUTPUT VOLTAGE TRACKING (OVT) IIB Input bias current VOS OVT offset voltage 0.001 VOS = V(OVT) - V(FB), 0.1 V < V(OVT) < 0.5 V -15 0.05 µA 15 mV POWER GOOD (PG) Power Good threshold V(th) Feedback voltage rising Power Good Hysteresis -7% VO -5% VO 2% VO VOL Low level voltage I(PG) = 1 mA Ilkg Power Good leakage current V(PG) = 3.8 V 1 -3% VO V 7% VO V 0.3 V 100 nA OUTPUT rDS(on) P-channel MOSFET on-resistance Ilkg P-channel leakage current VI = V(GS) = 1.8 V Ilkg N-channel leakage current V(DS) = 3.6 V IF Forward current limit (P- and N-channel) 1.8 V < VI < 3.8 V fs Oscillator frequency MODE = high Vref Reference voltage IFB tSS (1) (2) (3) 170 10 VI = V(GS) = 1.8 V N-channel MOSFET on-resistance Feedback regulation voltage 120 VI = 3.6 V rDS(on) VFB 330 VI = V(GS) = 3.3 V 200 VI = V(GS) = 3.3 V 1.75 2.00 2.25 A 1.3 1.5 1.7 MHz 10 5 VI = VO + 0.3 V ; 0 mA ≤ IO ≤ 1.5 A MODE = high (forced PWM operation) -1 1 V(FB) = 0.6 V, EN = high VI = VO + 0.3 V (min 1.8 V) to 3.8 V; IO = 800 mA Load Regulation IO = 10 mA to 1500 mA Soft start time VO ramping from 5% to 95% of nominal value Leakage resistance from SW pin to GND VI > VO, 0 V ≤ V(SW) ≤ VI Leakage resistance from FB pin to GND EN = low µA V -2 Line Regulation mΩ 130 VI = VO + 0.3 V ; 0 mA ≤ IO ≤ 1.5 A MODE = low (PFM / PWM) Feedback bias current µA 80 0.6 (3) mΩ % 0.001 0.05 µA 0 %/V 0.1 %/A 750 µs 700 1000 17 23 kΩ The undervoltage lockout threshold is detected at the AVIN pin. Current through the RC filter causes a UVLO trip at higher VI The minimum and maximum duty cycle applied to the MODE pin is calculated as: D(min) = 75 ns × f(sync) and D(max) = 1 - 75 ns × f(sync). When using the output voltage tracking function, the feedback regulates to the voltage applied to OVT as long as the OVT < 0.6 V. Submit Documentation Feedback 3 TPS62510 www.ti.com SLVS651 – MAY 2006 PIN ASSIGNMENT DRC Package (Top View) A. 1 10 PVIN PGND 2 9 AVIN AGND 3 8 PG FB 4 7 MODE OVT 5 6 EN Exposed Thermal Die (Note A) SW The exposed Thermal Die is connected to AGND. TERMINAL FUNCTIONS TERMINAL NAME 4 NO. I/O DESCRIPTION SW 1 Switch pin of the converter. The inductor is connected here. PGND 2 Power ground for the converter AGND 3 Analog ground connection FB 4 I Feedback voltage sense input. Connect directly to VO or to the midpoint of an external voltage divider for the adjustable version. OVT 5 I Output Voltage Tracking input. The signal applied to this pin is used as reference voltage overiding the internal reference voltage when it is below the internal 0.6-V reference. If this feature is not used, the OVT pin is connected to VI. EN 6 I Enable pin. A logic high enables the regulator, a logic low disables the regulator. This pin needs to be terminated and not left floating. MODE 7 I This pin is used to force fixed frequency PWM operation or to synchronize the device to an external clock signal. With MODE = high, the device is forced into 1.5-MHz fixed frequency PWM operation. With MODE = low, the device automatically enters the Power Save Mode at light load currents. PG 8 O Power Good indication. This is a open drain output that is low when the device is disabled or the output voltage drops 10% below target. AVIN 9 Power supply for control circuitry. Must be connected to the same voltage supply as PVIN through RC filter. PVIN 10 Input voltage for the power stage. VIN must be connected to the same voltage supply as AVIN. PowerPAD™ C2 Connect the PowerPAD to analog ground AGND. Submit Documentation Feedback TPS62510 www.ti.com SLVS651 – MAY 2006 FUNCTIONAL BLOCK DIAGRAM PG MODE PVIN Q3 PLL High Side Current Sense 1.5 MHz SawTooth 0.6 V (See Note A) R1 Summing Comparator Q1 VOUT Generator Loop Error Amplifier Compensation EN FB R2 Vref 0.6 V Vref 0.6 V Analog Softstart Low Side Current Sense PFM/PWM Transition Vref 0.6 V Vref - 2% Bandgap Undervoltage Lockout Thermal Shutdown R3 Output Voltage Tracking R4 EN Q4 AGND A. SW Q2 PFM Comparator AVIN MOSFET Driver Anti Shoot Through Converter Control Logic 0.6 V OVT PGND R1 and R2 are only used for the fixed output voltage version. Submit Documentation Feedback 5 TPS62510 www.ti.com SLVS651 – MAY 2006 TYPICAL CHARACTERISTICS Table of Graphs FIGURE η Efficiency vs Load current 3, 4 (1) I(q) No load quiescent current vs Input voltage 5, 6 f Frequency vs Temperature rDS(on) (1) 7 Line transient response 8 (1) Load transient response (mode = high) 9 (1) Load transient response (mode = low) 10 (1) Falling load transient (mode = low) 11 (1) Rising load transient (mode = low) 12 (1) Power Save Mode Operation, VOUT 13 (1) Start-up, VOUT 14 (1) P-CHannel (PMOS) vs Input voltage 15 N-Channell (NMOS) vs Input voltage 16 FB Offset vs Input Voltage on OVT 17 Generated with the circuit in Figure 1 with L1 = 2.2 µH (Wuerth 74455022). EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 95 100 95 VI = 3.2 V (Mode Low) 90 85 Efficiency - % Efficiency - % 85 80 VI = 3.2 V (Mode High) 75 VI = 3.6 V (Mode Low) 70 VI = 2.4 V (Mode Low) 80 75 VI = 1.9 V (Mode High) 70 VI = 2.4 V (Mode High) VI = 3.2 V (Mode Low) 65 VI = 3.6 V (Mode High) 65 VI = 3.2 V (Mode High) 60 60 55 VI = 1.9 V (Mode Low) 90 VO = 2.5 V 55 VO = 1.2 V 50 0.01 0.1 1 10 100 1k 10 k 50 0.01 1 10 100 IL - Load Current- mA IL - Load Current- mA Figure 3. 6 0.1 Figure 4. Submit Documentation Feedback 1k 10 k TPS62510 www.ti.com SLVS651 – MAY 2006 NO LOAD QUIESCENT CURRENT vs INPUT VOLTAGE NO LOAD QUIESCENT CURRENT vs INPUT VOLTAGE 30 6 Mode = Low Mode = High 28 5 24 I(q) - Quiescent Current - mA I(q) - Quiescent Current - mA 26 o 85 C 22 o 25 C 20 o -40 C 18 16 14 o 25 C o 85 C 4 o -40 C 3 2 1 12 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 0 1.6 1.8 2 2.2 2.4 2.6 2.8 VI - Input Voltage - V 3 3.2 3.4 3.6 3.8 VI - Input Voltage - V Figure 5. Figure 6. FREQUENCY vs TEMPERATURE LINE TRANSIENT RESPONSE 1610 1600 VI = 3.8 V f - Frequency - kHz 1590 VI = 3 V to 3.6 V (500 mV/div) 1580 VI = 3.3 V 1570 1560 1550 1540 VI = 1.8 V 1530 VO (50 mV/div AC Coupled) 1520 1510 -40 -20 0 20 40 60 80 t - Time = 500 ms/div o Temperature - C Figure 7. Figure 8. Submit Documentation Feedback 7 TPS62510 www.ti.com SLVS651 – MAY 2006 LOAD TRANSIENT RESPONSE MODE = HIGH LOAD TRANSIENT MODE = LOW VO (20 mV/div) VO (50 mV/div) IL = 150 mA to 1300 mA IL = 150 mA to 1300 mA (500 mA/div) (500 mA/div) t - Time = 1 ms/div t - Time = 1 ms/div Figure 9. Figure 10. FALLING LOAD TRANSIENT RESPONSE MODE = LOW RISING LOAD TRANSIENT RESPONSE MODE = LOW VO (50 mV/div) VO (50 mV/div) IL = 1300 mA to 150 mA (500 mA/div) IL = 150 mA to 1300 mA (500 mA/div) t - Time = 20 ms/div t - Time = 20 ms/div Figure 11. 8 Figure 12. Submit Documentation Feedback TPS62510 www.ti.com SLVS651 – MAY 2006 POWER SAVE MODE OPERATION SOFT START-UP VO = 1.8 V V(EN) (5 V/div) VO (20 mV/div) V(SW) (2 V/div) VO = 1.8 V (1 V/div) I(AVIN) and I(PVIN) (500 mA/div) IL = 150 mA (500 mA/div) t - Time = 200 ms/div Figure 13. Figure 14. PMOS rDS(on) vs INPUT VOLTAGE NMOS rDS(on) vs INPUT VOLTAGE 0.25 0.2 o 85 C 0.15 o 25 C 0.1 o -20 C 0.05 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 rDS(on) - Static Drain-Source On-State Resistance - W rDS(on) - Static Drain-Source On-State Resistance - W t - Time = 2 ms/div 0.2 0.15 o 85 C o 25 C 0.1 o -20 C 0.05 0 1.6 1.8 VI - Input Voltage - V 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 VI - Input Voltage - V Figure 15. Figure 16. Submit Documentation Feedback 9 TPS62510 www.ti.com SLVS651 – MAY 2006 FB OFFSET vs VOLTAGE ON VOUT 15 10 o 25 C o -40 C FB Offset - mV 5 o 85 C 0 -5 OVT £ 0.6 V, VI = 2.4 V, IO = 1 mA -10 0 0 0.1 0.2 0.3 0.4 Voltage on OVT - V Figure 17. 10 Submit Documentation Feedback 0.5 0.6 TPS62510 www.ti.com SLVS651 – MAY 2006 DETAILED DESCRIPTION The TPS62510 has two target areas of operation. The high efficiency area is defined when the MODE pin is held low. In this condition, the converter operates at typically 1.5-MHz fixed frequency PWM (pulse width modulation) at moderate to heavy load currents. At light load currents, the converter automatically enters power save mode and operates with PFM (pulse frequency modulation). Low noise operation is defined when the MODE pin is held high. In this condition, the converter is forced into fixed frequency PWM mode and runs at 1.5 MHz. The converter is capable of delivering 1.5-A output current. The TPS62510 can also be synchronized to an external clock in the frequency range between 1.15 MHz and 2.25 MHz. Synchronization is aligned with the falling edge of the incoming clock signal. This allows simple synchronization of two step-down converters running 180° out of phase reducing overall input RMS current. During PWM operation, the converters use a unique fast response voltage mode control scheme with input voltage feed-forward to achieve good line, and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead time, which is used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel rectifier, and turning on the P-channel switch. Power Save Mode operation (MODE) When the MODE pin is connected to GND, the device automatically enters the power save mode when the average output current reaches the appropriate threshold. This reduces the switching frequency and minimum quiescent current, maintaining efficiency over the entire load current range. For low noise operation, the device can be forced into fixed frequency PWM mode operating at 1.5 MHz over the entire load current range. This is done by pulling the Mode pin high. Many applications require a low output ripple voltage during power save mode. This is accomplished by a single threshold PFM comparator which allows control of the output voltage ripple in power save mode. The larger the output capacitor value, the smaller the output voltage ripple (see Figure 13). During power save mode, the device monitors the output voltage with the PFM comparator. As soon as the output voltage falls below the nominal output voltage, the device starts switching for a minimum of 1 µs (typical), or until the output voltage is above the nominal output voltage. Power Save Mode Transition Thresholds To achieve an accurate transition into and out of power save mode, the device monitors the average inductor current which is equal to the average output current. The device enters power save mode when the average output current is ≤ I(PFM enter) as calculated in Equation 1. VIN I(PFM enter) = (1) 22 W The device leaves the power save mode when the output current is ≥ I(PFM enter). VIN I(PFM leave) = (2) 17 W To minimize any delay times during a load transients, the device enters PWM mode when the output voltage is 2% below the nominal value, and the PFM/PWM transition comparator trips. Output Voltage Tracking (OVT) In applications where a processor or FPGA is powered, it is important that the I/O voltage and core voltage start-up in a controlled way to avoid possible processor and FPGA latch-up. To implement this, the TPS62510 has an Output Voltage Tracking feature where the internal reference voltage for the error amplifier follows the voltage applied to OVT, until OVT reaches Vref. Vref is the nominal internal reference voltage, typically 0.6 V. The tracking feature is available with the fixed output voltage version as well as with the adjustable output voltage version. Figure 18 shows a typical application where an external voltage (V1) is applied to OVT pin using a resistor divider. Submit Documentation Feedback 11 TPS62510 www.ti.com SLVS651 – MAY 2006 DETAILED DESCRIPTION (continued) VI 1.8 V to 3.8 V TPS62510 10 Rf 1 W C1 10 mF 9 6 Cf 100 nF V1 Output of External DC-DC Converter e.g. I/O Rail 5 R3 300 kW 7 1 SW PVIN AVIN FB EN PG L1 2.2 mH V2 1.5 V to 1.5 A C3 22 pF 4 R1 300 kW C2 22 mF 8 OVT AGND MODE PGND R2 200 kW 3 2 R4 200 kW Figure 18. Output Voltage Tracking, V2 Tracks V1 In this application, the output voltage (V2) of the TPS6251x tracks the voltage (V1) as long as the OVT voltage is smaller then the internal device reference voltage, Vref = 0.6 V. Depending on the resistor divider (R3, R4), the tracking can be adjusted. V2 can rise faster, at the same timer, or slower than V1. Voltage V1 V2 R3 R4 < R1 R2 Time Figure 19. V2 Comes Up Before V1 Simultaneous tracking is achieved when the resistor divider (R3/R4) is equal to the resistor divider of the TPS65210. R3 = R4 V2 - Vref 1.5 V - 0.6 V = Vref V2(tracking) = V(OVT) x = 1.5 0.6 V V2 Vref (3) = V1 x R4 R3 + R4 x V2 Vref = V1 200 k 300 k + 200 k x 1.5 V 0.6 V = V1 (4) Equation 3 and Equation 4 are used with the fixed and adjustable version of the TPS6251x. If V2 needs to rise before V1, then R4 must be increased as shown in Figure 20. V1 Voltage V2 R3 R4 = R1 R2 Time Figure 20. Simultaneous Tracking of V2 and V1 12 Submit Documentation Feedback TPS62510 www.ti.com SLVS651 – MAY 2006 DETAILED DESCRIPTION (continued) If V2 needs to rise after V1, then R4 must be decreased as shown in Figure 21. Voltage V1 V2 R3 R4 > R1 R2 Time Figure 21. V2 Comes Up After V1 Soft Start The converter has an internal soft start circuit that limits the inrush current during start-up. The soft start is realized by using a low current to control the output of the error amplifier during startup. The soft start time is typically 750 µs to ramp the output voltage to 95% of the final target value. There is a short delay of typically 120 µs between the converter being enabled and switching activity actually starting. See the typical soft start characteristic shown in Figure 14. 100% Duty Cycle Low Dropout Operation The TPS62510 converter offers a low input to output voltage difference while maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the entire battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current and output voltage, and in Equation 5. VI min = VO min + IO max x (rDS(on) max + RL ) (5) with: IOmax = maximum load current (Note: ripple current in the inductor is zero under these conditions) rDS(on)max = maximum P-channel switch rDS(on) RL = dc resistance of the inductor VOmin = nominal output voltage minus 2% tolerance limit Power Good The power good output can be used for sequencing purposes, enabling a separate regulator once the output voltage is reached, or to indicate that the output voltage is in regulation. When the device is disabled, the PG pin is pulled low by the internal open-drain output transistor. Internally, the TPS62510 compares the feedback voltage FB to the nominal reference voltage of typically 0.6 V. If the feedback voltage is more than 95% of this value then the power good output goes high impedance. If the feedback voltage is less than 90% of the reference voltage then PG pin is pulled low. Undervoltage Lockout The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages. It disables the converter. The UVLO circuit monitors the AVIN pin, the falling threshold is set internally to 1.55 V with 150-mV hysteresis. Note that when the dc-dc converter is running, there is an input current at the AVIN pin, which is up to 5 mA when in PWM mode. This current must be taken into consideration if an external RC filter is used at the VCC pin to remove switching noise from the TPS62510 internal analog circuitry supply. Submit Documentation Feedback 13 TPS62510 www.ti.com SLVS651 – MAY 2006 DETAILED DESCRIPTION (continued) Short-Circuit Protection The TPS62510 monitors the forward current through both the high-side and low-side power devices. This enables the converter to limit the short-circuit current, which helps to protect the device and other circuits connected to its output. Thermal Shutdown As soon as the device's junction temperature exceeds 160°C (typical), all switching activity ceases and both high-side and low-side power transistors are off. The device continues operation once the temperature fall to 20°C (typical) below its thermal shutdown threshold of 160°C. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering, and minimizing the interference with other circuits caused by high input voltage spikes. The converter needs a ceramic input capacitor of 22 µF. The input capacitor may be increased without any limit for better input voltage filtering. The AVIN pin is separated from the power input of the converter. Note that the filter resistor may affect the undervoltage lockout threshold since up to 5 mA can flow via this resistor into the AVIN pin when the converter runs in PWM mode. Table 1. Input Capacitor Selection Capacitor Value Case Size Component Supplier Comments 22 µF 22 µF 1206 TDK C3216X5R0J226M Ceramic 1206 Taiyo Yuden JMK316BJ226ML Ceramic Output Filter Design (Inductor and Output Capacitor) The TPS62510 step-down converter has an internal loop compensation. Therefore, the external L-C filter must be selected to work with the internal compensation. The internal compensation is optimized to operate with an output filter of L = 2.2 µH with an output capacitor of CO = 22 µF. The output filter has its corner frequency per Equation 6: 1 ƒc = 2p x L x CO 1 = 2p x = 22.8 kHz 2.2 mH x 22 mF (6) with L = 2.2 µH CO = 22 µF As a general rule of thumb, the product LxC should not move over a wide range when selecting a different output filter. This is because the internal compensation is designed to work with a certain output filter corner frequency, as calculated in Equation 6. This is especially important when selecting smaller inductor or output capacitor values that move the corner frequency to higher frequencies. However, when selecting the output filter a low limit for the inductor value exists due to other internal circuit limitations. The minimum inductor value for the TPS62510 should be kept at 2.2µH. Selecting a larger capacitor value is less critical because the corner frequency drops, causing fewer stability issues. 14 Submit Documentation Feedback TPS62510 www.ti.com SLVS651 – MAY 2006 Table 2. Output Capacitor Selection (1) L CO 2.2 µH ≥ 22 µF (ceramic capacitor) 3.3 µH ≥ 22 µF (ceramic capacitor) (1) For output currents < 800 mA, a 10-µF output capacitor is sufficient. Setting the Output Voltage Using the Feedback Resistor Divider The external resistor divider sets the output voltage of the converter. The output voltage is calculated as: ( VO = 0.6 V x 1 + R1 R2 ) (7) with: R1 + R2 ≤ 1 MΩ, and the internal reference voltage is Vref typical = 0.6 V. To keep the operating quiescent current to a minimum, a high impedance feedback divider is selected with R1 + R2 ≤ 1 MΩ. The sum of R1 and R2 should not be greater than 1 MΩ to avoid possible noise related regulation issues. A feedforward capacitor is needed across the upper feedback resistor to place a zero at a frequency of 25 kHz in the control loop. After selecting the feedback resistor values, the feedforward capacitor is calculated as: 1 = C1 = 2p x ƒz x R1 1 2p x 25 kHz x R1 (8) with: R1 = upper resistor of voltage divider, and C1 = upper capacitor of voltage divider. Select the capacitor value that is closest to the calculated value. This capacitor is only needed when setting the output voltage with the external divider. Inductor Selection For high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. Especially at high switching frequencies where the core material has a higher impact on the efficiency. The inductor value determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current, and the lower the conduction losses of the converter. However, larger inductor values cause slower load transient response. Usually, the inductor ripple current as calculated in Equation 9, should be around 20% of the average output current. To avoid saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current calculated in Equation 9: 1 DIL = VO x VO VI L x ƒ IL max = IO max + DIL 2 (9) with: f = Switching frequency (1.5 MHz typical) L = Inductor value ∆IL = Peak-to-Peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current occurs at maximum VI. A more conservative approach is to select the inductor current rating just for the maximum typical switch current limit of the converter of 2 A. See Table 3 for inductor recommendations. Submit Documentation Feedback 15 TPS62510 www.ti.com SLVS651 – MAY 2006 Table 3. Inductor Recommendations Inductor Value Component Supplier Dimensions I(SAT) / R(DC) 2.2 µH Sumida CDRH2D18/HP 4R7 3.2 mm x 3.2 mm x 2 mm 1.6 A / 60 mΩ 2.2 µH Wuerth 744045002 4.5 mm x 3.2 mm x 2.6 mm 1.6 A / 110 mΩ 2.2 µH Sumida CDRH3D14 4 mm x 4 mm x 1.8 mm 1.75 A / 69 mΩ 2.2 µH Sumida CDRH4D22 5 mm x 5 mm x 2.4 mm 1.8 A / 25.4 mΩ 2.2 µH Sumida CDRH4D28 5 mm x 5 mm x 3 mm 2 A / 31.3 mΩ 2.2 µH Coilcraft MSS5131 5.1 mm x 5.1 mm x 3.1 mm 1.9 A / 23 mΩ 2.2 µH Coilcraft DO1608 6.6 mm x 4.45 mm x 2.92 mm 2.3 A / 28 mΩ 2.2 µH Wuerth 74455022 6.6 mm x 4.45 mm x 2.92 mm 2.3 A / 28 mΩ Layout Guidelines VI 1.8 V to 3.8 V C1 22 mF TPS62510 10 Rf 1 W Cf 100 nF 9 PVIN AVIN 6 EN 5 7 SW FB PG OVT AGND MODE PGND 1 4 L1 2.2 mH C3 22 pF 8 3 VO 1.5 V to 1.5 A R1 300 kW C2 22 mF R2 200 kW 2 Figure 22. Layout Guidelines 1. 2. 3. 4. 5. Place and route the power components first (C1, L1, C2). The input capacitor (C1) must be placed as close as possible from PVIN to PGND. The inductor must be placed as close as possible to the switch pin. All ground connections (shown in bold) must be on a common ground plane or form a star ground. Analog ground (AGND) and power ground (PGND) as well as the device PowerPAD™ must be tight together. 6. The feedback network (R1, C3, R2) must be routed away from the inductor (L1) and should be grounded to the PowerPAD™. 7. The feedback network must sense and regulate the output voltage across the output capacitor to minimize load regulation. 16 Submit Documentation Feedback TPS62510 www.ti.com SLVS651 – MAY 2006 APPLICATION INFORMATION Typical Application VI 1.8 V to 3.8 V TPS62510 10 Rf 1 W C1 22 mF Cf 100 nF 9 6 5 7 PVIN SW AVIN FB EN PG OVT AGND MODE PGND 1 4 VO 1.5 V to 1.5 A L1 2.2 mH C3 22 pF R1 300 kW C2 22 mF 8 R2 200 kW 3 2 Figure 23. Adjustable Version Programmed to 1.5 V VI 1.8 V to 3.8 V C1 22 mF TPS62510 10 Rf 1 W Cf 100 nF 9 6 5 7 PVIN SW AVIN FB EN PG OVT AGND MODE PGND VO 1.5 V to 1.5 A L1 2.2 mH 1 4 8 C3 22 pF VI 3 2 R1 300 kW C2 22 mF R2 200 kW R3 500 kW Power Good Figure 24. Adjustable Version Programmed to 1.5 V Using Power Good Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS62510DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62510DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62510DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS62510DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS62510DRCR DRC 10 SITE 41 330 12 3.3 3.3 1.1 8 12 Q2 TPS62510DRCT DRC 10 SITE 41 180 12 3.3 3.3 1.1 8 12 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2007 Device Package Pins Site Length (mm) Width (mm) TPS62510DRCR DRC 10 SITE 41 346.0 346.0 29.0 TPS62510DRCT DRC 10 SITE 41 190.0 212.7 31.75 Pack Materials-Page 2 Height (mm) IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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