TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE FEATURES APPLICATIONS • • • • • • • • • • • • • Eight Voltage Output DACs in One Package – TLV5630 . . . 12-Bit – TLV5631 . . . 10-Bit – TLV5632 . . . 8-Bit – 1 µs in Fast Mode – 3 µs in Slow Mode Programmable Settling Time vs Power Consumption – 1 µs in Fast Mode – 3 µs in Slow Mode – 18 mW in Slow Mode at 3 V – 48 mW in Fast Mode at 3 V Compatible With TMS320 and SPI Serial Ports Monotonic Over Temperature Low Power Consumption: – 18 mW in Slow Mode at 3 V – 48 mW in Fast Mode at 3 V Power-Down Mode Internal Reference Data Output for Daisy-Chaining Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices DW OR PW PACKAGE (TOP VIEW) DGND DIN SCLK FS PRE OUTE OUTF OUTG OUTH AGND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DVDD DOUT LDAC MODE REF OUTD OUTC OUTB OUTA AVDD DESCRIPTION The TLV5630, TLV5631, and TLV5632 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs, and a data output which can be used to cascade multiple devices, and an internal programmable band-gap reference. The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be connected to the supply voltage. Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V. The devices are available in 20-pin SOIC and TSSOP packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2004, Texas Instruments Incorporated TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS PACKAGE TA 40°C to 85°C SOIC (DW) TSSOP (PW) RESOLUTION TLV5630IDW TLV5630IPW 12 TLV5631IDW TLV5631IPW 10 TLV5632IDW TLV5632IPW 8 FUNCTIONAL BLOCK DIAGARAM REF Band-Gap Voltage 12/10/8 12/10/8 12/10/8 X2 1 V or 2 V (Trimmed) with Enable DAC A Holding Latch 2 OUTA DAC A Latch SCLK DIN DOUT 12 Serial Interface FS 8 DAC B, C, D, E, F, G and H Same as DAC A MODE PRE OUT B, C, D, E, F, G and H LDAC Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 10 P Analog ground AVDD 11 P Analog power supply DGND 1 P Digital ground DIN 2 I Digital serial data input DOUT 19 O Digital serial data output DVDD 20 P Digital power supply FS 4 I Frame sync input LDAC 18 I Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input. MODE 17 I DSP/µC mode pin. High = µC mode, NC = DSP mode. PRE 5 I Preset input REF 16 I/O SCLK OUTA-OUTH 2 Voltage reference input/output 3 I Serial clock input 12-15, 6-9 O DAC outputs A, B, C, D, E, F, G and H TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) (1) UNIT Supply voltage, (AVDD, DVDD to GND) 7V Reference input voltage range - 0.3 V to AVDD + 0.3 Digital input voltage range - 0.3 V to DVDD + 0.3 Operating free-air temperature range, TA -40°C to 85°C Storage temperature range, Tstg -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 260°C Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Supply voltage, AVDD, DVDD High-level digital input, VIH Low-level digital input, VIL Reference voltage, Vref Analog output load resistance, RL MIN TYP MAX 5-V operation 4.5 5 5.5 V 3-V operation 2.7 3 3.3 V DVDD = 2.7 V 2 DVDD = 5.5 V 2.4 0.6 DVDD = 5.5 V 1.0 AVDD = 5 V GND 2.048 AVDD AVDD = 3 V GND 1.024 AVDD 2 Clock frequency, fCLK Operating free-air temperature, TA V DVDD = 2.7 V Analog output load capacitance, CL -40 UNIT V V kΩ 100 pF 30 MHz 85 °C 3 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Fast 16 21 Slow 6 8 UNIT POWER SUPPLY IDD Power supply current No load, All inputs = DVDD or GND, Vref = 2.048 V, Power-down supply current POR Power on threshold PSRR Power supply rejection ratio mA 0.1 µA 2 V 50 dB TLV5630 12 Bits TLV5631 10 Bits TLV5632 8 Bits Full scale, See (1) STATIC DAC SPECIFICATIONS Resolution TLV5630 INL Integral nonlinearity TLV5631 Vref = 1 V, 2 V TLV5632 TLV5630 DNL Differential nonlinearity TLV5631 Vref = 1 V, 2 V TLV5632 EZS Zero scale error (offset error at zero scale) EZS TC Zero scale error temperature coefficient EG Gain error EGTC Gain error temperature coefficient Code 40 to 4095 ±2 ±6 LSB Code 20 to 1023 ±0.5 ±2 LSB Code 6 to 255 ±0.3 ±1 LSB Code 40 to 4095 ±0.5 ±1 LSB Code 20 to 1023 ±0.1 ±1 LSB Code 6 to 255 ±0.1 ±1 LSB ±30 mV 30 µV/°C ±0.6 10 %Full Scale V ppm/°C OUTPUT SPECIFICATIONS VO Voltage output range Output load regulation accuracy RL = 10 kΩ 0 AVDD-0.4 RL = 2 kΩ vs 10 kΩ V ±0.3 %Full Scale V REFERENCE OUTPUT VREFOU Low reference voltage TL VREFOU VDD > 4.75 V High reference voltage 1.010 1.024 1.040 V 2.020 2.048 2.096 V TH Iref(Sourc Output source current 1 mA e) Iref(Sink) Output sink current Load capacitance PSRR -1 See (2) 1 Power supply rejection ratio mA 10 µF 60 dB REFERENCE INPUT VI Input voltage range RI Input resistance Ci Input capacitance Reference input bandwidth (1) (2) 4 0 AVDD 50 Vref = 0.4 Vpp + 2.048 Vdc, Input code = 0x800 V kΩ 10 pF Fast 2.2 MHz Slow 1.9 MHz Power supply rejection ratio at full scale is measured by varying AVDD and is given by: PSRR = 20 log [(EG(AVDDmax) EG(AVDDmin))/VDDmax] In parallel with a 100-nF capacitor TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER Reference feedthrough TEST CONDITIONS Vref = 2 Vpp at 1 kHz + 2.048 Vdc, See MIN (3) TYP MAX 84 UNIT dB DIGITAL INPUTS IIH High-level digital input current VI = DVDD IIL Low-level digital input current VI = 0 V CI Input capacitance 1 1 µA µA 8 pF DIGITAL OUTPUT VOH High-level digital output RL = 10 kΩ voltage 2.6 VOL Low-level digital output voltage RL = 10 kΩ Output voltage rise time RL = 10 kΩ, CL = 20 pF, Includes propagation delay V 0.4 V 5 10 ns Fast 1 3 Slow 3 7 Fast 0.5 1 Slow 1 2 ANALOG OUTPUT DYNAMIC PERFORMANCE ts(FS) Output settling time, full RL = 10 kΩ, CL = 100 pF, See scale (4) ts(CC) Output settling time, code to code RL = 10 kΩ, CL = 100 pF, See (5) SR Slew rate RL = 10 kΩ, CL = 100 pF, See (6) Glitch energy See Channel crosstalk 10 kHz sine, 4 VPP (3) (4) (5) (6) (7) Fast 4 10 Slow 1 3 (7) µs µs V/µs 4 nV-s 90 dB Reference feedthrough is measured at the DAC output with an input code = 0x000. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x080 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. Code transition: TLV5630 - 0x7FF to 0x800, TLV5631 - 0x7FCto 0x800, TLV5632 - 0x7F0 to 0x800. DIGITAL INPUT TIMING REQUIREMENTS PARAMETER tsu(FS-CK) Setup time, FS low before next negative SCLK edge MIN TYP MAX UNIT 8 ns tsu(C16-FS) Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising edge of FS. µC mode only 10 ns tsu(FS-C17) µC mode, setup time, FS high before 17th positive SCLK. 10 ns tsu(CK-FS) DSP mode, setup time, SLCK low before FS low. 5 ns twL(LDAC) LDAC duration low 10 ns tsu(FS-CK) Setup time, FS low before first negative SCLK edge 8 ns twL SCLK pulse duration low tsu(D) Setup time, data ready before SCLK falling edge th(D) Hold time, data held valid after SCLK falling edge twH(FS) FS duration high twL(FS) FS duration low 10 ns ts Settling time 16 8 ns 5 ns 10 ns See AC specs 5 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 TYPICAL CHARACTERISTICS OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION 1 1 VDD = 3 V, Vref = 1 V, Zero Scale 0.9 0.8 0.8 Fast VO − Output Voltage − V VO − Output Voltage − V VDD = 5 V, Vref = 2 V, Zero Scale 0.9 0.7 0.6 0.5 0.4 0.3 Fast 0.7 0.6 0.5 0.4 0.3 0.2 0.2 0.1 0.1 Slow Slow 0 0 0.5 0 1.5 1 Sinking Current − mA 0.5 0 2 Figure 1. OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION 4.12 VDD = 3 V, Vref = 1 V, Full Scale 2.055 4.11 Slow VO − Output Voltage − V VO − Output Voltage − V 2 Figure 2. 2.06 2.05 1.5 1 Sinking Current − mA Fast 2.045 2.04 2.035 VDD = 5 V, Vref = 2 V, Full Scale Fast 4.1 Slow 4.09 4.08 4.07 4.06 2.03 2.025 −0.05 −0.5 4.05 4.04 −1 −1.5 −2 −2.5 −3 Sourcing Current − mA Figure 3. 6 −3.5 −4 0 −0.5 −1 −1.5 −2 −2.5 −3 Sourcing Current − mA Figure 4. −3.5 −4 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) INL − Integral Nonlinearity − LSB TLV5630 INTEGRAL NONLINEARITY vs CODE 4 3 2 1 0 −1 −2 −3 −4 0 1024 2048 3072 4096 3072 4096 768 1024 Code Figure 5. DNL − Differential Nonlinearity − LSB TLV5630 DIFFERENTIAL NONLINEARITY vs CODE 1.0 0.8 0.6 0.4 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 −1.0 0 1024 2048 Code Figure 6. INL − Integral Nonlinearity − LSB TLV5631 INTEGRAL NONLINEARITY vs CODE 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 0 256 512 Code Figure 7. 7 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) DNL − Differential Nonlinearity − LSB TLV5631 DIFFERENTIAL NONLINEARITY vs CODE 1.0 0.8 0.6 0.4 0.2 −0.0 −0.2 −0.4 −0.6 −0.8 −1.0 0 256 512 768 1024 Code Figure 8. INL − Integral Nonlinearity − LSB TLV5632 INTEGRAL NONLINEARITY vs CODE 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 50 100 150 200 250 200 250 Code Figure 9. DNL − Differential Nonlinearity − LSB TLV5632 DIFFERENTIAL NONLINEARITY vs CODE 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 50 100 150 Code Figure 10. 8 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION twH twL SCLK X 1 2 3 4 16 17 X th(D) tsu(D) DIN X D15 DOUT X D15 D14 † D13 † D14 D13 D12 † D12 D1 † D1 D0 † D0 X † X tsu(FS - C17) tsu(FS - CK) twH(FS) tsu(C16 - FS) FS (µC mode) tsu(CK - FS) twL(FS) FS (DSP Mode) † X Previous input data Figure 11. Serial Interface Timing twL(LDAC) LDAC ts ±0.5 LSB OUTx Figure 12. Output Timing 9 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 APPLICATION INFORMATION GENERAL FUNCTION The TLV5630/31/32 are 8-channel, single-supply DACs, based on a resistor string architecture. They consist of a serial interface, a speed and power-down control logic, an internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) for each channel is given by: 2REF CODE [V] 0x1000 where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for the TLV5630, 0x000 to 0xFFC for the TLV5631, and 0x000 to 0xFF0 for the TLV5632. A power-on-reset initially puts the internal latches to a defined state (all bits zero). SERIAL INTERFACE A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed. For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles. DSP Mode: SCLK FS DIN X D15 D14 D1 D0 E15 E14 X D15 D14 D1 D0 X E15 E1 E0 X E1 E0 X X F15 F15 X F15 F15 µC Mode: SCLK FS DIN E14 X Difference between DSP mode (MODE = N.C. or 0) and µC (MODE = 1) mode: • In µC mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS. • In DSP mode, FS needs to stay low for 20 ns and can go high before the 16th falling clock edge. • In DSP mode there needs to be one falling SCLK edge before FS goes low to start the write (DIN) cycle. This extra falling SCLK edge has to happen at least 5 ns before FS goes low, tsu(CK-FS) ≥ 5 ns. • In µC mode, the extra falling SCLK edge is not necessary. However, if it does happen, the extra negative SCLK edge is not allowed to occur within 10 ns after FS goes HIGH to finish the WRITE cycle (tsu(FS-C17)). 10 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 APPLICATION INFORMATION (continued) SERIAL CLOCK FREQUENCY AND UPDATE RATE The maximum serial clock frequency is given by: f sclkmax t whmin 1 t 30 MHz wlmin The maximum update rate is: f updatemax 1 whmin twlmin 16 t 1.95 MHz Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the DAC has to be considered also. DATA FORMAT The 16-bit data word consists of two parts: • Address bits (D15…D12) • Data bits (D11…D0) D15 D14 D13 D12 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Ax: Address bits. See table. REGISTER MAP A3 A2 A1 A0 FUNCTION 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 0 0 0 CTRL0 1 0 0 1 CTRL1 1 0 1 0 Preset 1 0 1 1 Reserved 1 1 0 0 DAC A and B 1 1 0 1 DAC C and D 1 1 1 0 DAC E and F 1 1 1 1 DAC G and H 11 TLV5630 TLV5631 TLV5632 www.ti.com SLAS269D – MAY 2000 – REVISED MARCH 2004 DAC A-H AND TWO-CHANNEL REGISTERS Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.). The TLV5630 decodes all 12 data bits. The TLV5631 decodes D11 to D2 (D1 and D0 are ignored). The TLV5632 decodes D11 to D4 (D3 to D0 are ignored). PRESET The outputs of all DAC channels can be driven to a predefined value stored in the Preset register by driving the PRE input low. The PRE input is asynchronous to the clock. CTRL0 BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X X PD DO R1 R0 IM Default X X X X X X X 0 0 0 0 0 PD : Full device power down 0 = normal 1 = power down DO : DOUT enable 0 = disabled 1 = enabled R1:0 : Reference select bits 0 = external 1 = external, 2 = internal 1 V, 3 = internal 2 V IM : Input mode 0 = straight binary 1 = twos complement X : Reserved If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to daisy-chain multiple DACs on one serial bus. CTRL1 BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X PGH PEF PCD PAB SGH SEF SCD SAB Default X X X X 0 0 0 0 0 0 0 0 PXY : Power Down DACXY 0 = normal 1 = power down SXY : Speed DACXY 0 = slow 1 = fast XY : DAC pair AB, CD, EF or GH In power-down mode, the amplifiers of the selected DAC pair are disabled and the total power consumption of the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by setting the PXY bit within the data word to 1. There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to 1 and slow mode is selected by setting SXY to 0. 12 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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