D−8 DGK−8 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 2.7-V TO 5.5-V, LOW POWER, 12-BIT, DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN FEATURES APPLICATIONS • • • • • • • • • • • 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time: – 1 µs in Fast Mode – 3.5 µs in Slow Mode Compatible With TMS320 and SPI™ Serial Ports Differential Nonlinearity . . . <0.5 LSB Typ Monotonic Over Temperature Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices D OR DGK PACKAGE (TOP VIEW) DIN SCLK CS FS 1 8 2 7 3 6 4 5 VDD OUT REF AGND DESCRIPTION The TLV5636 is a 12-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows glueless interface to TMS320 and SPI™, QSPI™, and Microwire™ serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5636 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial temperature ranges AVAILABLE OPTIONS TA PACKAGE SOIC (D) MSOP (DGK) 0°C to 70°C TLV5636CD TLV5636CDGK -40°C to 85°C TLV5636ID TLV5636IDGK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc.. Microwire is a trademark of National Semiconductor Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2004, Texas Instruments Incorporated TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM REF PGA With Output Enable Voltage Bandgap Power and Speed Control Power-On Reset 2 2 DIN SCLK CS 2-Bit Control Latch Serial Interface and Control 12 12 12-Bit DAC Latch FS x2 Terminal Functions TERMINAL I/O/P DESCRIPTION NAME NO. AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input FS 4 I Frame sync input OUT 7 O DAC A analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 OUT TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage (VDD to AGND) 7V Reference input voltage - 0.3 V to VDD + 0.3 V Digital input voltage range - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA TLV5636C 0°C to 70°C TLV5636I -40°C to 85°C Storage temperature range, Tstg -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Supply voltage, VDD MIN NOM MAX VDD = 5 V 4.5 5 5.5 V VDD = 3 V 2.7 3 3.3 V 2 V Power on Reset, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REF terminal 0.55 DVDD = 2.7 V 2 DVDD = 5.5 V 2.4 V DVDD = 2.7 V 0.6 DVDD = 5.5 V 1 VDD = 5 V (1) AGND 2.048 VDD - 1.5 VDD = 3 V (1) AGND 1.024 VDD - 1.5 Load resistance, RL UNIT 2 V V V kΩ Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz Operating free-air temperature, TA (1) TLV5636C TLV5636I 0 70 -40 85 °C Due to the x2 output buffer, a reference input voltage . (VDD - 0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) POWER SUPPLY PARAMETER IDD PSRR (1) (2) TEST CONDITIONS TYP MAX Fast MIN 2.3 3.3 Slow 1.5 1.9 10 Power supply current No load, All inputs = AGND or VDD, DAC latch = 0x800 Power-down supply current See Figure 8 0.01 (1) -65 Power supply rejection ratio Zero scale Full Scale (2) -65 UNIT mA µA dB Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax] Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax] 3 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) STATIC DAC SPECIFICATIONS PARAMETER TEST CONDITIONS MIN Resolution ±4 LSB ±1 LSB ±20 mV ±0.6 % of FS voltage See note (2) EZS Zero-scale error (offset error at zero scale) See note (3) Zero-scale-error temperature coefficient See note (4) EG Gain error See note (5) EG TC Gain error temperature coefficient See note (6) (3) (4) (5) (6) Bits ±2 See Differential nonlinearity (2) UNIT ±0.5 Integral nonlinearity DNL (1) MAX note (1) INL EZS TC TYP 12 10 µV/°C 10 ppm/°C The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 4095. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 10 to code 4095. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref x 106/(Tmax - Tmin). Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. Gain error temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref x 106/(Tmax - Tmin). OUTPUT SPECIFICATIONS PARAMETER VO TEST CONDITIONS Voltage output range MIN RL = 10 kΩ Output load regulation accuracy TYP 0 MAX VDD - 0.4 VO = 4.096 V, 2.048 V, RL= 2 kΩ UNIT V ±0.25 % of FS voltage REFERENCE PIN CONFIGURED AS OUTPUT (REF) PARAMETER Vref(OUTL) Low reference voltage Vref(OUTH) High reference voltage Iref(source) Output source current Iref(sink) Output sink current TEST CONDITIONS VDD > 4.75 V MIN TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.068 V 1 -1 mA Load capacitance PSRR mA 100 Power supply rejection ratio -65 pF dB REFERENCE INPUT CONFIGURED AS INPUT (REF) PARAMETER VI Input voltage Ri Input resistance Ci Input capacitance (1) TEST CONDITIONS MIN TYP 0 Reference input bandwidth REF = 0.2 Vpp + 1.024 V dc Reference feed through REF = 1 Vpp at 1 kHz + 1.024 V dc (1) MAX VDD - 1.5 UNIT V 10 kΩ 5 pF Fast 1.3 Slow 525 MHz -80 dB Reference feedthrough is measured at the DAC output with an input code = 0x000. DIGITAL INPUT PARAMETER TEST CONDITIONS IIH High-level digital input current VI = VDD IIL Low-level digital input current VI = 0 V Ci Input capacitance 4 MIN TYP MAX 1 -1 UNIT µA µA 8 pF TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) ANALOG OUTPUT DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS ts(FS) Output settling time (full scale) RL = 10 kΩ, see note (1) CL = 100 pF, ts(CC) Output settling time, code to code RL = 10 kΩ, see note (2) CL = 100 pF, SR Slew rate RL = 10 kΩ, see note (3) CL = 100 pF, Glitch energy DIN = 0 to 1, CS = VDD TYP MAX Fast MIN 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 8 Slow 1.5 fout = 1 kHz, Signal-to-noise ratio 71 S/(N+D) Signal-to-noise + distortion 59 THD Total harmonic distortion fs = 480 kSPS, RL = 10 kΩ, fout = 1 kHz, CL = 100 pF Spurious free dynamic range (1) (2) (3) µs µs V/µs 5 SNR UNIT nV-s 75 66 -67 59 -59 dB 69 Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of 0x20 to 0xFDF and 0xFDF to 0x020 respectively. Assured by design; not tested. Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of one count. Assured by design; not tested. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. TIMING REQUIREMENTS DIGITAL INPUTS MIN tsu(CS-FS) Setup time, CS low before FS falling edge tsu(FS-CK) Setup time, FS low before first negative SCLK edge 16th NOM MAX UNIT 10 ns 8 ns tsu(C16-FS) Setup time, negative edge after FS low on which bit D0 is sampled before rising edge of FS. 10 ns tsu(C16-CS) Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of 16th positive edge to update DAC, then setup time between FS rising edge and CS rising edge. 10 ns twH SCLK pulse duration high 25 ns twL SCLK pulse duration low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns twH(FS) FS duration high 25 ns 5 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION twL SCLK X 1 2 tsu(D) DIN X twH 3 4 5 15 X 16 th(D) D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(FS-CK) tsu(C16-FS) FS Figure 1. Timing Diagram 6 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 2.071 4.135 VDD = 3 V, REF = Int. 1 V, Input Code = 4095 VDD = 5 V, REF = Int. 2 V, Input Code = 4095 2.0705 4.134 Fast 2.0695 Output Voltage − V Output Voltage − V 2.07 Fast 2.0698 Slow 2.0685 2.068 4.133 Slow 4.132 4.131 2.0675 2.067 4.13 2.0665 4.129 2.066 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 Source Current − mA 1.5 2 2.5 3 3.5 4 Source Current − mA Figure 2. Figure 3. OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 3 5 VDD = 3 V, REF = Int. 1 V, Input Code = 0 VDD = 5 V, REF = Int. 2 V, Input Code = 0 4.5 2.5 2 Output Voltage − V Output Voltage − V 4 Fast 1.5 1 3.5 3 Fast 2.5 2 1.5 1 0.5 0.5 Slow 0 Slow 0 0 0.5 1 1.5 2 2.5 Sink Current − mA Figure 4. 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 Sink Current − mA Figure 5. 7 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE 3 3 VDD = 5 V, REF = 2 V, Input Code = 4095 VDD = 3 V, REF = 1 V, Input Code = 4095 2.5 2.5 Supply Current − mA Supply Current − mA Fast Mode 2 Slow Mode 1.5 1 Slow Mode 0.5 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 T − Temperature − °C 0.5 −40−30−20 −10 0 10 20 30 40 50 60 70 80 90 T − Temperature − °C Figure 6. Figure 7. POWER DOWN SUPPLY CURRENT vs TIME TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD+N − Total Harmonic Distortion and Noise − dB I DD − Power Down Supply Current − mA 1.5 1 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 t − Time − µs Figure 8. 8 Fast Mode 2 60 70 80 0 −10 VDD = 5 V Vref = 1 V dc + 1 V p/p Sine Wave Output Full Scale −20 −30 −40 −50 −60 Slow Mode −70 Fast Mode −80 −90 −100 100 1000 10000 f − Frequency − Hz Figure 9. 100000 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREQUENCY 0 VDD = 5 V Vref = 1 V dc + 1 V p/p Sine Wave Output Full Scale THD − Total Harmonic Distortion − dB −10 −20 −30 −40 −50 −60 −70 Slow Mode −80 Fast Mode −90 −100 100 1000 10000 100000 f − Frequency − Hz Figure 10. DNL − Differential Nonlinearity − LSB DIFFERENTIAL NONLINEARITY vs DIGITAL INPUT CODE 1 0.5 0 −0.5 −1 0 1024 2048 Digital Input Code 3072 4096 Figure 11. 9 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 TYPICAL CHARACTERISTICS (continued) INL − Integral Nonlinearity − LSB INTEGRAL NONLINEARITY vs DIGITAL INPUT CODE 4 3 2 1 0 −1 −2 −3 −4 0 1024 2048 Digital Input Code Figure 12. 10 3072 4096 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 APPLICATION INFORMATION GENERAL FUNCTION The TLV5636 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) for each channel is given by: 2 REF CODE [V] 2n where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n-1, where n = 12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). SERIAL INTERFACE The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on high-low transitions of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level. The serial interface of the TLV5636 can be used in two basic modes: • Four wire (with chip select) • Three wire (without chip select) Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). Figure 13 shows an example with two TLV5636s connected directly to a TMS320 DSP. TLV5636 CS TMS320 DSP FS DIN SCLK TLV5636 CS FS DIN SCLK XF0 XF1 FSX DX CLKX Figure 13. TMS320 Interface If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows an example of how to connect the TLV5636 to TMS320, SPI™ or Microwire™ using only three pins. 11 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 APPLICATION INFORMATION (continued) TMS320 DSP FSX DX CLKX TLV5636 FS DIN SCLK SPI TLV5636 FS DIN SCLK I/O MOSI SCK CS Microwire I/O SO SK TLV5636 FS DIN SCLK CS CS Figure 14. Three Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5636. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge. SERIAL CLOCK AND UPDATE RATE The maximum serial clock frequency is given by: 1 f sclkmax 20 MHz t whmin t wlmin (1) The maximum update rate is: 1 f updatemax 1.25 MHz 16 t whmin t wlmin (2) Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5636 has to be considered, too. DATA FORMAT The 16-bit data word for the TLV5636 consists of two parts: • Program bits (D15..D12) • New data (D11..D0) D15 D14 D13 D12 R1 SPD PWR R0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 12 Data bits SPD : Speed control bit 1 = fast mode 0 = slow mode PWR : Power control bit 1 = power down 0 = normal operation The following table lists the possible combination of the register select bits: Register Select Bits 12 R1 R0 REGISTER 0 0 Write data to DAC 0 1 Reserved 1 0 Reserved 1 1 Write data to control register D1 D0 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 The meaning of the 12 data bits depends on the selected register. For the DAC register, the 12 data bits determine the new DAC output value: Data Bits: DAC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC value If the control register is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: Data Bits: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X (1) X X X X X X X X X REF1 REF0 (1) X = don't care REF1 and REF0 determine the reference source. If internal reference is selected, REF1 and REF0 determine the reference voltage. Reference Bits REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. EXAMPLE: • Set DAC output, select fast mode, select internal reference at 2.048 V: Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 D2 D1 D0 Write new DAC value and update DAC output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 New DAC output value The DAC output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. 13 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE END SUPPLIES When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 15. Output Voltage 0V DAC Code Negative Offset Figure 15. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 16 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 16. Power-Supply Bypassing 14 TLV5636 www.ti.com SLAS223C – JUNE 1999 – REVISED APRIL 2004 DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY Integral Nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Differential Nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Zero-Scale Error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. Gain Error (EG) Gain error is the error in slope of the DAC transfer function. Total Harmonic Distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. Signal-To-Noise Ratio + Distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. 15 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device (1) Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV5636CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5636CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5636CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5636CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5636ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5636IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5636IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5636IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5636IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV5636CDGKR Package Package Pins Type Drawing VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5636CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5636IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5636IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5636CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5636CDR SOIC D 8 2500 367.0 367.0 35.0 TLV5636IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5636IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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