TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 D D D D D D D 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time vs Power Consumption 1 µs in Fast Mode 3.5 µs in Slow Mode Compatible With TMS320 Differential Nonlinearity . . . <0.5 LSB Typ Voltage Output Range . . . 2x the Reference Voltage Monotonic Over Temperature DW OR PW PACKAGE (TOP VIEW) D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 D1 D0 CS WE LDAC REG AGND OUT REF VDD applications D D D D D Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices description The TLV5639 is a 12-bit voltage output digital-to-analog converter (DAC) with a microprocessor compatible parallel interface. It is programmed with a 16-bit data word containing 4 control and 12 data bits. Developed for a wide range of supply voltages, the TLV5639 can be operated from 2.7 V to 5.5 V. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. Because of its ability to source up to 1 mA, the internal reference can also be used as a system reference. With its on-chip programmable precision voltage reference, the TLV5639 simplifies overall system design. The settling time and the reference voltage can be chosen by the control bits within the 16-bit data word. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges. AVAILABLE OPTIONS PACKAGE TA SOIC (DW) TSSOP (PW) 0°C to 70°C TLV5639CDW TLV5639CPW – 40°C to 85°C TLV5639IDW TLV5639IPW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 functional block diagram REF AGND VDD PGA With Output Enable Voltage Bandgap D(0–11) Powerdown and Speed Control Power-On Reset 4 REG Interface Control CS 12 WE x2 2 4-Bit Control Latch 12-Bit DAC Holding Latch 12 12-Bit DAC Register 12 LDAC Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 14 P Ground CS 18 I Chip select. Digital input active low, used to enable/disable inputs 1 – 10, 19, 20 I Data input D0 – D11 LDAC 16 I Load DAC. Digital input active low, used to load DAC output OUT 13 O DAC analog voltage output REG 15 I Register select. Digital input, used to access control register REF 12 I/O VDD WE 11 P Positive power supply 17 I Write enable. Digital input active low, used to latch data 2 Analog reference voltage input/output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 OUT TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5639C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5639I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage voltage, VDD VDD = 5 V VDD = 3 V Power on threshold voltage, POR High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REF terminal Reference voltage, Vref to REF terminal MIN NOM MAX 4.5 5 5.5 V 2.7 3 3.3 V 2 V 0.55 VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V 2 VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) Load resistance, RL Operating free-air free air temperature, temperature TA V AGND 2.048 AGND 1.024 0.8 V VDD –1.5 VDD – 1.5 V 2 Load capacitance, CL TLV5639I V kΩ 100 TLV5639C UNIT 0 70 –40 85 pF °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN IDD Power supply current 2.3 2.8 mA Slow 1.3 1.6 mA REF off Fast 1.9 2.4 mA Slow 0.9 1.2 mA REF on Fast 2.1 2.6 mA Slow 1.2 1.5 mA REF off Fast 1.8 2.3 mA 0.9 1.1 mA 0.01 1 µA Slow Power down supply current Power supply rejection ratio UNIT Fast VDD = 3 V PSRR MAX REF on VDD = 5 V No load, All inputs = AGND or VDD, DAC latch = 0x800 TYP Zero scale, See Note 2, External reference –60 Full scale, –60 See Note 3, External reference dB NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS MIN TYP Resolution MAX 12 UNIT bits INL Integral nonlinearity, end point adjusted RL = 10 kΩ, CL = 100 pF, See Note 4 ± 1.2 ±3 LSB DNL Differential nonlinearity RL = 10 kΩ, CL = 100 pF, See Note 5 ± 0.3 ± 0.5 LSB EZS EZS TC Zero-scale error (offset error at zero scale) See Note 6 Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 ±12 20 LSB ppm/°C ± 0.3 % full scale V EG TC Gain error temperature coefficient See Note 9 20 ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text). 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref × 106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/2Vref × 106/(Tmax – Tmin). output specifications PARAMETER VO TEST CONDITIONS Output voltage RL = 10 kΩ Output load regulation accuracy 4 VO = 4.096 V, 2.048 V POST OFFICE BOX 655303 MIN TYP MAX VDD–0.4 RL = 2 kΩ • DALLAS, TEXAS 75265 ± 0.29 UNIT V % full scale V TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 electrical characteristics over recommended operating free-air temperature range, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) (Continued) reference pin configured as output (REF) PARAMETER Vref(OUTL) Vref(OUTH) Low reference voltage Iref(source) Iref(sink) Output source current PSRR Power supply rejection ratio TEST CONDITIONS High reference voltage VDD > 4.75 V MIN TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.069 1 Output sink current –1 V mA mA –48 dB reference pin configured as input (REF) PARAMETER VI RI Input voltage CI Input capacitance TEST CONDITIONS MIN TYP 0 Input resistance Reference input bandwidth REF = 0.2 0 2 Vpp + 1.024 1 024 V dc 10 kHz H i di t ti f Harmonic distortion, reference in ut input REF = 1 Vpp + 2.048 V dc, VDD = 5 V 50 kHz 100 kHz Reference feedthrough MAX VDD–1.5 MΩ 5 pF 900 Slow 500 Fast –87 Slow –77 Fast –74 Slow –61 Fast V 10 Fast REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) UNIT kHz dB dB –66 dB – 80 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS VI = VDD VI = 0 V Low-level digital input current MIN TYP 1 • DALLAS, TEXAS 75265 UNIT µA µA –1 8 POST OFFICE BOX 655303 MAX pF 5 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 operating characteristics over recommended operating free-air temperature range, Vref = 2.048 V, and Vref = 1.024 V, (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX Fast 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 ts(FS) (FS) Output settling time, time full scale RL = 10 kΩ,, See Note 11 CL = 100 pF,, ts(CC) (CC) Output settling time time, code to code RL = 10 kΩ,, See Note 12 CL = 100 pF,, SR Slew rate RL = 10 kΩ,, See Note 13 CL = 100 pF,, Glitch energy DIN = 0 to 1, CS = VDD fCLK = 100 kHz, SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion THD Total harmonic distortion SFDR Spurious free dynamic range fs = 480 kSPS, fout = 1 kHz, fB = 20 kHz kHz, kΩ, RL = 10 kΩ CL = 100 pF F Fast 6 10 Slow 1.2 1.7 78 61 67 –69 63 µs µs V/µs 5 73 UNIT nV–S –62 dB 74 NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF or 0xFDF to 0x020. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS–WE) tsu(D) Setup time, CS low before negative WE edge 15 ns Setup time, data ready before positive WE edge 10 ns tsu(R) th(DR) Setup time, REG ready before positive WE edge 20 ns Hold time, data and REG held valid after positive WE edge 5 ns tsu(WE-LD) twH(WE) Setup time, positive WE edge before LDAC low 5 ns Pulse duration, WE high 20 ns tw(LD) Pulse duration, LDAC low 23 ns 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 PARAMETER MEASUREMENT INFORMATION D(0–7) X REG X Data X Reg X tsu(D) tsu(R) CS th(DR) twH(WE) tsu(CS-WE) WE tsu(WE-LD) tw(LD) LDAC Figure 1. Timing Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 DNL – Differential Nonlinearity – LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY ERROR 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 512 1024 1536 2048 2560 3072 3584 4096 3584 4096 Digital Code Figure 2 INL – Intergral Nonlinearity – LSB INTEGRAL NONLINEARITY ERROR 3 2 1 0 –1 –2 –3 0 512 1024 1536 2048 2560 Digital Code Figure 3 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3072 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 TYPICAL CHARACTERISTICS MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT 4.08 2.04 VDD = 3 V, Vref = Int. 1 V, Input Code = 0xFFF 2.0395 4.079 VO – Output Voltage – V 2.039 VO – Output Voltage – V VDD = 5 V, Vref = Int. 2 V, Input Code = 0xFFF 4.0795 Fast Mode, Source 4.0785 Fast Mode, Source 2.0385 2.038 4.078 4.0775 2.0375 2.037 Slow Mode, Source 4.077 Slow Mode, Source 2.0365 4.0765 2.036 4.076 4.0755 2.0355 0 0.5 1 1.5 2 2.5 3 3.5 4 0 4.5 0.5 1 Load Current – mA Figure 4 4 4.5 MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT 0.25 0.25 Fast Mode, Sink Fast Mode, Sink 0.2 VO – Output Voltage – V 0.2 VO – Output Voltage – V 3.5 Figure 5 MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT 0.15 0.1 Slow Mode, Sink 0.15 0.1 Slow Mode, Sink 0.05 0.05 0 1.5 2 2.5 3 Load Current – mA VDD = 3 V, Vref = Int. 1 V, Input Code = 0x000 VDD = 5 V, Vref = Int. 2 V, Input Code = 0x000 0 0 0.5 1 1.5 2 2.5 3 Load Current – mA 3.5 4 4.5 0 0.5 Figure 6 1 1.5 2 2.5 3 Load Current – mA 3.5 4 4.5 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY THD – Total Harmonic Distortion – dB 0 –10 VDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale –20 –30 –40 –50 –60 Slow Mode –70 –80 Fast Mode –90 –100 100 10000 1000 100000 THD+N – Total Harmonic Distortion and Noise – dB TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY 0 –10 VDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale –20 –30 –40 –50 –60 Slow Mode –70 –80 Fast Mode –90 –100 100 1000 f – Frequency – Hz f – Frequency – Hz Figure 8 Figure 9 POWER DOWN SUPPLY CURRENT vs TIME 1 0.9 I DD – Supply Current – mA 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 t – Time – µs 70 Figure 10 10 10000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 80 90 100000 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 APPLICATION INFORMATION general function The TLV5639 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). parallel interface The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written to the DAC holding latch or the control register depends on REG. REG = 0 selects the DAC holding latch, REG = 1 selects the control register. LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. However, to control the DAC using the load feature, there should be approximately a 5 ns delay after the positive WE edge before driving LDAC low. TMS320C2XX, 5X TMS320C3X A(0–15) A(0–15) TLV5639 TLV5639 REG REG IS Address Decoder Address Decoder CS R/W WE LDAC TCLK0 LDAC WE CS >=1 WE IOSTROBE D(0–11) D(0–11) D(0–15) D(0–15) Figure 11 data format The TLV5639 writes data either to the DAC holding latch or to the control register, depending on the level of the REG input. Data destination: REG = 0 → DAC holding latch REG = 1 → control register POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 APPLICATION INFORMATION The following table lists the meaning of the bits within the control register: D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X† X X† X X† X X† X X† X X† X X† REF1 0† REF0 0† X X† PWR 0† SPD 0† † Default values X: don’t care SPD: Speed control bit PWR: Power control bit 1 → fast mode 1 → power down 0 → slow mode 0 → normal operation REF1 and REF0 determine the reference source and the reference voltage. REFERENCE BITS REF1 REF0 REFERENCE 0 0 External 0 1 2.048 V 1 0 1.024 V 1 1 External If an external reference voltage is applied to the REF pin, external reference must be selected. linearity, offset, and gain error using single end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 12. Output Voltage 0V DAC Code Negative Offset Figure 12. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full scale code and the lowest code that produces a positive output voltage. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 APPLICATION INFORMATION TLV5639 interfaced to TMS320C203 DSP hardware interface Figure 13 shows an example of the connection between the TLV5639 and the TMS320C203 DSP. The only other device that is needed in addition to the DSP and the DAC is the 74AC138 address decoding circuit . Using this configuration, the DAC data is at address 0x0084 and the DAC control word is at address 0x0085 within the I/O memory space of the TMS320C203. LDAC is tied low so that the output voltage is updated on the rising WE edge. TMS320C203 74AC138 A2 A A3 A4 B Y1 C 5V A6 IS G1 G2A G2B TLV5639 CS REG A0 D(0–11) 12 D(0–11) OUT WE WE To Other Devices Requiring Voltage Reference RLOAD LDAC REF Figure 13. TLV5639 to TMS320C203 DSP Interface Connection software Writing data or control information to the TLV5639 is done using a single command. For example, the line of code which reads: out 62h, dac_ctrl writes the contents of address 0x0062 to the I/O address equated to dac_ctrl (0x0085, the address where the DAC control register has been mapped). The following code shows how to set the DAC up to use the internal reference and operate in FAST mode by a write to the control register. Timer interrupts are then enabled and repeatedly generated every 205 µs to provide a timebase for synchonizing the waveform generation. In this example, the waveform is generated by simply incrementing a counter and outputting the counter value to the DAC data word once every timer interrupt. This results in a saw waveform. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 APPLICATION INFORMATION ; ; ; ; File: Function: Processors: 1999 Texas RAMP.ASM ramp generation with TLV5639 TMS320C203 Instruments ;–––––––––– I/O .include dac_data .equ dac_ctrl .equ and memory mapped regs ––––––––––––––– “regs.asm” 0084h 0085h ;––––––––––––– vectors ––––––––––––––––––––––––––––––– .ps 0h b start b INT1 b INT23 b TIM_ISR ––––––––––Main Program–––––––––– .ps 1000h .entry start: ldp #0 ; set data page to 0 ; disable interrupts setc INTM ; disable maskable interrupts splk #0ffffh, IFR splk #0004h, IMR ; set up the timer splk #0000h, 60h splk #0042h, 61h out 61h, PRD out 60h, TIM splk #0c2fh, 62h out 62h, TCR ; SPD=1 splk #0011h, 62h ; set up the DAC (FAST mode) and ; REF1=1 (2.048 V internal ref enable) out 62h, dac_ctrl clrc INTM ; enable interrupts ; loop forever! next idle b next –––––––––– Interrupt Service Routines–––––––––– INT1: ret ; do nothing and return INT23: ret ; do nothing and return TIM_ISR: ; timer interrupt handler add #1h ; increment accumulator sacl 60h out 60h, dac_data ; write to DAC clrc intm ; re-enable interrupts ret ; return from interrupt .END 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) DIM 4040000 / D 02/98 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV5639C, TLV5639I 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN SLAS189 – MARCH 1999 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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