WM2631 Octal 10-bit, Serial Input, Voltage Output DAC with Internal Reference Production Data, April 2001, Rev 1.1 FEATURES • • • • • • • • • DESCRIPTION Eight 10-bit DACs in one package Dual supply 2.7V to 5.5V operation DNL ±0.1 LSBs, INL ±0.5 LSBs typical Programmable settling time / power (1.0µs typical in fast mode) Internal programmable voltage reference Microcontroller compatible serial interface Power down mode ( < 0.1µA) Monotonic over temperature Data output for daisy chaining The WM2631 is an octal, 10-bit, resistor string digital-toanalogue converter. The eight individual DACs contained in the IC can be switched in pairs between fast and slow (low power) operation modes, or powered down, under software control. Alternatively, the whole device can be powered down, reducing current consumption to less than 0.1µA. The DAC outputs are buffered by a rail-to-rail amplifier with a gain of two, which is configurable as Class A (fast mode) or Class AB (for low-power mode). The WM2631 has been designed to interface directly to industry standard microprocessors and DSPs, and can operate on two separate analogue and digital power supplies. It is programmed with a 16-bit serial word comprising 4 address bits and up to 12 DAC or control register data bits. All eight DACs can be simultaneously forced to a preset value using a preset input pin. APPLICATIONS • • • • • • • • Battery powered test instruments Digital offset and gain adjustment Battery operated / remote industrial controls Programmable loop controllers CNC machine tools Machine and motion control devices Wireless telephone and communication systems Robotics A daisy-chain data output makes it possible to control several of Wolfson’s octal DACs from the same interface, without increasing the number of control lines. The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported. ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2631CDT 0° to 70°C 20-pin TSSOP WM2631IDT -40° to 85°C 20-pin TSSOP BLOCK DIAGRAM TYPICAL PERFORMANCE REF (16) AVDD (11) DVDD (20) 0.2 1.024V / 2.048V SELECTABLE REFERENCE DAC A DIN (2) RESISTOR STRING SCLK (3) FS (4) MODE (17) PREB (5) SERIAL INTERFACE AND CONTROL LOGIC (12) OUT A LATCH POWER/SPEED CONTROL Differential Non-Linearity (LSBs) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 DOUT (19) -0.2 REF 0 DACs B, C, D, E, F, G, H as DAC A LOADB (18) AGND (10) (6-9, 13-15) OUT B to H 256 384 512 640 768 896 1024 DIGITAL CODE DGND (1) WOLFSON MICROELECTRONICS LTD Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] www.wolfsonmicro.com 128 Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions. 2001 Wolfson Microelectronics Ltd. WM2631 Production Data PIN CONFIGURATION DGND 1 20 DVDD DIN 2 19 DOUT SCLK 3 18 LOADB FS 4 17 MODE PREB 5 16 REF OUTE 6 15 OUTD OUTF 7 14 OUTC OUTG 8 13 OUTB OUTH 9 12 OUTA AGND 10 11 AVDD PIN DESCRIPTION PIN NO NAME TYPE 1 DGND Supply DESCRIPTION Digital Ground 2 DIN Digital input 3 SCLK Digital input Serial clock input 4 FS Digital input Frame sync input 5 PREB Digital input 6 OUTE Analogue output Digital serial data input Preset input DAC Output E 7 OUTF Analogue output DAC Output F 8 OUTG Analogue output DAC Output G 9 OUTH Analogue output DAC Output H 10 AGND Supply Analogue Ground 11 AVDD Supply Analogue positive power supply 12 OUTA Analogue output 13 OUTB Analogue output DAC Output B 14 OUTC Analogue output DAC Output C 15 OUTD Analogue output DAC Output D 16 REF Analogue I/O 17 MODE Digital input Input mode 18 LOADB Digital input Load DAC 19 DOUT Digital output Serial data output 20 DVDD Supply WOLFSON MICROELECTRONICS LTD DAC Output A Voltage reference input / output Digital positive power supply PD Rev 1.1 April 2001 2 WM2631 Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Reference input voltage -0.3V AVDD + 0.3V Digital input voltage range to GND -0.3V DVDD + 0.3V 0°C -40°C 70°C 85°C -65°C 150°C Digital supply voltages, AVDD or DVDD to GND 7V WM2631CDT WM2631IDT Operating temperature range, TA Storage temperature Soldering lead temperature, 1.6mm (1/16 inch) from package body for 10 seconds 260°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN Supply voltage AVDD, DVDD 2.7 High-level digital input voltage VIH 2 Low-level digital input voltage Reference voltage to REF VIL VREF Output Load Resistance Load capacitance Operating free-air temperature RL CL TA TYP MAX UNIT 5.5 V V AVDD = 5V GND 2.048 0.8 AVDD AVDD = 3V GND 1.024 AVDD V 100 70 85 kΩ pF °C °C 2 WM2631CDT WM2631IDT 0 -40 V Note: Reference input voltages greater than AVDD/2 will cause saturation for large DAC codes. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 3 WM2631 Production Data ELECTRICAL CHARACTERISTICS Test Characteristics: RL = 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 10 bits Integral non-linearity INL Code 20 to 1023 (see Note 1) ±0.5 ±2 LSB Differential non-linearity DNL Code 20 to 1023 (see Note 2) ±0.1 ±1 LSB Zero code error ZCE See Note 3 ±30 mV GE See Note 4 ±0.6 % FSR PSRR See Note 5 -50 dB Zero code error temperature coefficient See Note 6 30 µV/°C Gain error temperature coefficient See Note 6 10 ppm/°C Gain error DC power supply rejection ratio DAC Output Specifications Output voltage range 10kΩ Load Output load regulation 2kΩ to 10kΩ load See Note 7 0 AVDD-0.4 V ±0.3 % Full Scale 8 21 mA mA Power Supplies Active supply current Power down supply current IDD No load, VIH=DVDD, VIL=0V AVDD = DVDD = 5V, VREF = 2.048V Slow Fast See Note 8 6 16 No load, all inputs 0V or DVDD 0.1 µA 10 3 V/µs V/µs Dynamic DAC Specifications Slew rate Settling time Glitch energy Channel Crosstalk WOLFSON MICROELECTRONICS LTD DAC code 10%-90% Load = 10kΩ, 100pF Fast Slow See Note 9 DAC code 10%-90% Load = 10kΩ, 100pF Fast Slow See Note 10 4 1 1 3 3 7 µs µs DAC code 511 to 512 4 nV-s 10kHz sine wave, 4V pk-pk -90 dB PD Rev 1.1 April 2001 4 WM2631 Production Data Test Characteristics: RL = 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Reference Configured as Input Reference input resistance RREF 50 kΩ Reference input capacitance CREF 10 pF -84 dB 1.9 2.2 MHz MHz Reference feedthrough VREF=2VPP at 1kHz + 2.048V DC, DAC code 0 Reference input bandwidth VREF= 0.4VPP + 2.048V DC, DAC code 512 Slow Fast Reference Configured as Output Low reference voltage VREFOUTL High reference voltage VREFOUTH Output source current IREFSRC Output sink current IREFSNK Load Capacitance VDD > 4.75V 1.010 1.024 1.040 V 2.020 2.048 2.096 V 1 mA -1 in parallel with 100nF cap. 1 PSRR mA 10 µF 60 dB Digital Inputs High level input current IIH Input voltage = DVDD -1 Low level input current IIL Input voltage = 0V -1 Input capacitance CI 1 µA 1 µA 8 pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load. 8. IDD is measured while continuously writing a digital code of 512 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase. 9. Slew rate results are for the lower value of the rising and falling edge slew rates. 10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 5 WM2631 Production Data SERIAL INTERFACE tWL SCLK X 1 2 tWH 3 4 X 16 tHD tSUD DIN X D15 D14 D13 DOUT X D15 * D14 * D13 * tWHFS tSUFSCLK FS (µC MODE) 2 D12 * D1 D0 X D1 * D0 * X tSUC16-FS * DIN data from previous word (delayed by 16 clock cycles) tWLFS FS (DSP MODE) No high to low transitions Figure 1 Timing Diagram SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Setup time, FS pin low before first falling edge of SCLK 8 ns Setup time, 16th falling clock edge after FS low to rising edge of FS (only used in microcontroller mode) 10 ns tWLOADB Pulse duration, LOADB low 10 ns tWH Pulse duration, SCLK high 16 ns tWL Pulse duration, SCLK low 16 ns tSUD Setup time, data ready before SCLK falling edge 8 ns tHD Hold time, data held valid after SCLK falling edge 5 ns tWHFS Pulse duration, FS high 10 ns tWLFS Pulse duration, FS low 10 ns DAC Output settling time see Dynamic DAC Specifications tSUFSCLK tC16-FS ts WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 6 WM2631 Production Data TYPICAL PERFORMANCE GRAPHS 1 0.75 Integral Non-Linearity (LSBs) 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 128 256 384 512 640 768 896 1024 DIGITAL CODE Figure 2 Integral Non-Linearity 1 1 VDD = 3.3V VREF = 1.024V Input Code = 0 VDD = 5V VREF = 2.048V Input Code = 0 Slow Fast Output Voltage (V) Output Voltage (V) Slow Fast 0.8 0.8 0.6 0.4 0.2 0.6 0.4 0.2 0 0 0 0.5 1 1.5 2 0 0.2 0.4 0.6 Figure 3 Output Load Regulation (Sink) AVDD = 3V 1 1.2 1.4 1.6 1.8 2 Figure 4 Output Load Regulation (Sink) AVDD = 5V 2.1 4.15 VDD=3V VREF=1.024V Input Code = 4095 VDD=5V VREF=2.048V Input Code = 4095 Slow Fast 2.08 Slow Fast 4.13 DACA (Volts) DACA (Volts) 0.8 Sink Current (mA) Sink Current (mA) 2.06 2.04 4.11 4.09 4.07 2.02 4.05 2 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 Sourcing Current (mA) Figure 5 Output Load Regulation (Source) AVDD = 3V WOLFSON MICROELECTRONICS LTD 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 Sourcing Current (mA) Figure 6 Output Load Regulation (Source) AVDD = 5V PD Rev 1.1 April 2001 7 WM2631 Production Data DEVICE DESCRIPTION GENERAL FUNCTION The WM2631 is an octal 10-bit, voltage output DAC. It contains a serial interface, control logic for speed and power down, a programmable voltage reference, and eight digital to analogue converters. Each converter uses a resistor string network buffered with an op amp to convert 10-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: ( ) CODE Output voltage = 2 VREF 1024 INPUT 11 1111 1111 OUTPUT ( ) 1023 2 VREF 1024 : 10 0000 0001 : ( ) 511 2 VREF 1024 10 0000 0000 ( ) 512 2 VREF = VREF 1024 01 1111 1111 ( ) 511 2 VREF 1024 : 00 0000 0001 : ( ) 1 2 VREF 00 0000 0000 1024 0V Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC register to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kΩ load with a 100pF load capacitance. PROGRAMMABLE REFERENCE The DAC reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 8 WM2631 Production Data SERIAL INTERFACE INTERFACE MODES The control interface can operate in two different modes: • In the microcontroller mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS. • In DSP mode, FS only needs to stay low for 20ns, and can go high before the 16th falling clock edge. SCLK FS DIN X D15 D14 D1 D0 X E15 E15 E14 E14 E1 E0 E0 X X X F15 F14 X F15 F14 Figure 7 Interface Timing in Microcontroller Mode SCLK FS DIN X D15 D14 D1 D0 E1 X Figure 8 Interface Timing in DSP Mode The operating mode is selected using pin 17 (MODE). MODE PIN (17) INTERFACE MODE HIGH Microcontroller LOW or unconnected DSP mode Table 2 Interface Mode Selection SERIAL CLOCK AND UPDATE RATE Figure 1 shows the interface timing. The maximum serial clock rate is: f SCLK max = 1 = 31MHz tWH min + tWL min Since a data word contains 16 bits, the sample rate is limited to f s max = 1 16(tWH min + tWL min ) = 1.95MHz However, the DAC settling time to 10 bits accuracy limits the response time of the analogue output for large input step transitions. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 9 WM2631 Production Data DAISY CHAINING MULTIPLE DEVICES OCTAL DAC #1 DIN SCLK FS LOADB DOUT DIN SCLK FS LOADB DOUT DIN SCLK FS LOADB DOUT DIN SCLK FS LOADB The DOUT output (pin 19) provides the data sampled on DIN with a delay of 16 clock cycles. This signal can be used to control another WM2631 or similar device in a daisy-chain type circuit. OCTAL DAC #2 OCTAL DAC #3 Figure 9 Daisy Chaining SOFTWARE CONFIGURATION OPTIONS DATA FORMAT The WM2631 is controlled with a 16-bit code consisting of four address bits, A0-A3, and 12 data bits. D15 D14 D13 D12 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Table 3 Input Data Format Using the four address bits, 16 different registers can be addressed. A3 A2 A1 A0 REGISTER 0 0 0 0 DAC A Code 0 0 0 1 DAC B Code 0 0 1 0 DAC C Code 0 0 1 1 DAC D Code 0 1 0 0 DAC E Code 0 1 0 1 DAC F Code 0 1 1 0 DAC G Code 0 1 1 1 DAC H Code 1 0 0 0 Control Register 0 1 0 0 1 Control Register 1 1 0 1 0 Preset all DACs 1 0 1 1 RESERVED 1 1 0 0 DAC A and complement B 1 1 0 1 DAC C and complement D 1 1 1 0 DAC E and complement F 1 1 1 1 DAC G and complement H Table 4 Register Map WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 10 WM2631 Production Data DAC A TO H CODE REGISTERS Addresses 0 to 7 are the DAC registers. Bits D11 (MSB) to D2 (LSB) from these registers are transferred to the respective DAC when the LOADB input (pin 18) is low. Bits D1 and D0 are unused and should be set to 0. For instantaneous updating, LOADB can be held low permanently. CONTROL REGISTER 0 Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power Down and Data Input Format. BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X X X X PD DO R1 R0 IM Default X X X X X X X 0 0 0 0 0 Table 5 Control Register 0 Map BIT DESCRIPTION 0 1 PD Full device Power Down Normal Power Down DO DOUT Enable Disabled Enabled R1 Int / Ext Reference Select External Internal R0 Internal Reference Select 1.024V 2.048V IM Input Mode Straight Binary Two’s Complement X Reserved Table 6 Control Register 0 Functionality CONTROL REGISTER 1 Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of the device. The settling time in fast mode is typically 1µs. In slow mode, the settling time is typically 3µs and power consumption is reduced. BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function X X X X PGH PEF PCD PAB SGH SEF SCD SAB Default X X X X 0 0 0 0 0 0 0 0 Table 7 Control Register 1 Map BIT DESCRIPTION 0 1 PXY Power Down DACs X and Y Normal Power Down SXY Speed Setting for DACs X and Y Slow Fast Table 8 Control Register 1 Functionality DAC PRESET REGISTER The Preset register (address 10) makes it possible to update all eight DACs at the same time. The value stored in this register becomes the digital input to all the DACs when the asynchronous PREB input (pin 5) is driven low. If no data has previously been written to the preset register, all DACs are set to zero scale. TWO-CHANNEL REGISTERS The two-channel registers (addresses 12 to 15) provide a ‘differential output’ function where writing data to one DAC will automatically write the complement to the other DAC in the pair. For example, writing a value of 1023 to address 12 will set DAC A to full scale and DAC B to zero scale. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 11 WM2631 Production Data PROGRAMMABLE INTERNAL REFERENCE The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10MΩ and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. REF1 REF0 REFERENCCE 0 0 External (default) 0 1 1.024V 1 0 2.048V 1 1 External Table 9 Programmable Internal Reference APPLICATIONS INFORMATION LINEARITY, OFFSET, AND GAIN ERROR Amplifiers operating from a single supply can have positive or negative voltage offsets. With a positive offset, the output voltage changes on the first code transition. However, if the offset is negative, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. This is because with the most negative supply rail being ground, any attempt to drive the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the transfer function shown in Figure 10. Output Voltage 0V Negative Offset DAC code Figure 10 Effect of Negative Offset This offset error, not the linearity error, produces the breakpoint. The transfer function would follow the dotted line if the output buffer could drive below the ground rail. DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs at 1), disregarding offset and full-scale errors. However, due to the breakpoint in the transfer function, single supply operation does not allow for adjustment when the offset is negative. In such cases, the linearity is therefore measured between full-scale and the lowest code that produces a positive (nonzero) output voltage. POWER SUPPLY DECOUPLING AND GROUNDING Printed circuit boards with separate analogue and digital ground planes deliver the best system performance. The two ground planes should be connected together at the low impedance power supply source. Ground currents should be managed so as to minimise voltage drops across the ground planes. A 0.1µF decoupling capacitor should be connected between the positive supply and ground pins of the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analogue supply from the digital supply. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 12 WM2631 Production Data PACKAGE DIMENSIONS DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm) b DM008.D e 20 11 E1 E GAUGE PLANE 1 θ 10 D 0.25 c A A2 L A1 -C0.1 C SEATING PLANE Symbols A A1 A2 b c D e E E1 L θ REF: MIN ----0.05 0.80 0.19 0.09 6.40 4.30 0.45 o 0 Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 ----- MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 0.75 o 8 JEDEC.95, MO-153 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 April 2001 13