TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com 1-A, Positive Fixed Voltage, Low-Dropout Regulator FEATURES DESCRIPTION • • The TLV1117LV series of low-dropout (LDO) linear regulators is a low input voltage version of the popular 1117 voltage regulator. 1 2 • • • • • • • • • 1.5% Typical Accuracy Low IQ: 100 μA (max) – 500 times lower than standard 1117 devices VIN: 2.0 V to 5.5 V – Absolute maximum VIN = 6.0 V Stable with 0-mA Output Current Low Dropout: 455 mV at 1 A for VOUT = 3.3 V High PSRR: 65 dB at 1 kHz Minimum Ensured Current Limit: 1.1 A Stable with Cost-Effective Ceramic Capacitors: – With 0-Ω ESR Temperature Range: –40°C to +125°C Thermal Shutdown and Ovecurrent Protection Available in SOT223 Package – See Package Option Addendum at end of this document for complete list of available voltage options APPLICATIONS • • • • • Set Top Boxes TVs and Monitors PC Peripherals, Notebooks, Motherboards Modems and Other Communication Products Switching Power Supply Post-Regulation The TLV1117LV is an extremely low-power device that consumes 500 times lower quiescent current than traditional 1117 voltage regulators, making it suitable for applications that mandate very low standby current. The TLV1117LV family of LDOs is also stable with 0 mA of load current; there is no minimum load requirement, making it an ideal choice for applications where the regulator is required to power very small loads during standby in addition to large currents on the order of 1 A during normal operation. The TLV1117LV offers excellent line and load transient performance, resulting in very small magnitude undershoots and overshoots of output voltage when the load current requirement changes from less than 1 mA to more than 500 mA. A precision bandgap and error amplifier provides 1.5% accuracy. A very high power-supply rejection ratio enables usage of the device for post-regulation after a switching regulator. Other valuable features include low output noise and low-dropout voltage. The device is internally compensated to be stable with 0-Ω equivalent series resistance (ESR) capacitors. These key advantages enable the use of cost-effective, small-size ceramic capacitors. Cost-effective capacitors that have higher bias voltages and temperature derating can also be used if desired. The TLV1117LV series is available in a SOT223 package. OUTPUT TLV1117LVxxDCY 3 INPUT 2 OUTPUT 1 GND Figure 1. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TLV1117LVvv(A)yyyz VOUT VV is the nominal output voltage (for example, 33 = 3.3 V). YYY is the package designator. Z is the package quantity. Use R for reel (2500 pieces), and T for tape (250 pieces). (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) At TJ = +25°C (unless otherwise noted). All voltages are with respect to GND. VALUE Voltage Current MIN MAX UNIT Input voltage range, VIN –0.3 +6.0 V Output voltage range, VOUT –0.3 +6.0 V Maximum output current, IOUT Internally limited Output short-circuit duration Continuous total power dissipation Temperature Electrostatic Discharge Ratings (1) Indefinite PDISS See Dissipation Ratings Table Operating junction, TJ –55 +150 °C Storage, Tstg –55 +150 °C 2 kV 500 V Human body model (HBM) QSS 009-105 (JESD22-A114A) Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. THERMAL INFORMATION TLV1117LV THERMAL METRIC (1) DCY UNITS 3 PINS θJA Junction-to-ambient thermal resistance 62.9 θJCtop Junction-to-case (top) thermal resistance 47.2 θJB Junction-to-board thermal resistance 12.0 ψJT Junction-to-top characterization parameter 6.1 ψJB Junction-to-board characterization parameter 11.9 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. DISSIPATION RATINGS BOARD High-K (1) PACKAGE RθJC RθJA TA < +25°C DCY 47.2 62.9 1.59 W space (1) 2 The JEDEC high K (2s2p) board used to derive these data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS At VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA = +25°C, unless otherwise noted. SPACE TLV1117LV Series PARAMETER VIN TEST CONDITIONS MIN Input voltage range VOUT > 2 V VOUT DC output accuracy 1.5 V ≤ VOUT < 2 V 1.2 V ≤ VOUT < 1.5 V TYP MAX UNIT 2.0 5.5 V –1.5 +1.5 % –2 +2 % –40 +40 mV ΔVO/ΔVIN Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA 1 5 mV ΔVO/ΔIOUT Load regulation 0 mA ≤ IOUT ≤ 1 A 1 35 mV VOUT < 3.3 V VDO Dropout voltage (1) VIN = 0.98 x VOUT(NOM) VOUT ≥ 3.3 V (1) (2) IOUT = 200 mA 115 mV IOUT = 500 mA 285 mV IOUT = 800 mA 455 IOUT = 1 A 570 mV 800 mV IOUT = 200 mA 90 mV IOUT = 500 mA 230 mV IOUT = 800 mA 365 IOUT = 1 A 455 700 mV 100 µA mV ICL Output current limit VOUT = 0.9 × VOUT(NOM) IQ Quiescent current IOUT = 0 mA 50 PSRR Power-supply rejection ratio VIN = 3.3 V, VOUT = 1.8 V, IOUT = 500 mA, f = 100 Hz 65 dB VN Output noise voltage BW = 10 Hz to 100 kHz, VIN = 2.8 V, VOUT = 1.8 V, IOUT = 500 mA 60 µVRMS tSTR Startup time (2) COUT = 1.0 µF, IOUT = 1 A 100 µs UVLO Undervoltage lockout VIN rising 1.95 V Shutdown, temperature increasing +165 °C Reset, temperature decreasing +145 °C TSD Thermal shutdown temperature TJ Operating junction temperature 1.1 –40 A +125 °C VDO is measured for devices with VOUT(NOM) = 2.5 V so that VIN = 2.45 V. Startup time = time from when VIN asserts to when output is sustained at a value greater than or equal to 0.98 × VOUT(NOM). Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 3 TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN OUT Current Limit Thermal Shutdown UVLO Bandgap LOGIC TLV1117LV Series GND Figure 2. TLV1117LV Block Diagram PIN CONFIGURATIONS OUTPUT DCY PACKAGE SOT223 (TOP VIEW) 3 INPUT 2 OUTPUT 1 GND PIN DESCRIPTIONS TLV1117LV NAME (1) 4 (1) TLV1117LVDCY DESCRIPTION IN 3 Input pin. See Input and Output Capacitor Requirements in the Application Information section for more details. OUT 2, Tab GND 1 Regulated output voltage pin. See Input and Output Capacitor Requirements in the Application Information section for more details. Ground pin Shaded cells indicate preview device. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS At VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA = +25°C, unless otherwise noted. LINE REGULATION LINE REGULATION 1.9 1.9 1.85 1.8 +125°C +85°C +25°C -40°C 1.75 VOUT = 1.8 V IOUT = 1 A Output Voltage (V) Output Voltage (V) VOUT = 1.8 V IOUT = 10 mA 1.85 1.8 1.75 1.7 +85°C +25°C -40°C 1.7 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 3.3 3.5 3.7 3.9 Input Voltage (V) 4.1 4.3 4.5 4.7 4.9 5.1 5.3 Figure 3. Figure 4. LOAD REGULATION DROPOUT VOLTAGE vs INPUT 1200 1.9 VOUT = 1.8 V +85°C +25°C -40°C 1.85 1.8 +125°C +85°C +25°C -40°C 1.75 Dropout Voltage (mV) 1000 Output Voltage (V) 5.5 Input Voltage (V) 800 600 400 200 0 1.7 0 100 200 300 400 500 600 700 800 900 1000 2 2.5 3 Output Current (mA) 4 3.5 4.5 Input Voltage (V) Figure 5. Figure 6. DROPOUT VOLTAGE vs OUTPUT OUTPUT VOLTAGE vs TEMPERATURE 1.9 600 VOUT = 1.8 V 400 300 200 +125°C +85°C +25°C -40°C 100 Output Voltage (V) Dropout Voltage (mV) 500 1.85 1.8 1.75 10 mA 500 mA 1.7 0 0 100 200 300 400 500 600 700 800 900 1000 Output Current (mA) Figure 7. Copyright © 2011, Texas Instruments Incorporated -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 8. Submit Documentation Feedback 5 TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA = +25°C, unless otherwise noted. QUIESCENT CURRENT vs LOAD CURRENT LIMIT vs INPUT VOLTAGE 1.8 600 1.78 1.76 400 300 200 +125°C +85°C +25°C -40°C 100 Current Limit (mA) Quiescent Current (mA) 500 1.74 1.72 1.7 1.68 1.66 1.64 +85°C +25°C -40°C 1.62 1.6 0 0 3.3 3.5 100 200 300 400 500 600 700 800 900 1000 3.7 3.9 4.1 4.3 Figure 9. POWER-SUPPLY REJECTION RATIO vs FREQUENCY POWER-SUPPLY REJECTION RATIO vs FREQUENCY IOUT = 500 mA IOUT = 150 mA IOUT = 30 mA 80 70 60 50 40 30 20 10 VIN - VOUT = 3 V 10 100 1k 10 k 100 k 1M Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 5.5 5.1 5.3 90 0 IOUT = 500 mA IOUT = 150 mA IOUT = 30 mA 80 70 60 50 40 30 20 10 VIN - VOUT = 1.5 V 0 10 M 10 1M 10 M SPECTRAL NOISE DENSITY vs FREQUENCY 10 f = 120 Hz f = 10 kHz 70 f = 1 kHz f = 100 kHz 50 f = 1 MHz f = 10 MHz 30 100 k Figure 12. f = 50 Hz 40 10 k Figure 11. 80 60 1k Frequency (Hz) 20 10 Noise Spectral Density (mV/?Hz) 90 100 Frequency (Hz) POWER-SUPPLY REJECTION RATIO vs OUTPUT CURRENT Power-Supply Rejection Ratio (dB) 4.9 Figure 10. 90 1 0.1 0.01 VIN - VOUT = 1.5 V 0 0.001 0 100 200 300 400 500 600 700 Output Current (mA) Figure 13. 6 4.7 4.5 Input Voltage (V) Output Current (mA) Submit Documentation Feedback 800 900 1000 10 100 1k 10 k 100 k 1M 10 M Frequency (Hz) Figure 14. Copyright © 2011, Texas Instruments Incorporated TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA = +25°C, unless otherwise noted. 500 mA LOAD TRANSIENT RESPONSE 200 mA to 500 mA, COUT = 10 μF VIN = 2.8 V IOUT 200 mA 200 mA/div 200 mA/div LOAD TRANSIENT RESPONSE 200 mA to 500 mA, COUT = 1 μF 500 mA VIN = 2.8 V IOUT 200 mA 50 mV/div VOUT 50 ms/div Figure 15. Figure 16. LOAD TRANSIENT RESPONSE 1 mA to 500 mA, COUT = 1 μF LOAD TRANSIENT RESPONSE 1 mA to 500 mA, COUT = 10 μF VIN = 2.8 V 500 mA IOUT 50 mV/div 1 mA 500 mA/div 50 ms/div VOUT 500 mA IOUT 1 mA VOUT 50 ms/div Figure 18. LOAD TRANSIENT RESPONSE 200 mA to 1 A, COUT = 1 μF LOAD TRANSIENT RESPONSE 200 mA to 1 A, COUT = 10 μF 1A IOUT 200 mA 500 mA/div 50 ms/div Figure 17. 100 mV/div 100 mV/div 500 mA/div 50 mV/div 500 mA/div 50 mV/div VOUT VOUT 1A IOUT 200 mA VOUT 50 ms/div 50 ms/div Figure 19. Figure 20. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 7 TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA = +25°C, unless otherwise noted. LOAD TRANSIENT RESPONSE 1 mA to 1 A, COUT = 1 μF IOUT 100 mV/div 1 mA VOUT 1A 500 mA/div 1A IOUT 1 mA VOUT 50 ms/div Figure 21. Figure 22. LINE TRANSIENT RESPONSE VOUT = 1.8 V, IOUT = 10 mA LINE TRANSIENT RESPONSE VOUT = 1.8 V, IOUT = 500 mA 4.3 V 3.3 V 5 mV/div VIN 1 V/div 50 ms/div VOUT 4.3 V 3.3 V VIN VOUT 200 ms/div 200 ms/div Figure 23. Figure 24. LINE TRANSIENT RESPONSE VOUT = 1.8 V, IOUT = 1 A LINE TRANSIENT RESPONSE VOUT = 1.8 V, IOUT = 10 mA 4.3 V 3.3 V 10 mV/div VIN 1 V/div 500 mA/div 100 mV/div 1 V/div 5 mV/div 1 V/div 10 mV/div 8 LOAD TRANSIENT RESPONSE 1 mA to 1 A, COUT = 10 μF VOUT 5.5 V 3.3 V VIN VOUT 200 ms/div 200 ms/div Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 1.5 V; IOUT = 10 mA, COUT = 1.0 μF, and TA = +25°C, unless otherwise noted. 5.5 V 3.3 V VIN 1 V/div LINE TRANSIENT RESPONSE VOUT = 1.8 V, IOUT = 1 A 10 mV/div 10 mV/div 1 V/div LINE TRANSIENT RESPONSE VOUT = 1.8 V, IOUT = 500 mA VOUT 5.5 V 3.3 V VIN VOUT 200 ms/div 200 ms/div Figure 27. Figure 28. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9 TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION The TLV1117LV is a low quiescent current linear regulator designed for high current applications. Unlike typical high current linear regulators, the TLV1117LV series consume significantly less quiescent current. These devices deliver excellent line and load transient performance. The device is low noise, and exhibits a very good power-supply rejection ratio (PSRR). As a result, it is ideal for high current applications that require very sensitive power-supply rails. This family of regulators offers both current limit and thermal protection. The operating junction temperature range of the device is –40°C to +125°C. Input and Output Capacitor Requirements For stability, 1.0-μF ceramic capacitors are required at the output. Higher-valued capacitors improve transient performance. X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. Unlike traditional linear regulators that need a minimum ESR for stability, the TLV1117LV series are ensured to be stable with no ESR. Therefore, cost-effective ceramic capacitors can be used with these devices. Effective output capacitance that takes bias, temperature, and aging effects into consideration must be greater than 0.5 μF to ensure stability of the device. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1.0-μF, low-ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located physically close to the power source. If source impedance is greater than 2 Ω, a 0.1-μF input capacitor may also be necessary to ensure stability. Board Layout Recommendations to Improve PSRR and Noise Performance Input and output capacitors should be placed as close to the device pins as possible. To improve characteristic ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. Higher value ESR capacitors may degrade PSRR performance. Internal Current Limit The TLV1117LV internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and can be calculated by the formula: VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details The PMOS pass element in the TLV1117LV device has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited; if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. Dropout Voltage The TLV1117LV uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout Transient Response As with any regulator, increasing the size of the output capacitor reduces over-/undershoot magnitude. 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TLV1117LV Series www.ti.com SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 Undervoltage Lockout (UVLO) The TLV1117LV uses an undervoltage lockout circuit keep the output shut off until internal circuitry operating properly. Thermal Information Thermal protection disables the output when the junction temperature rises to approximately +165°C,allowing the device to cool. When the junction temperature cools to approximately +145°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. The internal protection circuitry of the TLV1117LV has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV1117LV into thermal shutdown degrades device reliability. Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 1: PD = (VIN - VOUT) IOUT (1) Package Mounting Current solder pad footprint recommendations for the TLV1117LV are available from the Texas Instruments web site at www.ti.com. The mechanical drawing for the DCY (SOT223) package and the recommended land pattern for the DCY (SOT223) package are both appended to this data sheet. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 11 TLV1117LV Series SBVS160A – MAY 2011 – REVISED SEPTEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers from previous revisions may differ from page numbers in the current version. Changes from Original (May, 2011) to Revision A Page • Updated front-page figure ..................................................................................................................................................... 1 • Corrected errors in pin numbers listed in Pin Descriptions table and shown in device pinout ............................................. 4 • Deleted example mechanical drawing and land pattern figures (Figure 29 and Figure 30, respectively) .......................... 11 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV12DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV15DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV15DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV18DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV18DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV25DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV25DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV28DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV28DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV30DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV30DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV33DCYR ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLV1117LV33DCYT ACTIVE SOT-223 DCY 4 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples (Requires Login) TLV1117LV12DCYR (1) (3) PACKAGE OPTION ADDENDUM www.ti.com 5-Jul-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TLV1117LV12DCYR SOT-223 DCY 4 2500 330.0 12.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV12DCYT SOT-223 DCY 4 250 177.8 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV15DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV15DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 TLV1117LV15DCYT SOT-223 DCY 4 250 177.8 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV15DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 TLV1117LV18DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV18DCYT SOT-223 DCY 4 250 177.8 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV25DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV25DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 TLV1117LV25DCYT SOT-223 DCY 4 250 177.8 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV25DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 TLV1117LV28DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 TLV1117LV28DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV28DCYT SOT-223 DCY 4 250 177.8 12.4 7.05 7.45 1.88 8.0 12.0 Q3 TLV1117LV28DCYT SOT-223 DCY 4 250 180.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 TLV1117LV30DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 TLV1117LV30DCYR SOT-223 DCY 4 2500 330.0 12.4 7.05 7.45 1.88 8.0 12.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TLV1117LV30DCYT SOT-223 DCY 4 250 177.8 12.4 TLV1117LV30DCYT SOT-223 DCY 4 250 180.0 12.4 TLV1117LV33DCYR SOT-223 DCY 4 2500 330.0 TLV1117LV33DCYT SOT-223 DCY 4 250 177.8 W Pin1 (mm) Quadrant 7.05 7.45 1.88 8.0 12.0 Q3 7.05 7.4 1.9 8.0 12.0 Q3 12.4 7.05 7.45 1.88 8.0 12.0 Q3 12.4 7.05 7.45 1.88 8.0 12.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV1117LV12DCYR SOT-223 DCY 4 2500 358.0 335.0 35.0 TLV1117LV12DCYT SOT-223 DCY 4 250 358.0 335.0 35.0 TLV1117LV15DCYR SOT-223 DCY 4 2500 358.0 335.0 35.0 TLV1117LV15DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0 TLV1117LV15DCYT SOT-223 DCY 4 250 358.0 335.0 35.0 TLV1117LV15DCYT SOT-223 DCY 4 250 340.0 340.0 38.0 TLV1117LV18DCYR SOT-223 DCY 4 2500 358.0 335.0 35.0 TLV1117LV18DCYT SOT-223 DCY 4 250 358.0 335.0 35.0 TLV1117LV25DCYR SOT-223 DCY 4 2500 358.0 335.0 35.0 TLV1117LV25DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0 TLV1117LV25DCYT SOT-223 DCY 4 250 358.0 335.0 35.0 TLV1117LV25DCYT SOT-223 DCY 4 250 340.0 340.0 38.0 TLV1117LV28DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV1117LV28DCYR SOT-223 DCY 4 2500 358.0 335.0 35.0 TLV1117LV28DCYT SOT-223 DCY 4 250 358.0 335.0 35.0 TLV1117LV28DCYT SOT-223 DCY 4 250 340.0 340.0 38.0 TLV1117LV30DCYR SOT-223 DCY 4 2500 340.0 340.0 38.0 TLV1117LV30DCYR SOT-223 DCY 4 2500 358.0 335.0 35.0 TLV1117LV30DCYT SOT-223 DCY 4 250 358.0 335.0 35.0 TLV1117LV30DCYT SOT-223 DCY 4 250 340.0 340.0 38.0 TLV1117LV33DCYR SOT-223 DCY 4 2500 358.0 335.0 35.0 TLV1117LV33DCYT SOT-223 DCY 4 250 358.0 335.0 35.0 Pack Materials-Page 3 MECHANICAL DATA MPDS094A – APRIL 2001 – REVISED JUNE 2002 DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE 6,70 (0.264) 6,30 (0.248) 3,10 (0.122) 2,90 (0.114) 4 0,10 (0.004) M 3,70 (0.146) 3,30 (0.130) 7,30 (0.287) 6,70 (0.264) Gauge Plane 1 2 0,84 (0.033) 0,66 (0.026) 2,30 (0.091) 4,60 (0.181) 1,80 (0.071) MAX 3 0°–10° 0,10 (0.004) M 0,25 (0.010) 0,75 (0.030) MIN 1,70 (0.067) 1,50 (0.059) 0,35 (0.014) 0,23 (0.009) Seating Plane 0,08 (0.003) 0,10 (0.0040) 0,02 (0.0008) 4202506/B 06/2002 NOTES: A. B. C. D. All linear dimensions are in millimeters (inches). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC TO-261 Variation AA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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