FUJITSU MB15F73UL

Dec. 2000
Edition 2.0
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F73UL
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DESCRIPTION
The Fujitsu MB15F73UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2250MHz and a
600MHz prescalers. A 64/65 or a 128/129 for the 2250MHz prescaler, and a 8/9 or a 16/17 for the 600MHz prescaler
can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process is used, as a result a supply current is typically 3.2mA typ. at 2.7V. The supply voltage
range is from 2.4V to 3.6V. A refined charge pump supplies well-balanced output current with 1.5mA and 6mA
selectable by serial data. The data format is same as the previous one MB15F03SL, MB15F73SP. Fast locking is
acheived for adopting the new circuit.
The new package(BCC20) decreases a mount area of MB15F73UL more than 30% comparing with the former
BCC16(for dual PLL).
MB15F73UL is ideally suited for wireless mobile communications, such as GSM and CDMA.
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FEATURES
• High frequency operation: RF synthesizer : 2250MHz max
IF synthesizer : 600MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current : ICC = 3.2 mA typ. (VCC = Vp=2.7V, Ta=25°C, SW=0 in RF, IF locking state)
• Direct power saving function : Power supply current in power saving mode
Typ. 0.1 µA(Vcc=Vp=2.7V, Ta=25°C), Max. 10 µA(Vcc=Vp=2.7V)
• Dual modulus prescaler : 2250MHz prescaler(64/65 or 128/129) / 600MHz prescaler(8/9 or 16/17)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• On-chip phase comparator for fast lock and low noise
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to 85°C
• Sireal data format compatible with MB15F03SL
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e
Pr
20-pin, Plastic TSSOP
n
i
im
.
y
ar
20-pad, Plastic BCC
(LCC-20P-M05)
(FPT-20P-M06)
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Dec. 2000
Edition 2.0
MB15F73UL
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PIN ASSIGNMENT
OSCIN
1
20
Clock
GND
2
19
Data
finIF
3
18
LE
4
17
finRF
XfinIF
TOP 16
VIEW
15
6
XfinRF
7
14
VccRF
VpIF
8
13
PSRF
DoIF
9
12
VpRF
LD/fout
10
11
DoRF
GNDIF
VccIF
PSIF
5
FPT-20P-M06
2
GNDRF
Data
OSCIN
GND Clock
finIF
1
20 19 18 17
16
LE
XfinIF
2
15
finRF
GNDIF
3
14
XfinRF
VccIF
4
13
GNDRF
PSIF
5
12
VCCRF
VpIF
6
11
PSRF
TOP
VIEW
7
8
9 10
DoIF
DoRF
VpRF
LD/fout
LCC-20P-M05
Dec. 2000
Edition 2.0
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MB15F73UL
PIN DESCRIPTIONS
Pin No.
TSSOP
BCC
Pin
name
I/O
Descriptions
1
19
OSCIN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
2
20
GND
-
Ground for OSC input buffer and the shift registor circuit.
3
1
finIF
I
Prescaler input pin for the IF-PLL section.
Connection to an external VCO should be AC coupling.
4
2
XfinIF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
5
3
GNDIF
-
Ground for the IF-PLL section.
6
4
VccIF
-
Power supply voltage input pin for the IF-PLL section(except for the
charge pump circuit), the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
7
5
PSIF
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode
8
6
VpIF
-
Power supply voltage input pin for the IF-PLL charge pump.
9
7
DoIF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
10
8
LD/fout
O
Lock detect signal output(LD)/ phase comparator monitoring outut
(fout). The output signal is selected by a LDS bit in a serial data.
LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal
11
9
DoRF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
12
10
VpRF
-
Power supply voltage input pin for the RF-PLL charge pump.
13
11
PSRF
I
Power saving mode control for the RF-PLL section. This pin must be
set at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode
14
12
VccRF
-
Power supply voltage input pin for the RF-PLL section(except for the
charge pump circuit).
15
13
GNDRF
-
Ground for the RF-PLL section.
16
14
XfinRF
I
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
17
15
finRF
I
Prescaler input pin for the RF-PLL.
Connction to an external VCO should be AC coupling.
18
16
LE
I
Load enable signal input (with the schmitt trigger circuit.)
When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data.
19
17
Data
I
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
20
18
Clock
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the
clock.
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Dec. 2000
Edition 2.0
MB15F73UL
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BLOCK DIAGRAM
VCCIF
(4) 6
PSIF 7
(5)
Intermittent
mode
control
(IF–PLL)
(1)
finIF 3
Xfin IF 4
(2)
3-bit latch
7-bit latch
11-bit latch
LDS SWIF FCIF
Binary 7-bit
swallow counter
Binary 11-bit
programmable
counter(IF–PLL)
(IF–PLL)
fpIF
VpIF
GNDIF
5 (3)
(6) 8
Phase
comp.
Charge Current
pump Switch
(IF–PLL)
(IF–PLL)
9 DoIF
(7)
Prescaler
(IF–PLL)
8/9,16/17
2-bit latch
T1
T2
14-bit latch
Lock
Det.
1-bit latch
(IF–PLL)
C/P
setting
current
Binary 14–bit programmable ref.
counter(IF–PLL)
LDIF
frIF
OSCin 1
(19)
Fast
lock
tuning
AND
Selector
LD
frIF
frRF
fpIF
fpRF
OR
T1
T2
2-bit latch
(15)
finRF 17
Xfin RF 16
(14)
C/P
setting
current
14-bit latch
1-bit latch
Prescaler
Lock
Det.
frRF
(RF–PLL)
64/65,
128/129
Intermittent
mode
control
3-bit latch
Binary 7-bit
swallow counter
(RF–PLL)
Binary 11-bit
programmable
counter(RF–PLL)
7-bit latch
11-bit latch
Phase
comp.
(RF–PLL)
fpRF
Fast
lock
tuning
Charge Current
pump
Switch
(RF–PLL)
(RF–PLL)
LE 18
(16)
Schmitt
circuit
Data 19
(17)
Schmitt
circuit
Clock 20
(18)
Schmitt
circuit
Latch selector
C
N
C
N
1
2
23-bit shift
register
2 (20)
GND
O -- TSSOP 20
( ) -- BCC 20
4
10 LD/fout
(8)
(RF–PLL)
LDS SWRF FCRF
PSRF 13
(11)
Binary 14-bit programmable ref.
counter(RF–PLL)
(12)14
VccRF
15 (13)
GNDRF
12 (10)
VpRF
11 DoRF
(9)
Dec. 2000
Edition 2.0
n
MB15F73UL
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VCC
–0.5 to +4.0
V
Vp
Vcc to +4.0
V
VI
–0.5 to VCC +0.5
V
VO
GND to Vcc
V
LD/fout
VDO
GND to Vp
V
Do
Tstg
–55 to +125
°C
Power supply voltage
Input voltage
Output voltage
Storage temperature
Remark
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Remark
3.6
V
VCCRF = VCCIF
2.7
3.6
V
GND
–
VCC
V
–40
–
+85
°C
Min.
Typ.
Max.
VCC
2.4
2.7
Vp
Vcc
Input voltage
VI
Operating temperature
Ta
Power supply voltage
Handling Precautions
(1) VccRF,VpRF,VccIF and VpIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VccRF,VpRF,VccIF and VpIF to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
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Dec. 2000
Edition 2.0
MB15F73UL
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ELECTRICAL CHARACTERISTICS
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
"H" level Input voltage
"L" level Input voltage
"L" level Input current
"H" level output voltage
mA
ICCRF
finRF=2000MHz
VccRF=VpRF=2.7V
1.3
2.0
2.8
mA
IPSIF
PSIF=PSRF= ”L”
–
0.1*2
10
µA
IPSRF
PSIF=PSRF= ”L”
–
0.1
10
µA
finIF*3
finIF
IF PLL
50
–
600
MHz
finRF*3
finRF
RF PLL
200
–
2250
MHz
OSCIN
fosc
3
–
40
MHz
finIF
PfinIF
IF PLL, 50 Ω system
-15
–
+2
dBm
finRF
PfinRF
RF PLL, 50 Ω system
-15
–
+2
dBm
OSCIN
VOSC
0.5
–
VCC
Vp-p
Data,
Clock,
LE
VIH
Schmitt trigger input
Vcc ×
0.7+0.4
–
–
VIL
Schmitt trigger input
–
–
Vcc×
0.3-0.4
Data,
Clock,
LE, PS
OSCIN
LD/fout
"L" level output voltage
"H" level output voltage
"L" level output voltage
High impedance
cutoff current
"H"level Output current
"L" level Output current
Unit
1.7
"L" level Input voltage
"H" level Input current
Max.
1.2
–
–
DoIF
DoRF
DoIF
DoRF
LD/fout
*2
VIH
–
Vcc×
0.7
–
–
VIL
–
–
–
Vcc×
0.3
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
IIH
–
0
–
+100
IIL*4
–
–100
–
0
Vcc –
0.4
–
–
–
–
0.4
PS
"L" level Input current
Typ.
0.8
"H" level Input voltage
"H" level Input current
Min.
finIF=480MHz
VccIF=VpIF=2.7V
Power saving current*9
Input sensitivity
Value
ICCIF
Power supply current*1
Operating frequency
Condition
VOH
VCC=Vp=2.7V, IOH=–1mA
VOL
VCC=Vp=2.7V, IOL=1mA
VDOH
VCC=Vp=2.7V, IDOH=-0.5mA
Vp –
0.4
–
–
VDOL
VCC=Vp=2.7V, IDOL=0.5mA
–
–
0.4
IOFF
VCC=Vp=2.7V,
VOFF=0.5V to Vp–0.5V
–
–
2.5
IOH*4
VCC = Vp = 2.7V
–
–
-1.0
IDOL
VCC = Vp = 2.7V
1.0
–
–
V
V
µA
µA
V
V
nA
mA
(Continued)
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Dec. 2000
Edition 2.0
MB15F73UL
(Continued)
Ta =(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
"H"level Output current
IDOH*4
DoTX*8
DoRX
"L" level Output current
IDOL
Charge pump
current rate
Min.
Typ.
Max.
CS bit ="1"
-8.2
-6.0
-4.1
CS bit ="0"
-2.2
-1.5
-0.8
VCC=Vp
CS bit ="1"
=2.7 V
VDOL=Vp /2
CS bit ="0"
Ta= 25°C
4.1
6.0
8.2
0.8
1.5
2.2
VCC=Vp
=2.7 V
VDOH=Vp /2
Ta= 25°C
Unit
mA
IDOL/IDOH
IDOMT*5
VDO=Vp/2
–
3
–
%
vs VDO
IDOVD*6
0.5V < VDO < Vp-0.5V
–
10
–
%
vs Ta
IDOTA*7
-40°C < Ta < 85 °C,
VDO=Vp/2
–
5
–
%
Conditions; fosc=12.8MHz, Ta = 25°C, SW="L" in locking state.
VccIF=VpIF=VccRF=VpRF=2.7V, fosc=12.8MHz, Ta = 25°C, in power saving mode.
AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
The symbol "-"(minus) means direction of current flow.
Vcc=Vp=2.7V, Ta=25°C ( ||I3| - |I4|| ) / [( |I3| + |I4| )/2] x 100(%)
Vcc=Vp=2.7V, Ta=25°C [( ||I2| - |I1|| ) /2 ] / [( |I1| + |I2| )/2] x 100(%) (Applied to each IDOL, IDOH)
Vcc=Vp=2.7V, [(||IDO(85C)| - |IDO(-40C)||) /2] / [(|IDO(85C)| + |IDO(-40C)|) /2] x 100(%) (Applied to each IDOL, IDOH)
When Charge pump current is measured, set LDS="0", T1="0" and T2="1".
PSIF=PSRF=GND (VIL=GND and VIH=Vcc for Clock, Data, LE)
I2
I3
IDOL
I1
IDOH
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
Value
Condition
I1
I4
I2
0.5
VP/2
Output voltage(V)
VP-0.5
VP
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Dec. 2000
Edition 2.0
MB15F73UL
n
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(P x N) + A} x fOSC ÷ R
fVCO:
P:
N:
A:
fOSC:
R:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127, condition;A < N)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
CN2
0
0
The programmable reference counter for the IF-PLL.
1
0
The programmable reference counter for the RF-PLL.
0
1
The programmable counter and the swallow counter for the IF-PLL
1
1
The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21
22 23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
C
S
X
X
X
CN1, 2
: Control bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, 2
: LD/fout output setting bit
CS
: Charge pump current select bit
X
: Dummy bits(Set "0" or "1")
NOTE: Data input with MSB first.
8
[Table. 1]
[Table. 2]
[Table. 3]
[Table. 8]
X
Dec. 2000
Edition 2.0
MB15F73UL
Programmable Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
C
N
1
C
N
2
L
D
S
S
W
F
C
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
IF/RF IF/RF
CN1, 2
N1 to N11
A1 to A7
SWIF/RF
: Control bit
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)
FCIF/RF
: Phase control bit for the phase detector(IF : FCIF, RF : FCRF)
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 3]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
Table.3 LD/fout output Selectable Bit Setting
LD/fout pin state
LDS
T1
T2
0
0
0
0
1
0
0
1
1
frIF
1
0
0
frRF
1
1
0
fpIF
1
0
1
fpRF
1
1
1
LD output
fout
output
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Dec. 2000
Edition 2.0
MB15F73UL
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 3 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(N)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note: • Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
Prescaler
divide ratio
SW = ”1”
SW = ”0”
IF-PLL
8/9
16/17
RF-PLL
64/65
128/129
Table. 7 Phase Comparator Phase Switching Data Setting
FCIF,RF = 1
FCIF,RF = 0
1
DoIF,RF
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
1
2
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
FC bit should be set.
10
VCO Output
Frequency
2
VCO Input Voltage
Dec. 2000
Edition 2.0
MB15F73UL
Table. 8 Charge Pump Current Setting
CS
Current value
1
+ 6.0 mA
0
+ 1.5 mA
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 9. PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: When power (VCC) is first applied, the device must be in standby mode, PS=Low, for at least 1µs.
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Dec. 2000
Edition 2.0
MB15F73UL
Note: • PS pin must be set at “L” for Power ON.
OFF
ON
tv > 1µs
Vcc
Clock
Data
LE
tps > 100ns
PS
(1)
(2)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1µs later after power supply remains stable(Vcc > 2.2V).
(3) Relase power saving mode (PS: L → H) 100nS later after setting serial data.
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Edition 2.0
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MB15F73UL
SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit Invalid data
LSB
MSB
Data
Clock
LE
t2
t1
t4
t3
t5
t7
t6
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter
Min.
t1
20
t2
Typ.
Max.
Unit
Parameter
–
–
ns
t5
100
20
–
–
ns
t6
t3
30
–
–
ns
t7
t4
30
–
–
ns
Min.
Typ.
Max.
Unit
–
–
ns
20
–
–
ns
100
–
–
ns
Note: LE should be "L" when the data is transferred into the shift register.
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PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = 1)
H
DoIF/RF
Z
L
(FC bit = 0)
DoIF/RF
Z
LD Output Logic Table
RF–PLL section
LD output
Locking state / Power saving state
Locking state / Power saving state
H
Locking state / Power saving state
Unlocking state
L
Unlocking state
Locking state / Power saving state
L
Unlocking state
Unlocking state
L
IF–PLL section
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is t WL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 2/fosc: i.e. tWU > 156.3ns when foscin = 12.8 MHz
tWL < 4/fosc: i.e. tWL < 312.5ns when foscin = 12.8 MHz
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MB15F73UL
TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
fout
Oscilloscope
VpIF
0.1µF
VccIF
0.1µF
1000pF
1000pF
P.G
LD/fout DoIF VpIF
50Ω
P.G
1000pF
10
9
8
PSIF VccIF GNDIF XfinIF
7
6
5
finIF
50Ω
GND OSCin
4
3
2
1
17
18
19
20
MB15F73UL
11
1000pF
12
13
14
15
DoRF VpRF PSRF VccRF GNDRF
16
XfinRF finRF LE
Data
Clock
P.G
50Ω
VpRF
1000pF Controller (divide
ratio setting)
VccRF
0.1µF
0.1µF
Note : TSSOP-20
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APPLICATION EXAMPLE
OUTPUT
from controller
LPF
VCO
1000 pF
2.7 V
2.7 V
0.1µF
0.1µF
1000 pF
Clock
20
DATA
LE
finRF
XfinRF
GNDRF
VccRF
PSRF
VpRF
DoRF
19
18
17
16
15
14
13
12
11
10
MB15F73UL
1
OSCin
2
3
GND
finIF
4
XfinIF
5
6
7
8
9
GNDIF
VccIF
PSIF
VpIF
DoIF
LD/fout
Lock Det.
2.7 V
1000 pF
1000 pF
2.7 V
1000 pF
0.1µF
0.1µF
TCXO
OUTPUT
VCO
LPF
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
Note :TSSOP-20
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Dec. 2000
Edition 2.0
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MB15F73UL
PACKAGE DIMENSION
20 pin, Plastic SSOP
(FPT-20P-M06)
* : These dimensions do not include resin protrusion.
(Continued)
17
MB15F73UL
Dec. 2000
Edition 2.0
(Continued)
20 pad, Plastic BCC
(LCC-20P-M05)
18