FUJITSU MB15F88UL

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21370-2E
ASSP
Fractional-N
PLL Frequency Synthesizer
MB15F88UL
■ DESCRIPTION
The Fujitsu MB15F88UL is Fractional-N Phase Locked Loop (PLL) frequency synthesizer with fast lock up function.
The Fractional-N PLL operating up to 2600 MHz and the integer PLL operating up to 1200 MHz are integrated
on one chip.
The MB15F88UL is used as charge pump which is well-balanced output current with 1.5 mA and 6 mA selectable
by serial data, direct power save control and digital lock detector. In addition, the MB15F88UL adopts a new
architecture to achieve fast lock.
The new package (Thin Bump Chip Carrier20) decreases a mount area of the MB15F88UL more than 30%
comparing with the former B.C.C.16 (for dual PLL, MB15F08SL) .
The MB15F88UL is ideally suited for wireless mobile communications, such as W-CDMA.
■ FEATURES
• High frequency operation
: RX synthesizer : 2600 MHz Max
TX synthesizer : 1200 MHz Max
• Low power supply voltage
: VCC = 2.7 V to 3.6 V
• Ultra Low power supply current : ICC = 6.0 mA Typ ( VCC = Vp = 3.0 V, Ta = + 25 °C, SW = 0 in TX and RX
locking state)
• 23-bit shift register input control
(Continued)
■ PACKAGES
20-pin, plastic TSSOP
20-pad, plastic BCC
(FPT-20P-M06)
(LCC-20P-M05)
MB15F88UL
(Continued)
• Direct power saving function : Power supply current in power saving mode
Typ 0.1 µA (VCC = Vp = 3.0 V, Ta = + 25 °C) , Max 10 µA (VCC = Vp = 3.0 V)
• Fractional function : selectable modulo 5 or 8/Acheiving fast lock and low phase noise (implemented in RX)
• Dual modulus prescaler : 2600 MHz prescaler (32/33 fixed) /1200 MHz prescaler (16/17 or 32/33)
• Serial input 14-bit programmable reference divider : R = 8 to 16,383
• Serial input programmable divider consisting of :
RX section - Binary 5-bit swallow counter : 0 to 31
- Binary 10-bit programmable counter : 34 to 1,023
- Binary 4-bit fractional counter numerator : 0 to 15
TX section - Binary 5-bit swallow counter : 0 to 31
- Binary 11-bit programmable counter : 3 to 2,047
• On-chip phase comparator for fast lock and low noise
• Operating temperature : Ta = −40 °C to + 85 °C
• Small package Bump Chip Carrier.0 (3.4 mm × 3.6 mm × 0.6 mm)
■ PIN ASSIGNMENTS
(BCC-20)
TOP VIEW
(TSSOP-20)
TOP VIEW
OSCIN
1
20
Clock
GND
2
19
Data
finTX
3
18
LE
XfinTX
4
17
finRX
GNDTX
5
16
XfinRX
VCCTX
6
15
GNDRX
PSTX
7
14
VCCRX
VpTX
8
13
PSRX
DOTX
9
12
VpRX
LD/fout
10
11
DORX
(FPT-20P-M06)
2
OSCIN Data
GND Clock
finTX
1
20 19 18 17 16
XfinTX
2
finRX
GNDTX
VCCTX
3
4
15
14
GNDRX
PSTX
5
13
12
VpTX
6
7
8
9 10 11
DOTX DORX
LD/fout VpRX
(LCC-20P-M05)
LE
XfinRX
VCCRX
PSRX
MB15F88UL
■ PIN DESCRIPTION
Pin no.
TSSOP BCC
Pin
name
I/O
Descriptions
I
The programmable reference divider input pin. TCXO should be connected with an
AC coupling capacitor.
1
19
OSCIN
2
20
GND
3
1
finTX
I
Prescaler input pin for the TX-PLL.
Connection to an external VCO should be AC coupling.
4
2
XfinTX
I
Prescaler complimentary input pin for the TX-PLL section.
This pin should be grounded via a capacitor.
5
3
GNDTX
6
4
VCCTX
7
5
PSTX
8
6
VpTX
 Power supply voltage input pin for the TX-PLL charge pump.
9
7
DoTX
O
10
8
LD/fout
11
9
DoRX
O
12
10
VpRX
 Power supply voltage input pin for the RX-PLL charge pump.
13
11
PSRX
I
Power saving mode control pin for the RX-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited. )
PSRX = “H” ; Normal mode, PSRX = “L” ; Power saving mode
14
12
VCCRX

Power supply voltage input pin for the RX-PLL section (except for the charge pump
circuit) .
15
13
GNDRX  Ground pin for the RX-PLL section.
16
14
XfinRX
I
Prescaler complimentary input pin for the RX-PLL section.
This pin should be grounded via a capacitor.
17
15
finRX
I
Prescaler input pin for the RX-PLL.
Connection to an external VCO should be AC coupling.
18
16
LE
I
Load enable signal input pin (with the schmitt trigger circuit.)
On a rising edge of load enable, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data.
19
17
Data
I
Serial data input pin (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (TX-ref counter, TX-prog. counter,
RX-ref. counter, RX-prog. counter) according to the control bit in a serial data.
20
18
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the clock.
 Ground pin for OSC input buffer and the shift register circuit.
 Ground pin for the TX-PLL section.
Power supply voltage input pin for the TX-PLL section (except for the charge pump
 circuit) , the shift register and the oscillator input buffer.
When power is OFF, latched data of TX-PLL is lost.
I
Power saving mode control pin for the TX-PLL section. This pin must be set at “L”
when the power supply is started up. (Open is prohibited.)
PSTX = “H” ; Normal mode, PSTX = “L” ; Power saving mode
Charge pump output pin for the TX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
Look detect signal output (LD) /phase comparator monitoring output (fout) pins.
O The output signal is selected by an LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal, LDS bit = “L” ; outputs LD signal
Charge pump output pin for the RX-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
3
MB15F88UL
■ BLOCK DIAGRAM
VCCTX GNDTX
(4) 6
5 (3)
11-bit latch
fpTX
Binary 11-bit
Binary 5-bit
swallow counter programmable
(TX-PLL)
counter (TX-PLL)
TX-PLL
Phase
comp.
Charge
pump
(TX-PLL)
(TX-PLL)
9 DoTX
(7)
Prescaler
(TX-PLL)
CSC
FCC
SWC
14-bit latch
Binary 14-bit programmable ref.
counter (TX-PLL)
T2
16/17,
32/33
T1
(1)
finTX 3
XfinTX 4
(2)
5-bit latch
Power
saving
LDS
PSTX 7
(5)
VpTX
(6) 8
Lock
Det.
(TX-PLL)
6-bit latch
LDTX
Slector
LDTX
LDRX
frTX
14-bit latch
10 LD/fout
(8)
frRX
fpTX
fpRX
CSF
FCF
SC2
SWF
SC1
Binary 14-bit programmable ref.
counter (RX-PLL)
OR
QM
OSCIN 1
(19)
Lock
Det.
6-bit latch
(RX-PLL)
frRX
MD2
(15)
finRX 17
XfinRX 16
(14)
PSRX 13
(11)
LE 18
(16)
frRX
Fractional
Counter
5, 8
Prescaler
Selector
fpRX
MD1
(RX-PLL)
fpRX
32/33
Power
saving
RX-PLL
Schmitt
circuit
Binary 10-bit
Binary 5-bit
swallow counter programmable
(RX-PLL)
counter (RX-PLL)
5-bit latch
10-bit latch
F
F
F
F
1
2
3
4
Phase
comp.
(RX-PLL)
Charge
pump
(RX-PLL)
4-bit latch
Latch selector
SC
SC1
SC2
Data 19
(17)
Clock 20
(18)
Schmitt
circuit
C C C
N N N
Schmitt
circuit
1 2 3
4
(RX-PLL)
23-bit shift
register
2 (20)
GND
O : TSSOP 20
( ) : BCC 20
OR
(12) 14
15 (13) 12 (10)
VccRX GNDRX VpRX
11
(9)
DoRX
MB15F88UL
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Unit
Min
Max
VCC
−0.5
+4.0
V
Vp
VCC
+4.0
V
VI
−0.5
VCC + 0.5
V
LD/fout
VO
GND
VCC
V
DO
VDO
GND
Vp
V
Tstg
−55
+125
°C
Power supply voltage
Input voltage
Output voltage
Rating
Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Remark
3.6
V
VCCRX = VCCTX
3.0
3.6
V
GND

VCC
V
−40

+85
°C
Min
Typ
Max
VCC
2.7
3.0
Vp
VCC
Input voltage
VI
Operating temperature
Ta
Power supply voltage
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F88UL
■ ELECTRICAL CHARACTERISTICS
*
(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
“H” level input voltage
“L” level input voltage
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
“H” level input current
“L” level input current
Min
Typ
Max
1.3
2.0
2.8
mA
ICCRX *1
finRX = 2500 MHz,
VCCRX = VpRX = 3.0 V
2.6
4.0
5.6
mA
IPSTX
PS = “L”

0.1 *2
10
µA
IPSRX
PS = “L”

0.1 *2
10
µA
finTX *3
finTX
TX PLL
100

1200
MHz
RX 3
finRX
RX PLL
1700

2600
MHz
OSCIN
fOSC
3

40
MHz
fin
*

finTX
PfinTX
TX PLL, 50 Ω system
−15

+2
dBm
finRX
PfinRX
RX PLL, 50 Ω system
−15

+2
dBm
OSCIN
VOSC
0.5

VCC
Vp-p
Data,
Clock,
LE
VIH
0.7VCC
+ 0.4




0.3VCC
− 0.4
PSTX
PSRX
VIH

0.7VCC


VIL



0.3VCC
Data,
Clock,
LE,
PSTX,
PSRX
IIH *4

−1.0

+1.0
IIL *4

−1.0

+1.0
IIH

0

+100
IIL *4

−100

0
VCC − 0.4




0.4
OSCIN
VIL

Schmitt triger input
Schmitt triger input
“H” level output voltage LD/
“L” level output voltage fout
VOH
VCC = Vp = 3.0 V, IOH = −1 mA
VOL
VCC = Vp = 3.0 V, IOL = 1 mA
“H” level output voltage DoTX
“L” level output voltage DoRX
VDOH
VCC = Vp = 3.0 V, IDOH = −0.5 mA Vp − 0.4


VDOL
VCC = Vp = 3.0 V, IDOL = 0.5 mA


0.4
IOFF
VCC = Vp = 3.0 V,
VOFF = 0.5 V to Vp − 0.5 V


2.5
IOH *4
VCC = Vp = 3.0 V


−1.0
IOL*4
VCC = Vp = 3.0 V
1.0


High impedance
cutoff current
Unit
finTX = 910 MHz, SWC = 0,
VCCTX = VpTX = 3.0 V
Power saving current
Input sensitivity
Value
ICCTX *1
Power supply current
Operating frequency
Condition
DoTX
DoRX
“H” level output current LD/
“L” level output current fout
V
V
µA
µA
V
V
nA
mA
(Continued)
6
MB15F88UL
(Continued)
(VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
“H” level output
current
IDOH *4
DoTX
DoRX
“L” level output
current
IDOL
IDOL/IDOH IDOMT *5
Charge pump
current rate
DOVD 6
vs VDO
I
*
vs Ta
IDOTA *7
Value
Condition
Unit
Min
Typ
Max
CS bit = “H”
−8.2
−6.0
−4.1
mA
CS bit = “L”
−2.2
−1.5
−0.8
mA
CS bit = “H”
4.1
6.0
8.2
mA
CS bit = “L”
0.8
1.5
2.2
mA
VDO = Vp / 2

3

%
0.5 V ≤ VDO ≤ Vp − 0.5 V

10

%
−40 °C ≤ Ta ≤ +85 °C,
VDO = Vp / 2

5

%
VCC = Vp = 3.0 V,
VDOH = Vp / 2,
Ta = +25 °C
VCC = Vp = 3.0 V,
VDOL = Vp / 2,
Ta = +25 °C
*1 : Conditions ; fosc = 13 MHz, Ta = +25 °C in locking state.
*2 : VCCTX = VpTX = VCCRX = VpRX = 3.0 V, fosc = 13 MHz, Ta = +25 °C, in power saving mode.
*3 : AC coupling. 1000 pF capacitor is connected.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = Vp = 3.0 V, Ta = +25 °C (||I3| − |I4||) / [ (|I3| + |I4|) / 2] × 100 (%)
*6 : VCC = Vp = 3.0 V, Ta = +25 °C [ (||I2| − |I1||) / 2] / [ (|I1| + |I2|) / 2] × 100 (%) (Applied to each lDOL and lDOH)
*7 : VCC = Vp = 3.0 V, Ta = +25 °C[ (||IDO (+85 °C) | − |IDO (–40 °C) ||) / 2] / [ (|IDO (+85 °C) | + |IDO (–40 °C) |) / 2] × 100 (%)
(Applied to each IDOL and IDOH)
I2
I3
I1
IDOL
IDOH
0.5
I1
I4
I2
Vp/2
Vp − 0.5
Vp
output voltage (V)
7
MB15F88UL
■ FUNCTIONAL DESCRIPTION
1. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RX-PLL
sections and programmable reference dividers of TX/RX-PLL sections are controlled individually.
Serial data of binary code is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
The programmable
reference counter for
the TX-PLL
The programmable
counter and the swallow
counter for the TX-PLL
The programmable
The programmable
reference counter for counter and the swallow
the RX-PLL
counter for the RX-PLL
CN1
0
1
0
1
CN2
0
0
1
1
CN3
0
0
0
0
Note : CN3 = 1 is prohibited
(1) Serial data format
Direction of data shift
LSB
2
3
0
0
0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 LDS T1
1
0
0 AC1 AC2 AC3 AC4 AC5 0
0
1
0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF9 RF10 RF11 RF12 RF13 RF14 QM SC1 SC2
1
1
0 AF1 AF2 AF3 AF4 AF5 NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NF10 F1
RC1 to RC14
AC1 to AC5
NC1 to NC11
LDS, T1, T2
SWC
FCC
CSC
RF1 to RF14
AF1 to AF5
NF1 to NF10
F1 to F4
QM
SC1, SC2
FCF
CSF
X
4
5
6
7
9
10 11 12
13
14
15
16
17
18
19
20
21
22
23
T2 SWC FCC CSC
0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 X
F2
1
F3
Control bit (CN3)
Control bit (CN2)
Control bit (CN1)
: Divide ratio setting bits for the reference counter of the TX (8 to 16383)
: Divide ratio setting bits for the swallow counter of the TX (0 to 31, A < N)
: Divide ratio setting bits for the programmable counter of the TX (3 to 2047)
: Select bits for the lock detect output or a monitoring phase comparison frequency
: Divide ratio setting for the prescaler of the TX
: Phase control bit for the phase detector of the TX
: Charge pump current select bit of the TX
: Divide ratio setting bits for the reference counter of the RX (8 to 16383)
: Divide ratio setting bits for the swallow counter of the RX (0 to 31, A < N − 2)
: Divide ratio setting bits for the programmable counter of the RX (34 to 1023)
: Fractional-N increment setting bit for the fractional accumulator (0 to 15, F < Q)
: Fractional-N modulus selection bit. “1” modulus = 8, “0” modulus = 5
: Spurious cancel set bit of the RX.
: Phase control bit for the phase detector of the RX.
: Charge pump current select bit of the RX
: Dummy bit (Set “0” or “1”)
Note: Data input with MSB first.
8
8
MSB
1
X
FCF CSF
F4
0
MB15F88UL
(2) Data Setting
• RX synthesizer Data Setting (Fractional-N)
The divide ratio can be calculated using the following equation :
fVCORX = NTOTAL × fosc÷R
NTOTAL = P × N + A + F / Q (A < N − 2, F < Q)
fVCORX
NTOTAL
fosc
R
P
N
A
F
Q
: Output frequency of external voltage controlled oscillator (VCO)
: Total division ratio from prescaler input to the phase detector input
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14 bit referance counter (8 to 16383)
: Preset divide ratio of modulus prescaler (32 fixed)
: Preset divide ratio of binary 10 bit programmable counter (34 to 1023)
: Preset divide ratio of binary 5 bit swallow counter (0 to 31)
: A numerator of fractional-N (0 to 15)
: A denominator of fractional-N “QM bit = 1” modulo 8, “QM bit = 0” modulo 5
• Binary 14-bit Programmable Reference Counter Data Setting (RF1 to RF14)
Divide ratio
(R)
RF14 RF13 RF12 RF11 RF10 RF9
RF8
RF7
RF6
RF5
RF4
RF3
RF2
RF1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1















52
0
0
0
0
0
0
0
0
1
1
0
1
0
0















16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 8 is prohibited.
• Fractional-N incremant of the fractional accumulator Data Setting (F1 to F4)
Setting value(F)
F4
F3
F2
F1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0





15
1
1
1
1
Note : F < Q, F5 = 0
• Fractional-N modulo Data Setting (Q)
QM
Modulo-Q
0
5
1
8
9
MB15F88UL
• Binary 10-bit Programable Counter Data Setting (NF1 to NF10)
Divide ratio (N)
NF10
NF9
NF8
NF7
NF6
NF5
NF4
NF3
NF2
NF1
34
0
0
0
0
1
0
0
0
1
0
35
0
0
0
0
1
0
0
0
1
1











64
0
0
0
1
0
0
0
0
0
0











1023
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 34 is prohibited.
• Binary 5-bit Swallow Counter Data Setting (AF1 to AF5)
Divide ratio (A)
AF5
AF4
AF3
AF2
AF1
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
1
0






31
1
1
1
1
1
Note : A < N − 2
• Spurious cancel Bit Setting
Spurious cancel amount
SC1
SC2
Large
0
0
Midium
0
1
Small
1
0
Note : The bits set how much the amount of spurious cancel.
If the Large is selected, a spurious is tended to become small.
• Phase Comparator Phase Switching Data Setting
FCF = “1”
FCF = “0”
DO
DO
fr > fp
H
L
fr < fp
L
H
fr = fp
Z
Z
VCO polarity
1
2
Notes : • Z = High-Z
• Depending upon the VCO and LPF polarity, FC bit should be set.
• Charge pump current select Bit Setting
CSF
10
Current value
1
±6.0 mA
0
±1.5 mA
MB15F88UL
• TX synthesizer Data Setting (Integer)
The divide ratio can be calculated using the following equation :
fVCOTX = [ (P × N) + A] × fosc÷R (A < N)
fVCOTX
P
N
A
fosc
R
: Output frequency of external voltage controlled oscillator (VCO)
: Preset divide ratio of modulus prescaler (16 or 32)
: Preset divide ratio of binary 11 bit programmable counter (3 to 2047)
: Preset divide ratio of binary 5 bit swallow counter (0 to 31)
: Output frequency of the reference frequency oscillator
: Preset divide ratio of binary 14 bit reference counter (8 to 16383)
• Binary 14-bit Programmable Reference Counter Data Setting (RC1 to RC14)
Divide ratio
(R)
RC14 RC13 RC12 RC11 RC10
RC9
RC8
RC7
RC6
RC5
RC4
RC3
RC2
RC1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1















16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 8 is prohibited.
• Binary 11-bit Programmable Counter Data Setting (NC1 to NC11)
Divide ratio (N)
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0












2047
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 5-bit Swallow Counter Data Setting (AC1 to AC5)
Divide ratio (A)
AC5
AC4
AC3
AC2
AC1
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
1
0






31
1
1
1
1
1
Note : A < N, AC6 to AC7 = 0
• Prescaler Data Setting (SWC)
SWC
Prescaler divide ratio
1
16/17
0
32/33
11
MB15F88UL
• Phase Comparator Phase Switching Data Setting
FCC = “1”
FCC = “0”
DO
DO
fr > fp
H
L
fr < fp
L
H
fr = fp
Z
Z
VCO polarity
1
2
Notes : • Z = High-Z
• Depending upon the VCO and LPF polarity, FC bit should be set.
• Charge pump current select Data Setting (CSC)
CSC
Do current
1
±6.0 mA
0
±1.5 mA
• Common Setting
• LD/fout Output Select Data Setting
LD/fout
LDS
T1
T2
0


frTX
1
0
0
frRX
1
1
0
fpTX
1
0
1
fpRX
1
1
1
LD output
fout
output
• FC Bit Setting
When designing a synthesizer, the FC bit setting depends on the VCO and LPF characteristics
When the LPF and VCO characteristics are similar to (1) ,
FC : “H”.
When the VCO characteristics are similar to (2) ,
FC : “L”.
High
(1)
VCO Output
Frequency
(2)
LPF Output Voltage
12
Max.
MB15F88UL
2. Power Saving Mode (Intermittent Mode Control)
• PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters the power saving mode, reducing the current consumption. See
“ ELECTRICAL CHARACTERISTICS” for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is shown in“ PHASE DETECTOR OUTPUT WAVEFORM the LD Output
Logic table” .
Setting the PS pin high releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth start-up when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes : • When power (VCC) is first applied, the device must be in standby mode and PS = Low, for at least 1 µs.
• PS pin must be set “L” for Power ON.
OFF
VCC
ON
tV ≥ 1 µs
Clock
Data
LE
tPS ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs after power supply remains stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PS : L → H) 100 ns after setting serial data.
13
MB15F88UL
3. Serial Data Input Timing
1st data
2nd data
Control bit
Data
MSB
Invalid data
LSB
Clock
LE
t1
t4
t3
t2
t5
t6
t7
Parameter
On the rising edge of the clock, one bit of data is tranferred into shift register.
Min
Typ
Max
Unit
Parameter
Min
Typ Max
t1
20


ns
t5
100


ns
t2
20


ns
t6
20


ns
t3
30


ns
t7
100


ns
t4
30


ns
Note : LE should be “L” when the data is transferred into the shift register.
14
Unit
MB15F88UL
■ PHASE DETECTOR OUTPUT WAVEFORM
frTX/RX
fpTX/RX
tWU
tWL
LD
(FC bit = High)
H
DOTX/RX
Z
L
(FC bit = Low)
H
DOTX/RX
Z
L
LD Output Logic Table
TX-PLL section
RX-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
Notes : • Phase error detection range = −2 π to +2 π
• Pulses on DoTX/RX signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or
more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU ≥ 2/fosc : i.e. tWU ≥ 153.8 ns when fosc = 13 MHz
tWU ≤ 4/fosc : i.e. tWL ≤ 307.6 ns when fosc = 13 MHz
15
MB15F88UL
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
VpTX
0.1 µF
VCCTX
0.1 µF
1000 pF
1000 pF
P.G
1000 pF
S.G
50 Ω
LD/fout DOTX VpTX PSTX VCCTXGNDTX XfinTX finTX GND OSCIN
50 Ω
10
9
8
7
6
5
4
3
2
1
17
18
19
20
MB15F88UL
11
1000 pF
12
13
14
15
16
DORX VpRX PSRX VCCRXGNDRXXfinRX finRX
LE
Data Clock
S.G
50 Ω
1000 pF
VpRX
VCCRX
0.1 µF
Note : TSSOP-20
16
0.1 µF
Controller (divide
ratio setting)
MB15F88UL
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RX-PLL input sensitivity vs Input frequency
Ta = + 25 °C
10.0
0.0
SPEC
PfinRX (dBm)
−10.0
−20.0
−30.0
−40.0
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−50.0
−60.0
0
400
800
1200
1600
2000
2400
2800
3200
3600
4000
finRX (MHz)
TX-PLL input sensitivity vs Input frequency
Ta = + 25 °C
10.0
0.0
PfinTX (dBm)
SPEC
−10.0
−20.0
−30.0
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−40.0
−50.0
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
finTX (MHz)
17
MB15F88UL
2. OSCIN input sensitivity
Input sensitivity vs Input frequency
Ta = + 25 °C
10
SPEC
0
POSC (dBm)
−10
−20
−30
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
SPEC
−40
−50
−60
0
20
40
60
80 100 120 140 160 180 200 220 240 260 280 300 320
fOSC (MHz)
18
MB15F88UL
3. RX-PLL Do output current
• 1.5 mA mode
Charge pump output current IDO (mA)
IDO − VDO
Ta = +25 ˚C
VCC = Vp = 3.0 V
10.0
0
−10.0Charge pump output voltage VDO (V)
3.0
0.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
Charge pump output current IDO (mA)
IDO − VDO
Ta = +25˚C
VCC = Vp = 3.0 V
10.0
0
−10.0
Charge pump output voltage VDO (V)
0.0
3.0
Charge pump output voltage VDO (V)
19
MB15F88UL
4. TX-PLL Do output current
• 1.5 mA mode
Charge pump output current IDO (mA)
IDO − VDO
10.0
Ta : + 25 °C
VCC = Vp = 3.0 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
Charge pump output current IDO (mA)
IDO − VDO
10.0
Ta : + 25 °C
VCC = Vp = 3.0 V
0
−10.0
0.0
1.0
2.0
3.0
Charge pump output voltage VDO (V)
20
MB15F88UL
5. fin input impedance
finRX input impedance
4 : 17.994 Ω
−52.029 Ω
1.1765 pF
2 600.000 000 MHz
1 : 45.859 Ω
−188.77 Ω
1 GHz
2 : 25.48 Ω
−103.67 Ω
1.7 GHz
3 : 22.152 Ω
−83.391 Ω
2 GHz
1
4
3
START 1 000.000 000 MHz
2
STOP 2 600.000 000 MHz
finTX input impedance
4 : 29.164 Ω
−143.77 Ω
922.54 fF
1 200.000 000 MHz
1 : 926.38 Ω
−970.56 Ω
100 MHz
2 : 120.58 Ω
−429.81 Ω
400 MHz
3 : 45.984 Ω
−220.31 Ω
800 MHz
1
2
4
START 100.000 000 MHz
3
STOP 1 200.000 000 MHz
21
MB15F88UL
6. OSCIN input impedance
OSCIN input impedance
4 : 081.06 Ω
−1.0784 kΩ
1.4758 pF
100.000 000 MHz
1 : 15.032 kΩ
−10.537 kΩ
3 MHz
2 : 1.2688 kΩ
−5.2405 kΩ
20 MHz
4
3 : 352.88 Ω
−2.6899 kΩ
40 MHz
1
32
START 3.000 000 MHz
22
STOP 100.000 000 MHz
MB15F88UL
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
Test Circuit
S.G.
OSC IN
LPF
DO
fin
fVCO = 2490 MHz
KV = 52 MHz/V
fr = 1 MHz
fOSC = 13 MHz
LPF
VCC = Vp = 3.0 V
VVCO = 2.5 V
Ta = +25 °C
CP : 1.5 mA mode
Q=5
24 kΩ
Spec Trum
Analyzer
VCO
82 pF
15 kΩ
22 pF
820 pF
• PLL Reference Leakage
ATTEN 10 dB
RL 0 dBm
VAVG 30
10 dB/
∆MKR −67.17 dB
200 kHz
∆MKR
D 200 kHz
S −67.17 dB
CENTER 2.490008 GHz
∗ RBW 3.0 kHz
VBW 3.0 kHz
SPAN 1.000 MHz
SWP 280 ms
• PLL Phase Noise
ATTEN 10 dB
RL 0 dBm
VAVG 19
10 dB/
∆MKR −60.16 dB
1.00 kHz
∆MKR
D 1.00 kHz
S −60.16 dB
CENTER 2.49000668 GHz
RBW 100 Hz
VBW 100 Hz
SPAN 10.00 kHz
SWP 802 ms
(Continued)
23
MB15F88UL
(Continued)
• PLL Lock Up time
• PLL Lock Up time
2490 MHz → 2550 MHz within ± 1 kHz
Lch → Hch
144 µs
2550 MHz → 2490 MHz within ± 1 kHz
Hch → Lch
133 µs
2.550012000 GHz
2.490011750 GHz
2.550008000 GHz
2.490007750 GHz
2.550004000 GHz
2.490003750 GHz
−1.933 ms
24
567 µs
500.0 µs/div
3.067 ms
−1.933 ms
567 µs
500.0 µs/div
3.067 ms
MB15F88UL
■ APPLICATION EXAMPLE
VCO
OUTPUT
from controller
LPF
3.0 V
1000 pF
3.0 V
0.1 µF
0.1 µF
1000 pF
Clock
DATA
LE
finRX
XfinRX
GNDRX
VCCRX
PSRX
VpRX
DORX
20
19
18
17
16
15
14
13
12
11
MB15F88UL
1
2
3
4
5
6
7
8
9
10
OSCIN
GND
finTX
XfinTX
GNDTX
VCCTX
PSTX
VpTX
DOTX
LD/fout
1000 pF
1000 pF
3.0 V
1000 pF
0.1 µF
3.0 V
Lock Det.
0.1 µF
TCXO
OUTPUT
VCO
LPF
Notes : • Clock, Data, LE : Schmit trigger circuit is provided (insert a pull-down or pull-up resistor to prevent
oscillation when open-circuited in the input) .
• TSSOP-20
25
MB15F88UL
■ USAGE PRECAUTIONS
(1) VCCRX, VpRX, VCCTX and VpTX must be equal voltage.
Even if either RX-PLL or TX-PLL is not used, power must be supplied to VCCRX, VpRX, VCCTX and VpTX to
keep them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions :
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
■ ORDERING INFORMATION
Part number
26
Package
MB15F88ULPFT
20-pin plastic TSSOP
(FPT-20P-M06)
MB15F88ULPVA
20-pad plastic BCC
(LCC-20P-M05)
Remarks
MB15F88UL
■ PACKAGE DIMENSIONS
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) .
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
20-pin plastic TSSOP
(FPT-20P-M06)
*1 6.50±0.10(.256±.004)
0.17±0.05
(.007±.002)
11
20
*2 4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(Mounting height)
(.041±.002)
LEAD No.
1
10
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.13(.005)
M
0~8˚
+0.03
(0.50(.020))
0.10(.004)
C
0.60±0.15
(.024±.006)
+.001
0.07 –0.07 .003 –.003
(Stand off)
0.25(.010)
2003 FUJITSU LIMITED F20026S-c-3-3
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
27
MB15F88UL
(Continued)
20-pad plastic BCC
(LCC-20P-M05)
3.00(.118)TYP
3.60±0.10(.142±.004)
16
0.55±0.05
(.022±.002)
(Mounting height)
11
11
0.25±0.10
(.010±.004)
16
0.50(.020)
TYP
0.25±0.10
(.010±.004)
INDEX AREA
3.40±0.10
(.134±.004)
2.70(.106)
TYP
"D"
"A"
1
6
"C"
6
Details of "A" part
0.50±0.10
(.020±.004)
1
0.50(.020)
TYP
2.80(.110)REF
0.075±0.025
(.003±.001)
(Stand off)
0.05(.002)
"B"
Details of "B" part
0.50±0.10
(.020±.004)
Details of "C" part
0.50±0.10
(.020±.004)
Details of "D" part
0.30±0.10
(.012±.004)
C0.20(.008)
0.60±0.10
(.024±.004)
C
0.30±0.10
(.012±.004)
0.60±0.10
(.024±.004)
0.40±0.10
(.016±.004)
2001 FUJITSU LIMITED C20056S-c-2-1
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
28
MB15F88UL
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0306
 FUJITSU LIMITED Printed in Japan