FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21356-3E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F02SL
■ DESCRIPTION
The Fujitsu MB15F02SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1200 MHz and a
500 MHz prescalers. The 1200 MHz and 500 MHz prescalers have a dual modulus division ratio of 128/129 or
64/65, and a 8/9 or a 16/17 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15F02SL uses the latest BiCMOS process. As a result,
the supply current is typically 3 mA at 2.7 V. A refined charge pump supplies a well-balanced output current of 1.5
mA or 6 mA. The charge pump current is selectable by serial data.
MB15F02SL is ideally suited for wireless mobile communications, such as GSM and PDC.
■ FEATURES
• High frequency operation: RF synthesizer: 1200 MHz max
IF synthesizer: 500 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 3.0 mA typ. (VCC = 2.7 V, Ta = +25°C, in IF, RF locking state)
ICC = 3.5 mA typ. (VCC = 3.0 V, Ta = +25°C, in IF, RF locking state)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = 3.0 V, Ta = +25°C), Max. 10 µA (VCC = 3.0 V)
• Dual modulus prescaler: 1200 MHz prescaler (64/65, 128/129)/500 MHz prescaler (8/9 or 16/17)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
• Pin compatible with MB15F02, MB15F02L
■ PACKAGES
16-pin plastic SSOP
(FPT-16P-M05)
16-pad plastic BCC
(LCC-16P-M04)
MB15F02SL
■ PIN ASSIGNMENTS
16-pin SSOP
GNDRF Clock
GNDRF
1
16
Clock
OSCIN
2
15
Data
OSCIN
1
GNDIF
3
14
LE
GNDIF
2
finIF
4
13
finRF
finIF
3
VCCIF
5
12
VCCRF
VCCIF
4
LD/fout
6
11
XfinRF
LD/fout
5
PSIF
7
10
PSRF
PSIF
6
DOIF
8
9
DORF
TOP
VIEW
(FPT-16P-M05)
2
16-pad BCC
16
15
TOP
VIEW
7
8
14
Data
13
LE
12
finRF
11
VCCRF
10
XfinRF
9
PSRF
DOIF DORF
(LCC-16P-M04)
MB15F02SL
■ PIN DESCRIPTIONS
Pin no.
SSOP-16 BCC-16
Pin
name
I/O
Descriptions
1
16
GNDRF
–
Ground for RF-PLL section.
2
1
OSCIN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
3
2
GNDIF
–
Ground for the IF-PLL section.
4
3
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
5
4
VCCIF
–
Power supply voltage input pin for the IF-PLL section.
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
6
5
LD/fout
7
6
PSIF
I
Power saving mode control for the IF-PLL section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PSIF = “H” ; Normal mode
PSIF = “L” ; Power saving mode
8
7
DoIF
O
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
9
8
DoRF
O
Charge pump output for the RF-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
10
9
PSRF
I
Power saving mode control for the RF-PLL section. This pin must be set
at “L” during Power-ON. (Open is prohibited.)
PSRF = “H” ; Normal mode
PSRF = “L” ; Power saving mode
11
10
XfinRF
I
Prescaler complementary input for the RF-PLL section.
This pin should be grounded via a capacitor.
12
11
VCCRF
–
Power supply voltage input pin for the RF-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RF-PLL
is lost.
13
12
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
14
13
LE
I
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
15
14
Data
I
Serial data input (with a schmitt trigger input buffer.)
Data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit in
the serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
3
MB15F02SL
■ BLOCK DIAGRAM
VCCIF GNDIF
5 (4) 3 (2)
PSIF 7
(6)
finIF 4
(3)
Intermittent
mode control
(IF-PLL)
3-bit latch
7-bit latch
11-bit latch
LDS SWIF FCIF
Binary 7-bit
swallow counter
(IF-PLL)
Binary 11-bit
programmable
counter (IF-PLL)
fpIF
Charge
pump Current
(IF-PLL) Switch
Phase
comp.
(IF-PLL)
8 DoIF
(7)
Lock
Det.
(IF-PLL)
Prescaler
(IF-PLL)
8/9, 16/17
2-bit latch
T1
T2
14-bit latch
1-bit latch
Binary 14-bit
programmable ref.
counter (IF-PLL)
C/P setting
current CP
LDIF
frIF
OSCIN 2
(1)
AND
frRF
T1
OR
T2
2-bit latch
(12)
finRF 13
XfinRF 11
(10)
PSRF 10
(9)
LE 14
(13)
(14)
Data 15
Clock 16
(15)
Binary 14-bit
programmable ref.
counter (RF-PLL)
C/P setting
current CP
14-bit latch
1-bit latch
Intermittent
mode control
(RF-PLL)
Schmitt
circuit
Schmitt
circuit
LDS SWRF FCRF
Binary 7-bit
swallow counter
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
3-bit latch
7-bit latch
11-bit latch
Phase
comp.
(RF-PLL)
fpRF
Latch selector
C C
N N
1 2
23-bit shift register
12 (11) 1 (16)
VCCRF GNDRF
O : SSOP
( ) : BCC
4
6 LD/
(5) fout
Lock
Det.
(RF-PLL)
Prescaler
(RF-PLL)
64/65, 128/129
Schmitt
circuit
Selector
LD
frIF
frRF
fpIF
fpRF
Charge Current
pump switch
(RF-PLL)
9 DoRF
(8)
MB15F02SL
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min.
Max.
VCC
–0.5
+4.0
V
Input voltage
VI
–0.5
VCC +0.5
V
Output voltage
VO
GND
VCC
V
Tstg
–55
+125
°C
Power supply voltage
Storage temperature
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
VCC
2.4
3.0
3.6
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F02SL
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
“H” level input voltage
“L” level input voltage
Min.
Typ.
Max.
–
1.2
(1.5)
–
mA
ICCRF*1
finRF = 1200 MHz, VCCRF = 2.7 V
(VCCRF = 3.0 V)
–
1.8
(2.0)
–
mA
IPSIF
PSIF = PSRF = “L”
–
0.1*2
10
µA
IPSRF
PSIF = PSRF = “L”
–
0.1*2
10
µA
finIF*3
finIF
IF PLL
50
–
500
MHz
finRF*3
finRF
RF PLL
100
–
1200
MHz
OSCIN
fosc
3
–
40
MHz
–
IF*8
fin
PfinIF
IF PLL, 50 Ω system
–15
–
+2
dBm
finRF
PfinRF
RF PLL, 50 Ω system
–15
–
+2
dBm
OSCIN
VOSC
VCC
Vp-p
Data,
Clock,
LE
VIH
Schmitt trigger input
VCC ×0.7
+ 0.4
–
–
VIL
Schmitt trigger input
–
–
VCC × 0.3
– 0.4
–
0.5
VIH
–
VCC × 0.7
–
–
VIL
–
–
–
VCC × 0.3
Data,
Clock,
LE,
“L” level input current PSIF, PSRF
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
“H” level input current
IIH
–
0
–
+100
IIL*4
–
–100
–
0
“H” level input voltage
“L” level input voltage
PSIF,PSRF
“H” level input current
“L” level input current
“H” level output
voltage
“L” level output
voltage
“H” level output
voltage
“L” level output
voltage
High impedance
cutoff current
“H” level output
current
“L” level output
current
Unit
finIF = 500 MHz, VCCIF = 2.7 V
(VCCIF = 3.0 V)
Power saving current
Input sensitivity
Value
ICCIF*1
Power supply current*1
Operating frequency
Condition
OSCIN
DoIF
DoRF
V
µA
VOH
VCC = 3.0 V, IOH = –1 mA
VCC – 0.4
–
–
VOL
VCC = 3.0 V, IOL = 1 mA
–
–
0.4
VDOH
VCC = 3.0 V, IDOH = –0.5 mA
VCC – 0.4
–
–
µA
V
LD/fout
DoIF
DoRF
V
V
VDOL
VCC = 3.0 V, IDOL = 0.5 mA
–
–
0.4
IOFF
VCC = 3.0 V,
VOFF = 0.5 V to VCC – 0.5 V
–
–
2.5
IOH*4
VCC = 3.0 V
–
–
–1.0
nA
mA
LD/fout
I
OL*4
VCC = 3.0 V
1.0
–
–
(Continued)
6
MB15F02SL
(Continued)
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
Symbol
DoIF
DoRF
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
Typ.
Max.
–
–6.0
–
–
–1.5
–
CS bit = “H”
–
6.0
–
CS bit = “L”
–
1.5
–
Unit
mA
IDOL
VCC = 3.0 V,
VDOL= VCC/2,
Ta = +25°C
IDOL/IDOH
IDOMT*5
VDO = VCC/2
–
3
–
%
vs VDO
IDOVD
0.5 V ≤ VDO ≤ VCC – 0.5 V
–
10
–
%
vs Ta
IDOTA*7
–40°C ≤ Ta ≤ +85°C,
VDO = VCC/2
–
10
–
%
“L” level output current
Charge pump
current rate
Min.
VCC = 3.0 V,
CS bit = “H”
VDOH = VCC/2,
CS bit = “L”
Ta = +25°C
IDOH*4
“H” level output current
Value
Condition
*6
Conditions; fosc = 12 MHz, Ta = +25°C, in locking state.
VCCIF = VCCRF = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode.
AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
The symbol “–” (minus) means direction of current flow.
VCC = 3.0 V, Ta = +25°C (|I3| – |I4|)/[(|I3| + |I4|)/2] × 100(%)
VCC = 3.0 V, Ta = +25°C [(|I2| – |I1|)/2]/[(|I1| + |I2|)/2] × 100(%) (Applied to each IDOL, IDOH)
VCC = 3.0 V, [|IDO(+85°C) – IDO(–40°C)|/2]/[|IDO(+85°C) + IDO(–40°C)|/2] × 100(%) (Applied to each IDOL, IDOH)
Prescaler divided ratio
Charge pump current
finIF
VfinIF(min)
16/17
1.5 mA mode
50 MHz
fin
500 MHz
–15 dBm
6.0 mA mode
50 MHz
fin
300 MHz
–15 dBm
300 MHz < fin
500 MHz
–10 dBm
8/9
1.5 mA mode
50 MHz fin
300 MHz*
–15 dBm
300 MHz < fin
500 MHz
–15 dBm
6.0 mA mode
50 MHz
fin
300 MHz*
–15 dBm
300 MHz < fin
500 MHz
–10 dBm
* : VCC = 2.7 V to 3.6 V at 500 MHz,
VCC = 2.4 V to 3.6 V, Ta = –40°C to +85°C at fin < 500 MHz
I1
I3
I2
IDOL
IDOH
I4
I2
I1
0.5
Vcc/2
Vcc − 0.5
Vcc
Charge Pump Output Voltage (V)
7
MB15F02SL
■ FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation:
fVCO = {(M × N) + A} × fOSC ÷ R (A < N)
fVCO :
Output frequency of external voltage controlled oscillator (VCO)
M :
Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N :
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A :
Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC :
Reference oscillation frequency
R :
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table 1. Control Bit
Control bit
Destination of serial data
CN1
CN2
L
L
The programmable reference counter for the IF-PLL
H
L
The programmable reference counter for the RF-PLL
L
H
The programmable counter and the swallow counter for the IF-PLL
H
H
The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
CN1,2
R1 to R14
T1, 2
CS
X
R
8
R
9
R R R R R
10 11 12 13 14
C
S
X
X
X
: Control bit
[Table 1]
: Divide ratio setting bits for the programmable reference counter (3 to 16,383)[Table 2]
: Test purpose bit
[Table 3]
: Charge pump currnet select bit
[Table 9]
: Dummy bits (Set “0” or “1”)
NOTE: Data input with MSB first.
8
R
7
X
MB15F02SL
Programmable Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
22
23
SWIF/ FCIF/
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
SWRF FCRF
CN1 CN2 LDS
CN1, CN2
N1 to N11
A1 to A7
SWIF/SWRF
FCIF/FCRF
LDS
: Control bit
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)
: Phase control bit for the phase detector (IF: FCIF, RF: FCRF)
: LD/fout signal select bit
[Table 1]
[Table 4]
[Table 5]
[Table 6]
[Table 7]
[Table 8]
NOTE: Data input with MSB first.
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio
(R)
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Test Purpose Bit Setting
T1
T2
LD/fout pin state
L
L
Outputs frIF.
H
L
Outputs frRF.
L
H
Outputs fpIF.
H
H
Outputs fpRF.
9
MB15F02SL
Table 4. Binary 11-bit Programmable Counter Data Setting
Divide ratio
(N)
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 5. Binary 7-bit Swallow Counter Data Setting
Divide ratio
(A)
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table 6. Prescaler Data Setting
Prescaler
divide ratio
SW = “H”
SW = “L”
IF-PLL
8/9
16/17
RF-PLL
64/65
128/129
Table 7. Phase Comparator Phase Switching Data Setting
FCIF, FCRF = “H”
FCIF, FCRF = “L”
(1)
DoIF, DoRF
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
(1)
(2)
VCO Output
Frequency
(2)
LPF Output Voltage
Note: • Z = High-impedance
• Depending upon the VCO and LPF polarity, FC bit should be set.
Table 8. LD/fout Output Select Data Setting
LDS
10
LD/fout output signal
H
fout (frIF/frRF, fpIF/fpRF) signals
L
LD signal
MB15F02SL
Table 9. Charge Pump Current Setting
CS
Current value
H
±6.0 mA
L
±1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: • When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
• PS pin must be set at “L” for Power-ON.
ON
OFF
tv ≥ 1 µs
VCC
,,,
,,,,
,,,,
,,,
Clock
Data
LE
tps ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = “L” (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data.
11
MB15F02SL
■ SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit
Data
MSB
Invalid data
LSB
Clock
t1
t2
t3
t6
t7
LE
t4
t5
On rising edge of the clock, one bit of the data is transfered into the shift register.
Parameter
Min.
Typ.
Max.
Unit
Parameter
Min.
Typ.
Max.
Unit
t1
20
–
–
ns
t5
100
–
–
ns
t2
20
–
–
ns
t6
20
–
–
ns
t3
30
–
–
ns
t7
100
–
–
ns
t4
30
–
–
ns
Note: LE should be “L” when the data is transferred into the shift register.
12
MB15F02SL
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr IF /fr RF
fp IF /fp RF
t WU
t WL
LD
(FC bit = High)
D OIF / D ORF
(FC bit = Low)
D OIF / D ORF
LD Output Logic Table
IF-PLL section
RF-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
Notes: • Phase error detection range = –2π to +2π
•
•
•
•
Pulses on DoIF/RF signals are output to prevent dead zone.
LD output becomes low when phase error is tWU or more.
LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc: i. e. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc: i. e. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F02SL
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
VCCIF
0.1 µF
S.G.
1000 pF
1000 pF
50 Ω
50 Ω
DOIF
PSIF
LD/fout
VCCIF
finIF
GNDIF
OSCIN
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
DORF
PSRF
XfinRF
VCCRF
finRF
LE
Data
Clock
S.G.
GNDRF
1000 pF
Controller (divide ratio setting)
50 Ω
VCCRF
1000 pF
0.1 µF
Note: SSOP-16
14
S.G.
MB15F02SL
■ TYPICAL CHARACTERISTICS
1. fin input impedance
RF-PLL input sensitivity − Input frequency
10
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
5
Input sensitivity PfinRF (dBm)
Ta = +25 °C
0
−5
SPEC
−10
−15
−20
−25
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
−30
−35
VCC = 3.6 V
−40
0
500
1000
1500
2000
Input frequency finRF (MHz)
IF-PLL input sensitivity − Input frequency
Ta = +25 °C
10
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,,,
Input sensitivity PfinIF (dBm)
5
0
−5
SPEC
−10
−15
−20
VCC = 2.7 V
VCC = 3.0 V
−25
VCC = 3.6 V
−30
0
100
200
300
400
500
600
700
800
900
1000
Input frequency finIF (MHz)
15
MB15F02SL
2. OSCIN input sensitivity
,,,,
,,,,
Input sensitivity − Input frequency
Ta = +25 °C
10
Input sensitivity VOSC (dBm)
SPEC
0
−10
−20
−30
VCC = 2.4 V
VCC = 2.7 V
−40
VCC = 3.0 V
VCC = 3.6 V
−50
0
20
40
60
80
100
120
140
Input frequency fOSC (MHz)
16
160
180
200
220
240
MB15F02SL
3. Do output current (RF-PLL)
• 1.5 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
Change pump output current IDO (mA)
10.00
2.000
/div
IDOL
0
IDOH
−10.00
0
.6000/div
Change pump output voltage VDO (V)
• 6.0 mA mode
4.800
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
Change pump output current IDO (mA)
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
.6000/div
Change pump output voltage VDO (V)
4.800
17
MB15F02SL
4. Do output current (IF-PLL)
• 1.5 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
Change pump output current IDO (mA)
10.00
2.000
/div
IDOL
0
IDOH
−10.00
0
.6000/div
Change pump output voltage VDO (V)
4.800
• 6.0 mA mode
VDO − IDO
Ta = +25 °C
VCC = 3.0 V
Change pump output current IDO (mA)
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
18
.6000/div
Change pump output voltage VDO (V)
4.800
MB15F02SL
5. fin input impedance
finRF input impedance
1 : 351.03 Ω
−699.34 Ω
100 MHz
2:
33.18 Ω
−208.83 Ω
400 MHz
3 : 12.895 Ω
−94.023 Ω
800 MHz
1
4 : 10.543 Ω
−48.268 Ω
1200 MHz
2
4
3
START
100.000 000 MHz
STOP 1 200.000 000 MHz
finIF input impedance
1 : 859.06 Ω
−1.0314 kΩ
50 MHz
2 : 92.656 Ω
−413.59 Ω
200 MHz
3 : 28.531 Ω
−204.21 Ω
400 MHz
1
2
4 : 20.859 Ω
−159.23 Ω
500 MHz
4
3
START
50.000 000 MHz
STOP
500.000 000 MHz
19
MB15F02SL
6. OSCIN input impedance
OSCIN input impedance
1 : 9.0005 kΩ
−3.281 kΩ
3 MHz
2 : 3.9238 kΩ
−4.8648 kΩ
10 MHz
3 : 1.4543 kΩ
−3.45 kΩ
4
20 MHz
3
12 4 : 395.5 Ω
−1.8983 kΩ
40 MHz
START
20
3.000 000 MHz
STOP
40.000 000 MHz
MB15F02SL
■ APPLICATION EXAMPLE
VCO
OUTPUT
LPF
3V
0.1 µF
1000 pF
1000 pF
from controller
Clock
Data
LE
finRF
VCCRF
XfinRF
PSRF
DoRF
16
15
14
13
12
11
10
9
8
MB15F02SL
1
2
3
4
5
6
7
GNDRF
OSCIN
GNDIF
finIF
VCCIF
LD/fout
PSIF
DoIF
3V
1000 pF
LockDet
1000 pF
0.1 µF
TCXO
OUTPUT
VCO
LPF
Note: SSOP-16
■ USAGE PRECAUTIONS
(1) VCCRF must equal VccIF.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF and VCCIF to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
21
MB15F02SL
■ ORDERING INFORMATION
Part number
22
Package
MB15F02SLPFV1
16-pin, plastic SSOP
(FPT-16P-M05)
MB15F02SLPV1
16-pad, plastic BCC
(LCC-16P-M04)
Remarks
MB15F02SL
■ PACKAGE DIMENSIONS
16-pin, Plastic SSOP
(FPT-16P-M05)
Note 1 ) * : These dimensions do not include resin protrusion.
Note 2 ) Pins width and pins thickness include plating thickness.
* 5.00±0.10(.197±.004)
0.17±0.03
(.007±.001)
9
16
* 4.40±0.10
6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
+0.20
1.25 –0.10
+.008
.049 –.004
LEAD No.
1
8
0.65(.026)
0.10(.004)
C
(Mounting height)
1999 FUJITSU LIMITED F16013S-3C-5
"A"
0.24±0.08
(.009±.003)
0.13(.005)
M
0~8°
0.50±0.20
(.020±.008)
0.45/0.75
(.018/.030)
0.10±0.10
(Stand off)
(.004±.004)
0.25(.010)
Dimensions in mm (inches)
(Continued)
23
MB15F02SL
(Continued)
16-pad, Plastic BCC
(LCC-16P-M04)
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
3.40(.134)TYP
0.65(.026)
TYP
14
9
0.325±0.10
(.013±.004)
9
14
0.80(.031)
REF
INDEX AREA
4.20±0.10
(.165±.004)
3.25(.128)
TYP
"A"
0.40±0.10
(.016±.004)
1
6
0.075±0.025
(.003±.001)
(Stand off)
6
Details of "A" part
0.75±0.10
(.030±.004)
1.55(.061)
REF
"B"
1.725(.068)
REF
1
Details of "B" part
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
(.016±.004)
C
24
1999 FUJITSU LIMITED C16015S-1C-1
0.60±0.10
(.024±.004)
Dimensions in mm (inches)
MB15F02SL
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
F0001
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.