FUJITSU MB15F08SL

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21362-2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F08SL
■ DESCRIPTION
The Fujitsu MB15F08SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2500 MHz and a
1100 MHz prescalers. The 2500 MHz prescaler, and 1100 MHz prescaler have a dual modulus division ratio of 32/
33 or 64/65 and 16/17 or 32/33 enabling pulse swallow operation.
The supply voltage range is between 2.4 V and 3.6 V.
The MB15F08SL uses the latest BiCMOS process. As a result, the supply current is typically 7.0 mA at 2.7 V. A
refined charge pump supplies a well-balanced output current of 1.5 mA or 6 mA. The charge pump current is selectable
by serial data.
MB15F08SL is ideally suited for wireless mobile communications.
■ FEATURES
• High frequency operation: RX synthesizer: 2500 MHz max
TX synthesizer: 1100 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 7.0 mA typ. (VCC = 2.7 V, Ta = +25°C, in TX, RX locking state)
ICC = 7.5 mA typ. (VCC = 3.0 V, Ta = +25°C, in TX, RX locking state)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = 3V, Ta = +25°C), Max. 10 µA (VCC = 3V)
• Dual modulus prescaler: 2500 MHz prescaler (32/33 or 64/65)/1100 MHz prescaler (16/17 or 32/33)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On–chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
■ PACKAGES
16-pin, Plastic SSOP
16-pad, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M04)
1
MB15F08SL
■ PIN ASSIGNMENTS
16-pin SSOP
GNDRX
1
16
Clock
OSCIN
2
15
Data
GNDTX
3
14
LE
finTX
4
VCCTX
5
TOP 13
VIEW
12
finRX
VCCRX
LD/fout
6
11
XfinRX
PSTX
7
10
PSRX
DOTX
8
9
DORX
(FPT-16P-M05)
2
16-pad BCC
GNDRX Clock
OSCIN
1
GNDTX
2
finTX
VCCTX
3
4
LD/fout
PSTX
5
6
16 15
TOP
VIEW
7
8
14
Data
13
12
LE
11
10
9
finRX
VCCRX
XfinRX
PSRX
DOTX DORX
(LCC-16P-M04)
MB15F08SL
■ PIN DESCRIPTION
Pin no.
SSOP
BCC
Pin
name
1
16
GNDRX
–
Ground for RX-PLL section.
2
1
OSCIN
I
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
3
2
GNDTX
–
Ground for the TX-PLL section.
4
3
finTX
I
Prescaler input pin for the TX-PLL.
Connection to an external VCO should be via AC coupling.
5
4
VCCTX
–
Power supply voltage input pin for the TX-PLL section.
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).
The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal
LDS bit = “L” ; outputs LD signal
6
5
LD/fout
I/O
Descriptions
7
6
PSTX
I
Power saving mode control for the TX-PLL section. This pin must be set at
“L” during Power-ON. (Open is prohibited.)
PSTX = “H” ; Normal mode
PSTX = “L” ; Power saving mode
8
7
DoTX
O
Charge pump output for the TX-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
9
8
DoRX
O
Charge pump output for the RX-PLL section.
Phase characteristics of the phase detector can be selected via
programming of the FC-bit.
10
9
PSRX
I
Power saving mode control for the RX-PLL section. This pin must be set at
“L” during Power-ON. (Open is prohibited.)
PSRX = “H” ; Normal mode
PSRX = “L” ; Power saving mode
11
10
XfinRX
I
Prescaler complementary input for the RX-PLL section.
This pin should be grounded via a capacitor.
12
11
VCCRX
–
Power supply voltage input pin for the RX-PLL section, the shift register
and the oscillator input buffer. When power is OFF, latched data of RX-PLL
is lost.
13
12
finRX
I
Prescaler input pin for the RX-PLL.
Connection to an external VCO should be via AC coupling.
14
13
LE
I
Load enable signal inpunt (with a schmitt trigger input buffer.)
When the LE bit is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in the serial data.
15
14
Data
I
Serial data input (with a schmitt trigger input buffer.)
A data is transferred to the corresponding latch (TX-ref counter, TX-prog.
counter, RX-ref. counter, RX-prog. counter) according to the control bit in
the serial data.
16
15
Clock
I
Clock input for the 23-bit shift register (with a schmitt trigger input buffer.)
One bit of data is shifted into the shift register on a rising edge of the clock.
3
MB15F08SL
■ BLOCK DIAGRAM
VCCTX GNDTX
(4) 5
3 (2)
PSTX 7
(6)
finTX 4
(3)
Intermittent
mode control
(TX-PLL)
3-bit latch
7-bit latch
11-bit latch
LDS SWTX FCTX
Binary 7-bit
swallow counter
(TX-PLL)
Binary 11-bit
programmable
counter (TX-PLL)
fpTX
Charge Current
pump. Switch
(TX-PLL)
Phase
comp.
(TX-PLL)
8 DoTX
(7)
Lock
Det.
(TX-PLL)
Prescaler
(TX-PLL)
16/17, 32/33
2-bit latch
T1
T2
14-bit latch
1-bit latch
Binary 14-bit
programmable ref.
counter (TX-PLL)
C/P setting
current
LDTX
frTX
OSCIN 2
(1)
AND
frRX
T1
OR
T2
2-bit latch
(12)
finRX 13
XfinRX 11
(10)
PSRX 10
(9)
LE 14
(13)
(14)
Data 15
Clock 16
(15)
O -- SSOP
( ) -- BCC
4
Binary 14-bit
programmable ref.
counter (RX-PLL)
C/P setting
current
14-bit latch
1-bit latch
Intermittent
mode control
(RX-PLL)
Schmitt
circuit
Schmitt
circuit
6 LD/
(5) fout
Lock
Det.
(RX-PLL)
Prescaler
(RX-PLL)
32/33, 64/65
Schmitt
circuit
Selector
LD
frTX
frRX
fpTX
fpRX
LDS SWRX FCRX
Binary 7-bit
swallow counter
(RX-PLL)
Binary 11-bit
programmable
counter (RX-PLL)
3-bit latch
7-bit latch
11-bit latch
Phase
comp.
(RX-PLL)
fpRX
Latch selector
C C
N N
1 2
23-bit shift register
(11)12
1 (16)
VCCRX GNDRX
Charge Current
pump. Switch
(RX-PLL)
9 DoRX
(8)
MB15F08SL
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min.
Max.
VCC
–0.5
+4.0
V
Input voltage
VI
–0.5
VCC +0.5
V
Output voltage
VO
GND
VCC
V
Storage temperature
Tstg
–55
+125
°C
Power supply voltage
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
VCC
2.4
3.0
3.6
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F08SL
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
Power supply current*
Symbol
Condition
ICCTX*1
finTX =
1100 MHz
ICCRX*1
finRX =
2500 MHz
1
Power saving current
IPS
finTX
Input sensitivity
“H” level input voltage
“L” level input voltage
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
“H” level input current
“L” level input current
“H” level output voltage
“L” level output voltage
“H” level output voltage
PSTX = PSRX = “L”
(2.8)
4.4
(4.7)
Unit
–
mA
–
mA
–
0.1*2
10
µA
–
1100
MHz
finRX
finRX
RX PLL
400
–
2500
MHz
OSCIN
fosc
3
–
40
MHz
finTX
PfinTX
TX PLL, 50 Ω system
–10
–
+2
dBm
finRX
PfinRX RX PLL, 50 Ω system
–15
–
+2
dBm
OSCIN
VOSC
0.5
–
VCC
Vp-p
Data,
Clock,
LE,
VIH
VCC ×
0.7 + 0.4
–
–
–
–
VCC × 0.3
– 0.4
*8
PS
Data,
Clock,
LE, PS
OSCIN
LD/fout
High impedance
cutoff current
DoTX
DoRX
“H” level output current
(VCCRX = 3.0 V)
–
2.6
Max.
100
“L” level output voltage
“L” level output current
VCCRX = 2.7 V
–
Typ.
TX PLL
*3
DoTX
DoRX
“H” level output current
(VCCTX = 3.0 V)
Min.
finTX
*3
Operating frequency
VCCTX = 2.7 V
Value
LD/fout
DoTX
DoRX
VIL
–
–
Schmitt trigger input
Schmitt trigger input
VIH
–
VCC × 0.7
–
–
VIL
–
–
–
VCC × 0.3
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
IIH
–
0
–
+100
IIL
–
–100
–
0
*4
VOH
VCC = 3 V, IOH = –1 mA
VCC – 0.4
–
–
VOL
VCC = 3 V, IOL = 1 mA
–
–
0.4
VDOH
VCC = 3 V, IDOH = –0.5 mA
VCC – 0.4
–
–
VDOL
VCC = 3 V, IDOL = 0.5 mA
–
–
0.4
IOFF
VCC = 3 V,
VOFF = 0.5 V to VCC –0.5V
–
–
2.5
IOH*4
VCC = 3 V
–
–
–1.0
IDOL*4
VCC = 3 V
1.0
–
–
VCC = 3 V,
VDOH = VCC/2,
Ta = +25°C
CS bit = “H”
–
–6.0
–
IDOH*4
CS bit = “L”
–
–1.5
–
V
V
µA
µA
V
V
nA
mA
mA
(Continued)
6
MB15F08SL
(Continued)
(VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
Parameter
“L” level output current
Symbol
DoTX
DoRX
IDOL
Value
Condition
VCC = 3 V,
VDOL= VCC/2,
Ta = +25°C
Typ.
Max.
CS bit = “H”
–
6.0
–
CS bit = “L”
–
1.5
–
–
3
–
%
IDOL/IDOH IDOMT*5 VDO = VCC/2
Charge pump
current rate
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
Unit
Min.
mA
vs VDO
IDOVD
0.5 V ≤ VDO ≤ VCC – 0.5 V
–
10
–
%
vs Ta
IDOTA*7
–40°C ≤ Ta ≤+ 85°C,
VDO = VCC/2
–
10
–
%
*6
Conditions; fosc = 12 MHz, Ta = +25°C, SW=L, in locking state.
VCCTX = VCCRX = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving state.
AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
The symbol “–” (minus) means direction of current flow.
VCC = 3.0 V, Ta = +25°C (|I3| – |I4|)/[(|I3| + |I4|)/2] × 100(%)
VCC = 3.0 V, Ta = +25°C [(|I2| – |I1|)/2]/[(|I1| + |I2|)/2] × 100(%) (Applied to each IDOL, IDOH)
VCC = 3.0 V, [|IDO(85°C) – IDO(–40°C)|/2]/[|IDO(85°C) + IDO(–40°C)|/2] × 100(%) (Applied to each IDOL, IDOH)
fin operating frequency
Input sensitivity(Min.)
400 MHz
fin
2200 MHz –15 dBm
2200 MHz < fin
2500 MHz –10 dBm
I1
I3
I2
IDOL
IDOH
I4
I2
I1
0.5
VCC/2
VCC − 0.5 V VCC
Charge Pump Output voltage (V)
7
MB15F08SL
■ FUNCTIONAL DESCRIPTION
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
M
: Preset divide ratio of dual modulus prescaler (16or 32 for TX-PLL, 32 or 64 for RX-PLL)
N
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Reference oscillation frequency
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RX-PLL
sections, programmable reference dividers of TX/RX-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of serial data is transferred into the shift register. When the LE signal is taken high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table.1 Control Bit
Control bit
Destination of serial data
CN1
CN2
L
L
The programmable reference counter for the TX-PLL
H
L
The programmable reference counter for the RX-PLL
L
H
The programmable counter and the swallow counter for the TX-PLL
H
H
The programmable counter and the swallow counter for the RX-PLL
Shift Register Configuration
Programmable Reference Counter
LSB
MSB
Data Flow
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
N
1
C
N
2
T
1
T
2
R
1
R
2
R
3
R
4
R
5
R
6
CN1,2
R1 to R14
T1, 2
CS
X
R
8
R
9
R R R R R
10 11 12 13 14
C
S
X
X
X
X
: Control bit
[Table. 1]
: Divide ratio setting bit for the programmable reference counter (5 to 16,383)[Table. 2]
: Test purpose bit
[Table. 3]
: Charge pump currnet select bit
[Table. 9]
: Dummy bits (Set “0” or “1”)
NOTE: Data input with MSB first.
8
R
7
MB15F08SL
Programmable Counter
MSB
LSB
Data Flow
1
2
3
4
5
C
N
1
C
N
2
L
D
S
S
W
F
C
TX/
RX
TX/
RX
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
CNT1, 2 : Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
SWTX/RX : Divide ratio setting bits for the prescaler
(16/17 or 32/33 for the SWTX, 32/33 or 64/65 for the SWRX)
FCTX/RX
: Phase control bit for the phase detector (TX: FCTX, RX: FCRX)
LDS
: LD/fout signal select bit
NOTE: Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
[Table. 7]
[Table. 8]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table.3 Test Purpose Bit Setting
T
1
T
2
LD/fout pin state
L
L
Outputs frTX
H
L
Outputs frRX
L
H
Outputs fpTX
H
H
Outputs fpRX
9
MB15F08SL
Table.4 Brinary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table.5 Brinary 7-bit Swallow Counter Data Setting
Divide
ratio
(N)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table.6 Prescaler Data Setting
Prescaler
divide ratio
SW = “H”
SW = “L”
TX-PLL
16/17
32/33
RX-PLL
32/33
64/65
Table.7 Phase Comparator Phase Switching Data Setting
FCTX, RX = H
FCTX, RX = L
(1)
DoTX, RX
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO polarity
(1)
(2)
VCO Output
Frequency
(2)
Note: Z = High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
Table.8 LD/fout Output Select Data Setting
10
LDS
LD/fout output signal
H
fout (frTX, RX, fpTX, RX) signals
L
LD signal
LPF Output Voltage
MB15F08SL
Table.9 Charge Pump Current Setting
CS
Current value
H
±6.0 mA
L
±1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit)
Table.10 PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note:
When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
Note:
PS pin must be set “L” for Power-ON.
OFF
ON
tV ≥ 1 µs
V CC
Clock
Data
LE
tps ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS : L → H) 100 ns later after setting serial data.
11
MB15F08SL
■ SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit
Data
MSB
Invalid data
LSB
Clock
t1
t2
t3
t6
t7
LE
t4
t5
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
Min.
t1
20
t2
Typ.
Max.
Unit
Parameter
–
–
ns
t5
100
20
–
–
ns
t6
t3
30
–
–
ns
t7
t4
30
–
–
ns
Min.
Typ.
Max.
Unit
–
–
ns
20
–
–
ns
100
–
–
ns
Note: LE should be “L” when the data is transferred into the shift register.
12
MB15F08SL
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr TX/RX
fp TX/RX
t WU
t WL
LD
(FC bit = High)
H
D OTX/RX
Z
L
(FC bit = Low)
D OTX/RX
Z
LD Output Logic Table
TX-PLL section
RX-PLL section
LD output
Locking state/Power saving state
Locking state/Power saving state
H
Locking state/Power saving state
Unlocking state
L
Unlocking state
Locking state/Power saving state
L
Unlocking state
Unlocking state
L
Notes: • Phase error detection range = –2π to +2π
• Pulses on DoTX/RX signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 2/fosc: i. e. tWU > 156.3 ns when foscin = 12.8 MHz
tWU < 4/fosc: i. e. tWL < 312.5 ns when foscin = 12.8 MHz
13
MB15F08SL
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
fout
Oscilloscope
VCCTX
0.1µF
S·G
50 Ω
50 Ω
DOTX
PSTX
LD/fout
VCCTX
finTX
GNDTX
OSCIN
GNDRX
8
7
6
5
4
3
2
1
GND
MB15F08SL
9
10
11
12
13
14
15
16
DORX
PSRX
XfinRX
VCCRX
finRX
LE
Data
Clock
S·G
1000 pF
Controller (divide ratio setting)
50 Ω
VCCRX
1000 pF
0.1µF
Note: SSOP-16
14
S·G
1000 pF
1000 pF
MB15F08SL
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RX PLL input sensitivity − Input frequency
10
Ta = +25 °C
,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,
Input sensitivity PfinRX (dBm)
5
0
−5
SPEC
−10
−15
−20
−25
VCC = 2.4 V
−30
VCC = 2.7 V
−35
VCC = 3.0 V
VCC = 3.6 V
−40
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
Input frequency finRX (MHz)
TX PLL input sensitivity − Input frequency
10
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
Ta = +25 °C
Input sensitivity PfinTX (dBm)
5
0
SPEC
−5
−10
−15
−20
VCC = 2.4 V
−25
VCC = 2.7 V
−30
VCC = 3.0 V
−35
VCC = 3.6 V
−40
0
200
400
600
800
1000
1200
1400
1600
Input frequency finTX (MHz)
15
MB15F08SL
2. OSCIN input sensitivity
,,,,
,,,,
10
Input sensitivity − Input frequency
Ta = +25 °C
Input sensitivity VOSC (dBm)
SPEC
0
−10
−20
VCC = 2.4 V
−30
VCC = 2.7 V
−40
VCC = 3.0 V
VCC = 3.6 V
−50
0
20
40
60
80
100
120
140
Input frequency fOSC (MHz)
16
160
180
200
220
240
MB15F08SL
3. Do output current (RX PLL)
1.5 mA mode
IDO − VDO
Ta = +25 °C
VCC = 3.0 V
Charge pump output current IDO (mA)
10.00
2.000
/div
IDOL
0
IDOH
−10.00
0
.6000/div
4.800
Charge pump output voltage VDO (V)
6.0 mA mode
IDO − VDO
Ta = +25 °C
VCC = 3.0 V
Charge pump output current IDO (mA)
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
.6000/div
4.800
Charge pump output voltage VDO (V)
17
MB15F08SL
4. Do output current (TX PLL)
1.5 mA mode
IDO − VDO
Ta = +25 °C
VCC = 3.0 V
Change pump output current IDO (mA)
10.00
2.000
/div
IDOL
0
IDOH
−10.00
0
.6000/div
4.800
Charge pump output voltage VDO (V)
6.0 mA mode
IDO − VDO
Ta = +25 °C
VCC = 3.0 V
Charge pump output current IDO (mA)
10.00
IDOL
2.000
/div
0
IDOH
−10.00
0
18
.6000/div
Charge pump output voltage VDO (V)
4.800
MB15F08SL
5. fin input impedance
finTX input impedance
1 : 382.09 Ω
−720
Ω
100 MHz
2 : 32.828 Ω
−218.91 Ω
400 MHz
3 : 11.242 Ω
−97.672 Ω
800 MHz
1
4 : 9.4512 Ω
−50.598 Ω
1200 MHz
2
4
3
START 100.000 000 MHz
STOP 1 200.000 000 MHz
finRX input impedance
1 : 393.91 Ω
−714.91 Ω
100 MHz
2 : 9.5156 Ω
−69.926 Ω
1 GHz
3 : 27.894 Ω
−13.635 Ω
2 GHz
4
1
3
4 : 18.047 Ω
−1.2236 Ω
2.5 GHz
2
START 100.000 000 MHz
STOP 2 500.000 000 MHz
19
MB15F08SL
6. OSCIN input impedance
OSCIN input impedance
1 : 8.8755 kΩ
−2.52 kΩ
3 MHz
2 : 4.796 kΩ
−4.934 kΩ
10 MHz
3 : 1.7043 kΩ
−3.8729 kΩ
4
20 MHz
1
3
2
START 3.000 000 MHz
20
STOP 40.000 000 MHz
4 : 439.87 Ω
−2.1714 kΩ
40 MHz
MB15F08SL
■ REFERENCE INFORMATION
fVCO = 1733 MHz
KV = 44 MHz/V
fr = 200 kHz
fOSC = 13 MHz
LPF
Test Circuit
S.G
OSCIN
LPF
Do
fin
2200 pF
Spectrum
Analyzer
VCO
VCC = 3.0 V
VVCO = 3.5 V
Ta = +25 °C
CP : 6 mA mode
27 kΩ
1.9 kΩ
200 pF
0.022 µF
PLL Reference Leakage
ATTEN
RL
10 dB
0 dBm
10 dBm/
CENTER 1.733000 GHz
RBW 3.0 kHz
VBW 3.0 kHz
∆MKR −79.83 dB
200 kHz
SPAN 1.000 MHz
SWP 280 ms
PLL Phase Noise
ATTEN
RL
10 dB
0 dBm
10 dB/
∆MKR −48.67 dB
14.25 kHz
73.4 dBc/Hz
15.5 kHz
CENTER 1.73300000 GHz
RBW 300 Hz
VBW 300 Hz
SPAN 50.00 kHz
SWP 1.40 sec
21
MB15F08SL
(Continued)
PLL Lock Up time
1733 MHz → 1803 MHz within ± 1 KHz
Lch → Hch
467 µs
1803 MHz → 1733 MHz within ± 1 KHz
Hch → Lch
467 µs
1.90300 GHz
1.83300 GHz
1.80300 GHz
1.73300 GHz
1.70300 GHz
−678 µs
T1 400 µs
1.822 ms
4.322 ms
500.0 µs/div
T2 867 µs
∆ 467 µs
1.63300 GHz
−678 µs
T1 400 µs
1.803005000 GHz
1.733004750 GHz
1.803001000 GHz
1.733000750 GHz
1.802997000 GHz
−678 µs
T1 400 µs
22
PLL Lock Up time
1.822 ms
4.322 ms
500.0 µs/div
T2 889 µs
∆ 489 µs
1.732996750 GHz
−678 µs
T1 400 µs
1.822 ms
4.322 ms
500.0 µs/div
T2 867 µs
∆ 467 µs
1.822 ms
4.322 ms
500.0 µs/div
T2 867 µs
∆ 467 µs
MB15F08SL
■ APPLICATION EXAMPLE
OUTPUT
VCO
LPF
3V
0.1µF
1000 pF
1000 pF
From a
controller
Clock
Data
LE
finRX
VCCRX
XfinRX
PSRX
DoRX
15
14
13
12
11
10
9
8
16
MB15F08SL
1
GNDRX
2
3
OSCIN GNDTX
4
5
6
7
finTX
VCCTX
LD/fout
PSTX
DoTX
3V
1000 pF
1000 pF
LockDet
0.1µF
TCXO
OUTPUT
VCO
LPF
Note: SSOP-16
■ USAGE PRECAUTIONS
(1) VccRX must equa VccTX .
Even if either RX-PLL or TX-PLL is not used, power must be supplied to both VCCRX and VCCTX to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Tum off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
23
MB15F08SL
■ ORDERING INFORMATION
24
Part number
Package
MB15F08SLPFV1
16-pin, plastic SSOP
(FPT-16P-M05)
MB15F08SLPV1
16-pad, plastic BCC
(LCC-16P-M04)
Remarks
MB15F08SL
■ PACKAGE DIMENSIONS
16-pin, Plastic SSOP
(FPT-16P-M05)
* : These dimensions do not include resin protrusion.
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.10(.004)
INDEX
* 4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
+0.10
6.40±0.20
(.252±.008)
5.40(.213)
NOM
"A"
+0.05
0.22 –0.05
0.15 –0.02
+.004
–.002
.006 –.001
.009
Details of "A" part
+.002
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
(Continued)
25
MB15F08SL
(Continued)
16-pad, Plastic BCC
(LCC-16P-M04)
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
3.40(.134)TYP
0.65(.026)
TYP
14
9
0.325±0.10
(.013±.004)
9
14
0.80(.031)
REF
INDEX AREA
4.20±0.10
(.165±.004)
3.25(.128)
TYP
"A"
0.40±0.10
(.016±.004)
1
6
0.075±0.025
(.003±.001)
(Stand off)
6
Details of "A" part
0.75±0.10
(.030±.004)
1.55(.061)
REF
"B"
1.725(.068)
REF
1
Details of "B" part
0.60±0.10
(.024±.004)
0.05(.002)
0.40±0.10
(.016±.004)
C
26
1999 FUJITSU LIMITED C16015S-1C-1
0.60±0.10
(.024±.004)
Dimensions in mm (inches)
MB15F08SL
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
http://www.fmap.com.sg/
F9904
 FUJITSU LIMITED Printed in Japan
27