SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 description The SN28837 is a monolithic integrated circuit designed to supply timing signals for the Texas Instruments (TI) 8-mm-diagonal TC276 (PAL color) and TC277 (PAL monochrome) CCD image sensors. The SN28837 supplies both CCD-drive signals and PAL-television synchronization signals at standard video rates. It requires a single 5-V supply voltage and a 13.37-MHz crystal-oscillator input. The SN28837 provides the user with several options including multiple antiblooming modes, variable-integration time, external synchronization, clamp-pulse selection, and delayed horizontal transfer. FS PACKAGE (TOP VIEW) GND HCR VCR GT2 GT1/SH3 NC NC GT3/SH2 NC SH1 CLK PD LSW CLK13M NC PAL-Timing Operation Solid-State Reliability Color and Monochrome Operation Five Selectable-Antiblooming Modes Variable-Integration-Time Option Surface-Mount Package Clamp-Pulse Select Option Horizontal and Vertical Resets for External Synchronization BCP1 BCP2 CP1 CP2 CSYNC CBLK BF VD SCBLK IDP HGATE TESTA FI SFI NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VCC VCC1 X2 X1 GND VCC PI ABIN GT PS NC S3 S2 S1 T 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TESTB TESTC VDS E/L VGATE ABS0 ABS1 ABS2 VCC HIGH GPS GP VD2 SB NC • • • • • • • • NC – No internal connection The SN28837 is designed to drive the CCD image sensor through intermediary level-shifting devices such as the TI TMS3473B parallel driver and the SN28846 serial driver. It also supplies sample-and-hold signals for the TI TL1593 3-channel sample-and-hold circuit and multiplex signals for the TI TL1051 video preprocessor. In color applications, the SN28837 interfaces with the SN28838 color-subcarrier generator to generate the PAL color subcarrier. The SN28837 is supplied in a 60-pin plastic flat package and is characterized for operation from –20°C to 45°C. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, precautions should be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. TI is a trademark of Texas Instruments Incorporated. Copyright 1991, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 functional block diagram X1 X2 42 43 13 MHz 47 Oscillator Divide by 4 HCR 3.3 MHz 50 CLK13M 1 2 3 4 5 6 7 8 48 9 10 12 16 17 28 20 11 12 14 CLK 59 Horizontal Counter 58 Vertical Counter Decoder VCR GPS GP VDS SB 49 37 39 36 31 Clock Generator 26 27 18 29 Antiblooming Generator ABS0 ABS1 ABS2 E/L 2 38 BCP1 BCP2 CP1 CP2 CSYNC CBLK BF VD LSW SCBLK IDP TESTA TESTB TESTC VD2 VGATE HGATE FI SFI PD GT PI PS T ABIN 21 22 23 Serial Generator 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 32 33 34 51 53 56 57 S1 S2 S3 SH1 GT3/SH2 GT1/SH3 GT2 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ABIN 38 O Antiblooming in ABS0 21 I ABS1 22 I ABS2 23 I BCP1 1 O Optical black clamp BCP2 2 O Optical black clamp BF 7 O Burst flag CBLK 6 O Composite blank CLK 50 O 3.34-MHz clock (factory-test point) CLK13M 47 O 13-MHz clock (connect to SN28838 color-subcarrier generator for color operation) CP1 3 O Clamp 1 (signal processing) CP2 4 O Clamp 2 (signal processing) CSYNC 5 O Composite sync E/L 19 I Delay select for S1, S2, S3. When E/L is high, the three serial-transfer pulses occur early relative to the sample-and-hold pulses SH1, SH2, and SH3. When E/L is low, the three serial-transfer pulses occur late relative to the sample-and-hold pulses. 13 O Field index The levels on these three terminals determine which of the five antiblooming modes is selected: Mode ABS2 ABS1 ABS0 Operation 0 NC L L No ABG pulses 1 NC H L 2-MHz burst of ABG pulses 2 NC L H 1-MHz burst of ABG pulses 3 H H H 1-MHz continuous ABG pulses 4 L H H 2-MHz continuous ABG pulses Mode 1 is used for normal operation. FI GND GP 41, 60 27 Ground I Exposure control: GP gates the PS and PI outputs (see the description of GPS) GPS 26 I When GPS is high, the timer operates in the normal-integration-time mode (tint = 20 ms) and VD is connected internally to GP. To operate the imager in the variable-integration-time mode, GPS must be held low and a user-defined logic circuit must be inserted between VD and GP to vary the integration time (see Figure 1). GT 37 O TMS3473B parallel-driver MIDSEL input switch GT1/SH3 56 O GT1/SH3 is a logic signal for both Y gate 1 of the TL1051 video preprocessor and sample-and-hold channel 3 of the TL1593 3-channel sample-and-hold circuit. GT2 57 O Y gate 2 for the TL1051 video preprocessor GT3/SH2 53 O GT3/SH2 is a logic signal for both Y gate 3 of the TL1051 video preprocessor and sample-and-hold channel 2 of the TL1593 3-channel sample-and-hold circuit. HCR 59 I Horizontal-counter reset HGATE 11 O Decoded H count signal. HGATE is a test point and is not used in normal operation. HIGH 25 I Not used (tie high) IDP 10 O ID pulse (for SECAM operation) LSW 48 O Line switch (connect to SN28838 for color operation) NC 15, 30, 35, 46, 52, 54, 55 PD 49 O Power down. A low-logic level on PD causes the device to enter a low power-consumption mode. PI 39 O Parallel-image-area gate clock PS 36 O Parallel-storage-area gate clock SB 29 I Standby-mode select. When SB is high, normal operation is selected; when SB is low, the power-down mode is selected. SCBLK 9 O Subcarrier blank (for SECAM applications) No connect POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION SFI 14 O Second field index SH1 51 O Sample and hold 1 S1 32 O Serial clock 1 S2 33 O Serial clock 2 S3 34 O Serial clock 3 T 31 O Transfer-gate clock TESTA 12 O Test A (factory-test point) TESTB 16 O Test B (factory-test point) 17 O Test C (factory-test point) TESTC VCC VCC1 24, 40, 45 DC power VCR 58 I Vertical-counter reset VD 8 O Vertical drive VDS 18 I Vertical-dump speed. When VDS is high, the vertical-dump frequency is 3.3 MHz; when VDS is low, the vertical-dump frequency is 2 MHz. VD2 28 O Real-display-area signal. VD2 is a test point and is not used in normal operation. VGATE 20 O Decoded V count signal. VGATE is a test point and is not used in normal operation. X1 42 X2 43 44 Oscillator power Crystal oscillator (see Figure 2) tint GP 1 2 Flush Pulses 3 Transfer Pulse Figure 1. GP Flush and Transfer Pulses 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 variable-integration-time mode In addition to the normal TV mode of operation, the SN28837 timing generator offers an optional variable-integration mode for use with the TC276 and TC277 CCD area-array image sensors. The variable-integration mode is selected by applying a low-logic level to GPS. This low-logic level disables the vertical-drive (VD) signal from controlling, internal to the timer, the image-area and storage-area parallel transfer signal (GP). Prior to the start of a new integration period, the charge that has accumulated in the image area must be transferred out. To flush this previous signal or dark-current charge from the image area, GP is pulsed low two times. Each low pulse generates 302 pulses image-area and storage-area gate and transfer signals that shift the unwanted charge into the clearing drain. This clearing function should be performed during the high time of the VD signal (see Figure 3 through Figure 13). The new integration period continues as long as GP remains high. GPS must be held at a low-logic level to prevent VD from controlling GP internally. The integration ceases and the readout occurs when VD and GP are pulsed low simultaneously; this is accomplished by taking GPS to a high-logic level. The readout timing is dependent on the vertical-drive pulse; this means that the total-integration time is a multiple of 1/50 of a second plus the time interval between the last GP low pulse and the next VD low pulse. The image readout occurs within the normal 1/50-second readout interval. If the integration time is less than 1/50 of a second, normal output operation occurs; if the integration time is greater than 1/50 of a second, a frame buffer may be required to capture the image. Integration times greater than 1/50 of a second result in image degradation at temperatures greater than 25°C due to dark-current generation. The degradation is seen as a decrease in dynamic range (contrast) and an increase in noise. It is recommended that the image sensor be cooled for long-exposure operation. The dark-current generation is reduced by a factor of two for each 7°C temperature decrease. The sensor operates at – 30°C. Cooling can be accomplished by using a thermoelectric or Peltier cooler attached to the image sensor. Condensation on the header must be prevented by isolating the cooled sensor from moist air. Vacuum isolation is preferred; however, the continual flushing of dry nitrogen across the header can also prevent condensation. SN28837 X1 X2 42 43 C1 ≈ 40 pF C2 ≈ 40 pF NOTE: The SN28837 is designed for use with a crystal oscillator. The X1 and X2 terminals should not connect directly to external driver outputs. Figure 2. Connection of an External Crystal Oscillator to the SN28837 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Continuous total power dissipation at (or below) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 45°C Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions MIN Supply voltage, VDD NOM 4.5 High-level input voltage, VIH MAX 5 5.5 VDD x 0.7 0.8 13.375 Power-up time V MHz µs 300 Operating free-air temperature, TA V V Low-level input voltage, VIL Operating frequency UNIT – 20 45 °C electrical characteristics over recommended operating ranges of supply voltage and free-air temperature (unless otherwise noted) ‡ PARAMETER VOH VOL TEST CONDITIONS GT3/SH2 and GT1/SH3 All other outputs GT3/SH2 and GT1/SH3 All other outputs IIH§ IIL VDD = 4.5 V, VDD = 4.5 V, IOH = – 4 mA IOH = – 2 mA VDD = 4.5 V, VDD = 4.5 V, IOL = 4 mA IOL = 2 mA VIH = 5 V VIL = 0 MIN TYP MAX 3.5 V 3.5 0.5 0.5 1 – 30 UNIT V µA – 200 – 500 µA 10 30 mA IDD(AV) Average supply current IDD(S) Standby supply current ‡ The HCR, SB, and VCR inputs are Schmitt-trigger inputs with 0.1-V to 1-V hysteresis. § All inputs except X1 have pullup-current sources. 1 mA switching characteristics over recommended operating free-air temperature range, VDD = 5 V PARAMETER TEST CONDITIONS fclock tw Frequency S1, S2, S3, SH1, GT2, GT1/SH3, GT3/SH2 Pulse duration S1, S2, S3, SH1, GT2, GT1/SH3, GT3/SH2 tr Rise time tf 6 Fall time CL = 50 pF GT1/SH3 and GT3/SH2 All other outputs GT1/SH3 and GT3/SH2 MIN TYP All other outputs MHz ns 50 10 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 75 10 CL = 50 pF MAX 4.458333 ns ns SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 2H Vertical Scale 1238 1st Field 4th Field 1254 1246 1262 1270 1278 1286 1294 1302 1310 1862 1870 1255 12601265 1875 1878 1875 1886 1894 1902 1910 1918 1926 1880 1885 1890 CSYNC EQ EQ EQ 1250 VS EQ 1300 1875 1925 VS CBLK 1248 1268 1872 1892 BF 1250 1875 1265 1890 VD LSW 1250 1268 1286 1268 1286 1875 1300 1892 1910 1925 SCBLK 1892 1910 IDP 1250 1875 F1 SF1 1248 1256 1874 1890 CP1 1300 1250 1875 1925 CP2 1248 1298 1872 1924 BCP1 1248 1276 1872 1900 BCP2 1243 1245 1312 1314 1870 1937 VD2 VGATE HGATE 1314 1242 1939 1867 Always Continuous PI GT 1298 1248 1924 1872 PS, T ABIN S1,S2,S3 SH1,GT3/SH2, GT1/SH3 1250 1276 1874 1900 GT2 NOTES: A. GPS is low and VD is fed back to GP. B. When GPS is high, VGATE is always low. C. 1 field = 312 1/2 horizontal lines = 625 vertical counts. 1 frame = 625 horizontal lines = 1250 vertical counts. Period of each count of vertical counter = 32 µs. Figure 3. Vertical Timing (First and Fourth Fields) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 3rd Field 2H 2488 2nd Field 2492 2496 0 4 8 12 16 20 24 28 32 625 36 40 44 48 52 56 60 612 616 620 624 628 632 636 640 644 648 652 656 660 664 668 672 676 Vertical Scale CSYNC EQ EQ 0 CBLK 2496 EQ 50 VS EQ 675 625 VS 16 620 640 BF 0 625 15 VD LSW 0 18 36 18 36 50 625 642 660 642 660 675 SCBLK IDP 0 625 FI 15 SFI 2498 16 624 640 676 CP1 0 625 50 675 CP2 2498 48 622 674 BCP1 2498 26 622 650 BCP2 2493 2495 62 64 618 620 687 689 VD2 2492 64 617 689 VGATE HGATE Always Continuous PI GT 2498 48 622 674 PS,T AB IN S1,S2,S3 SH1, GT1/SH3, GT3/SH2 0 26 624 650 0 26 624 650 GT2 NOTES: A. GPS is low and VD is fed back to GP. B. When GPS is high, VGATE is always low. C. 1 field = 312 1/2 horizontal lines = 625 vertical counts. 1 frame = 625 horizontal lines = 1250 vertical counts. Period of each count of vertical counter = 32 µs. Figure 4. Vertical Timing (Second and Third Fields) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 Horizontal Scale† (214) 192 196 200 204 208 212 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 96 100 104 108 112 116 120 124 Continuous CLK 5 21 HSYNC 5 13 11 2 EQ CSYNC 203 5 96 120 11 2 VS 0 40 CBLK 23.5 BF 31 5 LSW 5 0 24 SCBLK 0 48 IDP 5 CP1 21 0 38 CP2 30 34 BCP1 30 BCP2 34 5 112 HGATE 24 28 PS 0 4 8 12 16 20 4 8 12 16 20 24 T S1,S2,S3 SH1,GT3/SH2, GT1/SH3 See Note A GT2 † For the horizontal scale (T1 clock), one interval = 299 ns ≥ 4 master-clock periods. NOTES: A. Although S1, S2, and S3 appear to be coincident, S1 leads S2 by t5 ns, and S2 leads S3 by 75 ns between 4 and 24 on the horizontal scale. B. 1 TV line = 64 µs = 214 horizontal clocks Figure 5. Horizontal Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 T1 = 299 ns 28 29 30 31 32 33 34 35 36 37 38 39 40 Horizontal Scale CBLK 4.458333-MHz Pulse S1 S2 S3 SH1 GT3/SH2 GT1/SH3 GT2 CCD Output CH1 CH2 CH3 DA 1 DA 2 DA 3 DA 4 DA 5 DA 6 DA 7 DU 1 DU 2 DU 3 DU 4 (2)A 1 A A 2 A 3 4 0(1) (1):Not For Use, (2):Half-Dark, DA:Dark, DU:Dummy, A:Active S/H Output CH1 CH2 CH3 DA 1 DA 2 DA 3 SW-Y Output DA 4 DA 5 DA 6 DA 7 DU 1 DU 2 Dark 1 2 3 4 5 6 7 DU 4 A 1 Dummy 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 8 9 10 11 12 1 BCP1 BCP2 CP2 NOTE A: This chart shows early mode only. Late mode is shown in Figure 7. Figure 6. S, SH, GT Timing (Start of H) 10 DU 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A 2 A 3 A 4 Active 2 3 4 5 6 7 8 9 10 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 T1 = 299 ns 30 29 T1 S1 ± 5 ns ± 5 ns S2 Early ± 5 ns S3 37.4 ± 10 ns S1 ± 5 ns ± 5 ns S2 Late ± 5 ns S3 ±10 ns(S1/SH1) SH1 ± 5 ns ± 5 ns GT3/SH2 ± 5 ns GT1/SH3 ± 5 ns ± 5 ns GT2 NOTE A: S1, S2, S3, SH1, GT3/SH2, GT1/SH3, GT2 are: Cycle time = 224.3 ns Pulse width = 74.8 ns Duty cycle = 1/3 Figure 7. S, SH, GT Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 T1 = 299 ns 211 212 (214) 213 0 T1 CBLK S1 S2 S3 SH1 GT3/SH2 GT1/SH3 GT2 CCD Output DA 1 A 232 CH1 CH2 233 DA 1 CH3 All Outputs Are Held Until Next Pulse S/H Output CH1 A 232 CH2 DA 1 233 DA 1 CH3 All Outputs Are Held Until Next Pulse SW-Y Output ACTIVE NOTE A: This chart shows early mode only. Late mode is shown in Figure 7. Figure 8. S, SH, GT Timing (End of H) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 H Timing 2T1 T1 = 299 ns 206 208 210 212 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 H Counter(T1) CBLK BCP1 BCP1 Mode 1 2-MHz Burst ABIN Mode 2 1-MHz Burst Mode 3 1 MHz (0.9554 MHz) Mode 4 2 MHz (1.9107 MHz) Always Free Running V Timing VD INTGO ABCLR (mode 1, mode 2) ABIN (mode 1, mode 2) ANTIBLOOMING MODE SELECTION MODE ABS0 ABS1 ABS2 0 X 0 0 ABIN OUTPUT No ABG 1 X 1 0 2 MHz burst 2 X 0 1 1 MHz burst 3 1 1 1 1 MHz const 4 0 1 1 2 MHz const X = Don’t care NOTES: A. For mode 1 and mode 4, duty cycle is 4/7 high and 3/7 low. B. Only the timing from odd field to even field is shown. The timing from even field to odd field is the same as that for odd field to even field minus the H-to-V timing. C. GPS is always high. Figure 9. ABIN Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 Powerup Operation Power Refresh Pulse (see Note B) SB (see Note A) VD (see Note C) 1026 Pulses 290 Pulses PI PS,T S1,S2,S3 GT ABIN Normal Operation See Note D Refresh Pulses (see Note B) SB VD (see Note A) 1026 Pulses 290 Pulses PI 290 Pulses PS,T S1,S2,S3 GT ABIN PD NOTES: A. B. C. D. A capacitor is connected to SB (between SB and GND). Refresh pulses (1026 pulses) of PI, PS and T are generated even if VD is not fed back to GP. VD is always fed back to GP and GPS is low. PI, PS, S1, S2, S3, ABIN, and GT go low when SB is low. Figure 10. Operation Chart of SB 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 VD GP 290 Pulses (see Note A) 302 Pulses (see Note B) PI PS,T GT ABIN BCP1, BCP2 Operation Mode Clear Operation Normal Operation NOTES: A. When VD is low and GP goes low, 290 pulses are generated for PI, PS, and T after VD goes high. B. When VD is high, GP goes low and 302 pulses are generated for PI, PS and T. C. GPS is at a steady-state low level. Figure 11. Normal Timing and Variable Integration T1 = 299 ns H Counter n n+1 n+2 n+3 n+4 m m+1 m+2 m+3 6 7 8 9 8 9 CLK HCR (see Note A) Reset Window m m+1 m+2 m+3 6 7 H Counter(T1) CBLK HCR (see Note B) NOTES: A. The H counter is preset to the value 6 when HCR changes from low to high. B. Output signals are changed one T1 clock after the change of the counter through the output latches. Figure 12. Operation of HCR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 1H = 64 µs V Counter (see Note A) n n+1 n+2 n+3 n+4 m m+1 m+2 m+3 16 17 18 19 CLK VCR Reset Window m m+1 m+2 V Counter (see Note A) CLK VCR NOTE A: The V counter is preset to the value 16 when VCR changes from low to high. Figure 13. Operation of VCR 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 m+3 16 17 18 19 SN28837 1/2-INCH PAL TIMER SOCS031B – JULY 1991 MECHANICAL DATA This plastic package consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compound. The compound withstands soldering temperatures with no deformation, and circuit performance characteristics remain stable when operated in high-humidity conditions. The package is intended for surface mounting, and leads are spaced on 1,0-mm centers with a 0,8-mm foot length. Leads require no additional cleaning or processing when used in soldered assembly. FS060 Designation per JEDEC Std 30: PQFP-G44 18,2 (0.717) 17,4 (0.685) 14,2 (0.559) 13,8 (0.543) 15 1 16 Index Corner Chamfer 60 (44 pin used for illustration to save space) 46 30 31 0,20 (0.008) 0,10 (0.004) 2,1 (0.083) 1,9 (0.075) 0° – 12° 45 0,65 (0.026) 0,45 (0.018) 0,95 (0.037) 0,65 (0.026) 1,4 (0.055) 0,10 (0.004) MIN 0,8 (0.031) Seating Plane 15,0 (0.591) NOM Detail A See Detail A ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7/94 17 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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