SN65LVELT22 www.ti.com............................................................................................................................................................................................ SLLS928 – DECEMBER 2008 3.3 V Dual LVTTL to DIfferential LVPECL Translator FEATURES APPLICATIONS • • • • 1 • • • 450 ps (typ) Propagation Delay Operating Range: VCC 3.0 V to 3.8 with GND = 0 V <50 ps (max) Output to Output Skew Built-in Temperature Compensation Drop in Compatible to MC100LVELT22 Data and Clock Transmission Over Backplane Signaling Level Conversion for Clock or Data DESCRIPTION The SN65ELT22 is a dual LVTTL to differential LVPECL translator buffer. It operates on +3V supply and ground only. The output is driven default high when the inputs are left floating or unused. The low output skew makes the device the ideal solution for clock or data signal translation. The SN65LVELT22 is housed in an industry standard SOIC-8 package and is also available in TSSOP-8 package option. PINOUT ASSIGNMENT Q0 1 8 VCC Q0 2 7 D0 Q1 6 D1 Q1 4 5 GND Table 1. Pin Description PIN FUNCTION D0, D1 TTL inputs Q0, Q0, Q1, Q1 PECL/ECL outputs VCC Positive supply GND Ground ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE LEAD FINISH SN65LVELT22D SN65LVELT22 SOIC NiPdAu SN65LVELT22DGK SN65LVELT22 SOIC-TSSOP NiPdAu Leaded device options not initially available. Contact TI sales representative for further details. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN65LVELT22 SLLS928 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT Absolute PECL mode supply voltage, VCC GND = 0 V 6 V VIN input voltage VI ≤ VCC 6 V Output current Continuous 50 Surge 100 mA Operating temperature range –40 to 85 °C Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POWER DISSIPATION RATINGS PACKAGE CIRCUIT BOARD MODEL POWER RATING TA < 25°C (mW) THERMAL RESISTANCE, JUNCTION TO AMBIENT NO AIRFLOW DERATING FACTOR TA > 25°C (mW/°C) POWER RATING TA = 85°C (mW) SOIC Low-K 719 139 7 288 High-K 840 119 8 336 Low-K 469 213 5 188 High-K 527 189 5 211 SOIC-TSSOP THERMAL CHARACTERISTICS PARAMETER θJB Junction-to Board Thermal Resistance θJC Junction-to Case Thermal Resistance PACKAGE VALUE UNIT SOIC 79 °C/W SOIC-TSSOP 120 SOIC 98 SOIC-TSSOP 74 °C/W KEY ATTRIBUTES CHARACTERISTICS Moisture sensitivity level VALUE Level 1 Flammability rating (Oxygen Index: 28 to 34) UL 94 V-0 at 0.125 in ESD-HBM 4 kV ESD-machine model 200 V ESD-charge device model 2 kV Meets or exceeds JEDEC Spec EIA/JESD78 latchup test 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 SN65LVELT22 www.ti.com............................................................................................................................................................................................ SLLS928 – DECEMBER 2008 PECL DC CHARACTERISTICS (1) (VCC = 3.3 V, GND = 0.0 V (2) –40°C CHARACTERISTICS ICC Power Supply Current VOH Output HIGH Voltage VOL (1) (2) (3) Output LOW Voltage MIN 25°C TYP MAX 23 (3) (3) MIN 85°C TYP MAX 33 25 MIN 33 TYP MAX 26 UNIT 33 mA 2275 2317 2420 2275 2331 2420 2275 2343 2420 mV 1490 1558 1680 1490 1556 1680 1490 1555 1680 mV Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Input parameters vary 1:1 with VCC. VCC can vary ±0.15 V Outputs are terminated through a 50-Ω resistor to VCC – 2.0 V. TTL DC CHARACTERISTICS (1) (VCC = 3.3 V; TA = –40°C to 85°C) CHARACTERISTIC CONDITION µA µA Input LOW current VIN = 0.5 V –0.2 mA Input clamp diode voltage IIN = –18 mA –1.2 V IIHH Input HIGH current max IIL VIK VIH Input HIGH voltage VIL Input LOW voltage 2.0 V 0.8 V Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. AC CHARACTERISTICS (1) (VCC = 3.3 V; GND = 0.0 V) –40°C CHARACTERISTIC MIN fMAX Max switching frequency (2), see Figure 5 tPLH/tPHL Propagation delay to output at 1.5V, see Figure 4 tSKEW 25°C TYP MAX MIN 1750 200 425 TYP 85°C MAX MIN 550 200 1750 550 200 445 TYP MAX 1700 460 20 50 20 50 20 50 Device-to-device skew (4) 30 100 30 100 30 100 Random clock jitter (RMS) tr/tf Output rise/fall times Q (20%–80%) 0.5 300 1.0 500 0.5 300 1.0 500 0.5 300 UNIT MHz 550 Within – device skew (3) tJITTER (2) (3) (4) UNIT 100 VIN = 2.7 V (1) TYP MAX VIN = VCC Input HIGH current (1) MIN 20 IIH ps ps 1.0 ps 500 ps Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Maximum switching frequency measured at output amplitude of 300 mVpp. This is measured between outputs under the identical transitions and conditions on any one device. Device-Device Skew is defined as identical transitions at identical VCC levels. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 3 SN65LVELT22 SLLS928 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com Typical Termination for Output Driver ZO = 50 W P P Driver Receiver N N ZO = 50 W 50 W 50 W VTT VTT = VCC - 2 V Figure 1. Termination for Output Driver 1.5 V 1.5 V IN OUT OUT tPLH tPHL Figure 2. Output Propagation Delay 80% 20% tr tf Figure 3. Output Rise and Fall Times 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 SN65LVELT22 www.ti.com............................................................................................................................................................................................ SLLS928 – DECEMBER 2008 1.5 V 1.5 V IN QO QO tPLH0 tPHL0 Q1 Q1 tPLH1 tPHL1 Device Skew = Higher [(tPLH1 - tPLH0), (tPHL1 - tPHL0)] Figure 4. Device Skew 1000 VCC = 3.3 V, GND = 0 V, Vswing = 0.8 V - 2 V 900 Output Amplitude - mV 800 700 TA = 85°C 600 500 TA = -40°C 400 TA = 25°C 300 200 100 0 0 500 1000 1500 f - Frequency - MHz 2000 2500 Figure 5. Output Amplitude vs. Frequency Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVELT22 5 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVELT22DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65LVELT22DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVELT22DGKR MSOP DGK 8 2500 346.0 346.0 29.0 SN65LVELT22DR SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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