ADS6425 www.ti.com SLWS197 – MARCH 2007 QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • Maximum Sample Rate: 125 MSPS 12-Bit Resolution with No Missing Codes 1.65-W Total Power Simultaneous Sample and Hold 70.3 dBFS SNR at Fin = 50 MHz 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR Trade-Off Serialized LVDS Outputs with Programmable Internal Termination Option Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp differential Internal Reference with External Reference Support No External Decoupling Required for References 3.3-V Analog and Digital Supply 64 QFN Package (9 mm × 9 mm) Pin Compatible 14-Bit Family (ADS644X) Base-station IF Receivers Diversity Receivers Medical Imaging Test Equipment DESCRIPTION The ADS6425 is a high performance 12-bit, 125-MSPS quad channel ADC. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB. The output interface is 2-wire, where each ADC's data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS6425 also includes the traditional 1-wire interface that can be used at lower sampling frequencies. An internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary. ADS6425 has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ADS6425 www.ti.com SLWS197 – MARCH 2007 LVDD LGND CAP AVDD AGND These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CLKP CLKM BIT Clock DCLKP DCLKM FRAME Clock FCLKP FCLKM PLL 12-Bit ADC Digital Encoder and Serializer 12-Bit ADC Digital Encoder and Serializer SHA 12-Bit ADC Digital Encoder and Serializer SHA 12-Bit ADC Digital Encoder and Serializer INA_P SHA INA_M INB_P SHA INB_M INC_P INC_M IND_P VCM DA1_P DA1_M DB0_P DB0_M DB1_P DB1_M DC0_P DC0_M DC1_P DC1_M DD0_P DD0_M DD1_P DD1_M REFM REFP IND_M DA0_P DA0_M Reference Parallel Interface Serial Interface SCLK RESET SEN SDATA CFG4 CFG3 CFG1 CFG2 PDN ADS6425 B0199-02 PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS6425 QFN-64 (2) RGC –40°C to 85°C AZ6425 (1) (2) 2 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS6425IRGCT 250, Tape/reel ADS6425IRGCR 2000, Tape/reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB. Submit Documentation Feedback ADS6425 www.ti.com SLWS197 – MARCH 2007 ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT AVDD Supply voltage range –0.3 to 3.9 V LVDD Supply voltage range –0.3 to 3.9 V Voltage between AGND and DGND –0.3 to 0.3 V Voltage between AVDD to LVDD –0.3 to 3.3 V Voltage applied to external pin, VCM –0.3 to 2.0 V Voltage applied to analog input pins – 0.3V to minimum ( 3.6, AVDD + 0.3V) V TA Operating free-air temperature range –40 to 85 °C TJ Operating junction temperature range 125 °C Tstg Storage temperature range –65 to 150 °C 220 °C Lead temperature 1,6 mm (1/16") from the case for 10 seconds (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 3.0 3.3 3.6 V LVDD 3.0 3.3 3.6 V SUPPLIES LVDS Buffer supply voltage ANALOG INPUTS Differential input voltage range 2 Vpp 1.5 ±0.1 Input common-mode voltage Voltage applied on VCM in external reference mode 1.45 1.50 V 1.55 V 125 MSPS CLOCK INPUT Input clock sample rate 5 Sine wave, ac-coupled Input clock amplitude differential (VCLKP– VCLKM) 0.4 ± 0.8 LVPECL, ac-coupled Vpp ± 0.35 LVDS, ac-coupled LVCMOS, ac-coupled Input Clock duty cycle 1.5 3.3 35% 50% 65% DIGITAL OUTPUTS CLOAD Maximum external load capacitance from each output pin to DGND Without internal termination 5 With internal termination RLOAD Differential load resistance (external) between the LVDS output pairs TA Operating free-air temperature Ω 100 –40 Submit Documentation Feedback pF 10 85 °C 3 ADS6425 www.ti.com SLWS197 – MARCH 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER TEST CONDITIONS MIN RESOLUTION TYP MAX UNIT 12 Bits 2.0 Vpp ANALOG INPUT Differential input voltage range Differential input capacitance 7 pF Analog input bandwidth 500 MHz Analog input common mode current (per input pin of each ADC) 155 µA REFERENCE VOLTAGES VREFB Internal reference bottom voltage 1.0 V VREFT Internal reference top voltage 2.0 V VCM Common mode output voltage 1.5 V VCM Output current capability ±4 mA DC ACCURACY No missing codes EO Assured Offset error -15 ±2 +15 mV Offset error temperature coefficient 0.05 Offset error temperature coefficient, channel-channel Internal reference error (VREFT-VREFB) -15 Internal reference error temperature coefficient EG Gain error (1) ±5 mV/°C 15 0.25 Does not include gain error caused due to internal reference error -1 0.3 mV mV/°C +1 % FS Gain error temperature coefficient ∆%/°C 0.005 Gain error temperature coefficient, channel-channel DNL Differential nonlinearity -0.9 INL Integral nonlinearity -2.5 PSRR DC Power supply rejection ratio 0.5 2.0 1.0 2.5 LSB LSB –0.5 mV/V POWER SUPPLY ICC Total supply current 412 mA IAVDD Analog supply current 90 mA ILVDD LVDS supply current 502 mA Total Power Power down (1) 4 Input clock running This is specified by design and characterization. It is not tested in production. Submit Documentation Feedback 1.65 1.8 W 77 150 mW ADS6425 www.ti.com SLWS197 – MARCH 2007 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC AC CHARACTERISTICS Fin = 10 MHz 70.9 Fin = 50 MHz 67.5 Fin = 100 MHz SNR Signal to noise ratio Fin = 170 MHz Fin = 230 MHz 69.9 0 dB gain 68.5 3.5 dB Coarse gain 68.1 0 dB gain 67.4 3.5 dB Coarse gain 67.1 Fin = 10 MHz 67 Fin = 100 MHz Signal to noise and distortion ratio Fin = 170 MHz Fin = 230 MHz RMS Output noise 69.7 66.9 3.5 dB Coarse gain 67.4 0 dB gain 66.5 Inputs tied to common-mode 0.407 Fin = 230 MHz 73 87 75 3.5 dB Coarse gain 79 0 dB gain 74 3.5 dB Coarse gain 78 73 Fin = 100 MHz Fin = 170 MHz Fin = 230 MHz 90 85 3.5 dB Coarse gain 88 0 dB gain 82 3.5 dB Coarse gain 85 73 Fin = 100 MHz Fin = 170 MHz Fin = 230 MHz Worst harmonic (other than HD2, HD3) dBc 90 Fin = 50 MHz Third harmonic 91 0 dB gain Fin = 10 MHz HD3 dBc 93 Fin = 50 MHz Second harmonic 83 0 dB gain Fin = 10 MHz HD2 LSB 90 Fin = 100 MHz Fin = 170 MHz dBFS 66 3.5 dB Coarse gain Fin = 50 MHz Spurious free dynamic range 70 0 dB gain Fin = 10 MHz SFDR dBFS 70.7 Fin = 50 MHz SINAD 70.5 83 87 0 dB gain 75 3.5 dB Coarse gain 79 0 dB gain 74 3.5 dB Coarse gain 78 Fin = 10 MHz 95 Fin = 50 MHz 94 Fin = 100 MHz 91 Fin = 170 MHz 88 Fin = 230 MHz 86 Submit Documentation Feedback dBc dBc 5 ADS6425 www.ti.com SLWS197 – MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP Fin = 10 MHz Fin = 50 MHz THD Total harmonic distortion Effective number of bits 81 Fin = 100 MHz 84 Fin = 170 MHz 73 Fin = 50 MHz IMD Two-tone intermodulation distortion Cross-talk UNIT 88 70 Fin = 230 MHz ENOB MAX dBc 72 10.8 11.4 F1= 46.09 MHz, F2 = 50.09 MHz 90 F1= 185.09 MHz, F2 = 190.09 MHz 82 Near channel, Frequency of interfering signal = 10 MHz 92 Bits dBFS dBFS Far channel, Frequency of interfering signal = 10 MHz 105 DIGITAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100Ω (1). All LVDS specifications are characterized, but not tested at production. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 10 µA Low-level input current 10 µA 4 pF High-level output voltage 1375 mV Low-level output voltage 1025 Input capacitance DIGITAL OUTPUTS |VOD| Output differential voltage VOS Output offset voltage Common-mode voltage of OUTP and OUTM Output capacitance Output capacitance inside the device, from either output to ground (1) 6 250 350 mV 450 1200 mV 2 pF IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair Submit Documentation Feedback mV ADS6425 www.ti.com SLWS197 – MARCH 2007 TIMING SPECIFICATIONS (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. PARAMETER tJ TEST CONDITIONS Aperture jitter MIN Uncertainty in the sampling instant Interface: 2-wire, DDR bit clock, 12x serialization TYP MAX UNIT 250 fs rms (4) tsu Data setup time (5) (6) Measured from zero crossing of data transitions to zero crossing of bit clock 0.4 0.6 ns th Data hold time (5) (6) Measured from zero crossing of bit clock to zero crossing of data transitions 0.5 0.7 ns tpd_clk Clock propagation delay (4) Input clock rising edge cross-over to frame clock rising edge cross-over 3.6 4.4 Bit clock cycle-cycle jitter (6) Frame clock cycle-cycle jitter (6) 5.2 ns 350 ps pp 75 ps pp Below specifications apply for 5 MSPS ≤ Fs ≤125 MSPS and all interface options. tA Aperture delay Delay from rising edge of input clock to the actual sampling instant Aperture delay variation, channel-channel Within the same device ADC Latency (7) Wake up time 1 2 -250 Time for a sample to propagate to the ADC output Figure 1 3 ns 250 ps Clock cycles 12 Time to valid data after coming out of global power down 100 Time to valid data after input clock is re-started 100 µs 200 clock cycles Time to valid data after coming out of channel standby µs tRISE Data rise time Data rise time measured from –100 mV to +100 mV 50 100 200 ps tFALL Data fall time Data fall time measured from +100 mV to –100 mV 50 100 200 ps tRISE Bit clock and Frame clock rise time Rise time measured from –100mV to +100mV 50 100 200 ps tFALL Bit clock and Frame clock fall time Fall time measured from +100mV to –100mV 50 100 200 ps LVDS Bit clock duty cycle 45% 50% 55% LVDS Frame clock duty cycle 47% 50% 53% (1) (2) (3) (4) (5) (6) (7) Timing parameters are ensured by design and characterization and not tested in production. CL is the external single-ended load capacitance between each output pin and ground. Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair. Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options. Timing parameters are measured at the end of a 2 inch pcb trace (100-Ω characteristic impedance) terminated by RLand CL. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as shown in Table 25 Submit Documentation Feedback 7 ADS6425 www.ti.com SLWS197 – MARCH 2007 Sample N+13 Sample N+12 Sample N+11 Sample N Input Signal tA Input Clock CLKM CLKP tPD_CLK Latency 12 Clocks Bit Clock Output Data DCLKP DCLKM DOP D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 Sample N–1 Frame Clock D6 D5 D4 D3 D2 D1 D0 DOM Sample N FCLKM FCLKP T0105-03 Figure 1. Latency DCLKP Bit Clock DCLKM tsu th tsu Output Data DOP, DOM th Dn+1 Dn T0106-03 Figure 2. LVDS Timings 8 Submit Documentation Feedback ADS6425 www.ti.com SLWS197 – MARCH 2007 DEVICE PROGRAMMING MODES ADS6425 offers flexibility with several programmable features that are easily configured. The device can be configured independently using either parallel interface control or serial interface programming. In addition, the device supports a third configuration mode, where both the parallel interface and the serial control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table (Table 2). If this additional level of flexibility is not required, the user can select either the serial interface programming or the parallel interface control. USING PARALLEL INTERFACE CONTROL ONLY To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3, CFG4, PDN, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up, the device will automatically get configured as per the parallel pin voltage settings (Table 3 to Table 6) and no reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are controlled in this mode—output data interface and format, power down modes, coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string as illustrated in Figure 3. Table 1 briefly describes the modes controlled by the parallel pins. Table 1. Parallel Pin Definition PIN SEN SCLK, SDATA CONTROL FUNCTIONS Coarse gain and internal/external reference. Sync, deskew patterns and global power down. PDN Dedicated pin for global power down CFG1 1-wire/2-wire and DDR/SDR bit clock CFG2 12x/14x serialization and SDR bit clock capture edge CFG3 Reserved function. Tie CFG3 to Ground. CFG4 MSB/LSB First and data format. USING SERIAL INTERFACE PROGRAMMING ONLY In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low. The Serial Interface section describes the register programming and register reset in more detail. Since the parallel pins (CFG1-4 and PDN) are not used in this mode, they must be tied to ground. The register override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface pins in this serial interface control ONLY mode. USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4 and PDN) can also be used to configure the device. The parallel interface control pins CFG1 to CFG4 and PDN are available. After power-up, the device will automatically get configured as per the parallel pin voltage settings (Table 3 to Table 9) and no reset is required. A simple resistor string can be used as illustrated in Figure 3. SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low. The Serial Interface section describes the register programming and register reset in more detail. Since some functions are controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table (Table 2). Submit Documentation Feedback 9 ADS6425 www.ti.com SLWS197 – MARCH 2007 Table 2. Priority Between Parallel Pins and Serial Registers PIN CFG1 to CFG4 FUNCTIONS SUPPORTED PRIORITY As described in Table 6 to Table 9 Register bits can control the modes ONLY if the <OVRD> bit is high. If the <OVRD> bit is LOW, then the control voltage on these parallel pins determines the function as per Tables PDN Global power down D0 bit in register 0x00 controls global power down ONLY if PDN pin is LOW. If PDN is high, device is in global power down mode. SEN Serial Interface Enable 3.5 dB coarse gain setting is controlled by bit D5 in register 0x0D ONLY if the <OVRD> bit is high. Else, it is in default setting of 0 dB coarse gain. Internal/External reference setting is determined by bit D5 in register 0x00. SCLK, SDATA Serial Interface Clock and Serial Interface Data Bits D5-D7 in register 0x0A control the SYNC and DESKEW output patterns. Power down is determined by bit D0 in 0x00 register. AVDD (5/8) AVDD 3R (5/8) AVDD GND 2R AVDD (3/8) AVDD (3/8) AVDD 3R To Parallel Pin GND Figure 3. Simple Scheme to Configure Parallel Pins 10 Submit Documentation Feedback ADS6425 www.ti.com SLWS197 – MARCH 2007 DESCRIPTION OF PARALLEL PINS Table 3. SCLK, SDATA Control Pins SCLK SDATA LOW LOW NORMAL conversion. DESCRIPTION LOW HIGH SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the deserialized data to the frame boundary. See Capture Test Patterns for details. HIGH LOW POWER DOWN –Global power down, all channels of the ADC are powered down, including internal references, PLL and output buffers. HIGH HIGH DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure deserializer uses the right clock edge. See Capture Test Patterns for details. Table 4. SEN Control Pin SEN 0 DESCRIPTION External reference and 0 dB coarse gain (Full-scale = 2V pp) (3/8)LVDD External reference and 3.5 dB coarse gain (Full-scale = 1.34V pp) (5/8)LVDD Internal reference and 3.5 dB coarse gain (Full-scale = 1.34V pp) LVDD Internal reference and 0 dB coarse gain (Full-scale = 2V pp) Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will automatically configure the device as per the voltage applied (Table 5 to Table 9). Table 5. PDN Control Pin PDN 0 AVDD DESCRIPTION Normal operation Power down global Table 6. CFG1 Control Pin CFG1 0 DESCRIPTION DDR bit clock and 1-wire interface (3/8)LVDD Not used (5/8)LVDD SDR bit clock and 2-wire interface LVDD DDR bit clock and 2-wire interface Table 7. CFG2 Control Pin CFG2 DESCRIPTION 0 12x serialization and capture at falling edge of bit clock (only with SDR bit clock) (3/8)LVDD 14x serialization and capture at falling edge of bit clock (only with SDR bit clock) (5/8)LVDD 14x serialization and capture at rising edge of bit clock (only with SDR bit clock) LVDD 12x serialization and capture at rising edge of bit clock (only with SDR bit clock) Table 8. CFG3 Control Pin CFG3 RESERVED - TIE TO GROUND Table 9. CFG4 Control Pin CFG4 0 DESCRIPTION MSB First and 2s complement (3/8)LVDD MSB First and Offset binary (5/8)LVDD LSB First and Offset binary LVDD LSB First and 2s complement Submit Documentation Feedback 11 ADS6425 www.ti.com SLWS197 – MARCH 2007 SERIAL INTERFACE The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with non-50% duty cycle SCLK. The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data. Register Reset After power-up, the internal registers must be reset to their default values. This can be done in one of two ways: 1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR 2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high– this resets the registers to their default values and then self-resets the <RST> bit to LOW. When RESET pin is not used, it must be tied to LOW. Register Address SDATA A4 A3 A2 A1 Register Data A0 D10 D9 D8 D7 D6 t(SCLK) D5 D4 D3 D2 D1 D0 t(DH) t(DSU) SCLK t(SLOADH) t(SLOADS) SEN RESET T0109-03 Figure 4. Serial Interface Timing 12 Submit Documentation Feedback ADS6425 www.ti.com SLWS197 – MARCH 2007 SERIAL INTERFACE TIMING CHARACTERISTICS Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted. PARAMETER MIN TYP > dc MAX UNIT 20 MHz fSCLK SCLK Frequency, fSCLK = 1/tSCLK tSLOADS SEN to SCLK Setup time 25 ns tSLOADH SCLK to SEN Hold time 25 ns tDSU SDATA Setup time 25 ns tDH SDATA Hold time 25 ns 100 ns Time taken for register write to take effect after 16th SCLK falling edge RESET TIMING Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, unless otherwise noted. PARMATER CONDITIONS MIN t1 Power-on delay time Delay from power-up of AVDD and LVDD to RESET pulse active t2 Reset pulse width Pulse width of active RESET signal t3 Register write delay time Delay from RESET disable to SEN active tPO Power-up delay time TYP UNIT 5 ms 10 ns 25 Delay from power-up of AVDD and LVDD to output stable MAX ns 6.5 ms Power Supply AVDD, LVDD t1 RESET t2 t3 SEN T0108-03 Figure 5. Reset Timing Submit Documentation Feedback 13 ADS6425 www.ti.com SLWS197 – MARCH 2007 SERIAL REGISTER MAP Table 10. Summary of Functions Supported By Serial Interface REGISTER ADDRESS A4 - A0 REGISTER FUNCTIONS (1) (2) D10 D9 D8 D7 00 <RST> S/W RESET 0 0 0 04 0 0 0 0 0 <DF> DATA FORMAT 2S COMP OR STRAIGHT BINARY 0 0A 0 0D 10 11 (1) (2) 14 D5 <REF> INTERNAL OR EXTERNAL D4 D3 <PDN CHD> POWER DOWN CH D <PDN CHC> POWER DOWN CHC D2 <PDN CHB> POWER DOWN CH B <CLKIN GAIN> INPUT CLOCK BUFFER GAIN CONTROL <PATTERNS> TEST PATTERNS 0 0 0 D1 D0 <PDN CHA> POWER DOWN CH A <PDN GLOBAL> GLOBAL POWER DOWN 0 0 0 0 <CUSTOM A> CUSTOM PATTERN (LOWER 11 BITS) 0B 0C D6 <FINE GAIN> FINE GAIN CONTROL (1dB to 6 dB) <OVRD> OVERRIDE BIT 0 0 0 0 0 BYTE-WISE OR BIT-WISE MSB OR LSB FIRST <COARSE GAIN> COURSE GAIN ENABLE <TERM CLK> LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS WORD-WISE CONTROL 0 0 <CUSTOM B> CUSTOM PATTERN (UPPER 5 BITS) FALLING OR RISING BIT CLOCK CAPTURE EDGE 0 <LVDS CURR> LVDS CURRENT SETTINGS 0 0 DDR OR SDR BIT CLOCK 1-WIRE OR 2-WIRE INTERFACE <CURR DOUBLE> LVDS CURRENT DOUBLE <TERM DATA> LVDS INTERNAL TERMINATION - DATA OUTPUTS The unused bits in each register (shown by white cells in above table) must be programmed as 0. Multiple functions in a register can be programmed in a single write operation. Submit Documentation Feedback 12X OR 14X SERIALIZE ADS6425 www.ti.com SLWS197 – MARCH 2007 DESCRIPTION OF SERIAL REGISTERS Table 11. Serial Register A REGISTER ADDRESS A4 - A0 00 BITS D10 <RST> S/W RESET D9 0 D8 0 D7 0 D6 D5 D4 D3 D2 D1 D0 0 <REF> INTERNAL OR EXTERNAL <PDN CHD> POWER DOWN CH D <PDN CHC> POWER DOWN CHC <PDN CHB> POWER DOWN CH B <PDN CHA> POWER DOWN CH A <PDN> GLOBAL POWER DOWN D0 - D4 Power down modes D0 <PDN GLOBAL> 0 Normal operation 1 Global power down, including all channels ADCs, internal references, internal PLL and output buffers D1 <PDN CHA> 0 CH A powered up 1 CH A ADC powered down D2 <PDN CHB> 0 CH B powered up 1 CH B ADC powered down D3 <PDN CHC> 0 CH C powered up 1 CH C ADC powered down D4 <PDN CHD> 0 CH D powered up 1 CH D ADC powered down D5 <REF> Reference 0 Internal reference enabled 1 External reference enabled D10 <RST> 1 Software reset applied – resets all internal registers and self-clears to 0 Submit Documentation Feedback 15 ADS6425 www.ti.com SLWS197 – MARCH 2007 Table 12. Serial Register B REGISTER ADDRESS A4 - A0 04 BITS D10 0 D9 0 D8 D7 0 D6 D5 D4 D3 D2 D1 D0 0 0 <CLKIN GAIN> INPUT CLOCK BUFFER GAIN CONTROL 0 D6 - D2 <CLKIN GAIN> Input clock buffer gain control 11000 Gain 0 Minimum gain 00000 Gain 1 01100 Gain 2 01010 Gain 3 01001 Gain 4 01000 Gain 5 Maximum gain Table 13. Serial Register C REGISTER ADDRESS A4 - A0 00 BITS D10 D9 D8 0 <DF> DATA DORMAT 2S COMP OR STRAIGHT BINARY 0 D7 D6 D5 <PATTERNS> TEST PATTERNS D4 D3 D2 D1 D0 0 0 0 0 0 D7 - D5 <PATTERNS> Capture test patterns 000 Normal ADC operation 001 Output all zeros 010 Output all ones 011 Output toggle pattern 100 Unused 101 Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C) 110 Output DESKEW pattern (serial stream of 1010..) 111 Output SYNC pattern D9 <DF> Data format selection 0 2s complement format 1 Straight binary format 16 Submit Documentation Feedback ADS6425 www.ti.com SLWS197 – MARCH 2007 Table 14. Serial Register D REGISTER ADDRESS A4 - A0 BITS D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 <CUSTOM A> CUSTOM PATTERN (LOWER 11 BITS) 0B D10 - D0 <CUSTOM A> Lower 11 bits of custom pattern <DATAOUT10>…<DATAOUT0> Table 15. Serial Register E REGISTER ADDRESS A4 - A0 0C BITS D10 D9 D8 <FINE GAIN> FINE GAIN CONTROL (1 dB to 6 dB) D7 D6 0 D5 0 D4 D3 D2 D1 D0 <CUSTOM B> CUSTOM PATTERN (UPPER 5 BITS) 0 D4 - D0 <CUSTOM B> Upper 5 bits of custom pattern <DATAOUT15>…<DATAOUT11> D10-D8 <FINE GAIN> Fine gain control 000 0 dB gain (Full-scale range = 2.00 Vpp) 001 1 dB gain (Full-scale range = 1.78 Vpp) 010 2 dB gain (Full-scale range = 1.59 Vpp) 011 3 dB gain (Full-scale range = 1.42 Vpp) 100 4 dB gain (Full-scale range = 1.26 Vpp) 101 5 dB gain (Full-scale range = 1.12 Vpp) 110 6 dB gain (Full-scale range = 1.00 Vpp) Table 16. Serial Register F REGISTER ADDRESS A4 - A0 0D BITS D10 <OVRD> OVER-RIDE BITE D9 D8 0 0 D7 BYTE-WISE OR BIT-WISE D6 MSB OR LSB FIRST D5 D4 D3 D2 D1 D0 <COARSE GAIN> COURSE GAIN ENABLE FALLING OR RISING BIT CLOCK CAPTURE EDGE 0 14-BIT OR 16-BIT SERIALIZE DDR OR SDR BIT CLOCK 1-WIRE OR 2-WIRE INTERFACE D0 Interface selection 0 1 wire interface 1 2 wire interface D1 Bit clock selection (only in 2-wire interface) 0 DDR bit clock 1 SDR bit clock D2 Serialization selection 0 12X serialization 1 14X serialization D4 Bit clock capture edge (only when SDR bit clock is selected, D1=1) 0 Capture data with falling edge of bit clock 1 Capture data with rising edge of bit clock Submit Documentation Feedback 17 ADS6425 www.ti.com SLWS197 – MARCH 2007 D5 <COARSE GAIN>Coarse gain control 0 0 dB coarse gain 1 3.5dB coarse gain (Full-scale range = 1.34 Vpp) D6 MSB or LSB first selection 0 MSB First 1 LSB First D7 Byte/bit wise outputs (only when 2-wire is selected) 0 Byte wise 1 Bit wise D10 <OVRD> Over-ride bit. All the functions in register 0x0D can also be controlled using the parallel control pins. By setting bit <OVRD> =1, the contents of register 0x0D will over-ride the settings of the parallel pins. 0 Disable over-ride 1 Enable over-ride Table 17. Serial Register G REGISTER ADDRESS A4 - A0 10 BITS D10 D9 D8 D7 D6 D5 <TERM CLK> LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS D4 D3 D2 <LVDS CURR> LVDS CURRENT SETTINGS D0 <CURR DOUBLE> LVDS current double for data outputs 0 Nominal LVDS current, as set by <D5…D2> 1 Double the nominal value D1 <CURR DOUBLE> LVDS current double for bit and word clock outputs 0 Nominal LVDS current, as set by <D5…D2> 1 Double the nominal value D3-D2 <LVDS CURR> LVDS current setting for data outputs 00 3.5 mA 01 4 mA 10 2.5 mA 11 3 mA D5-D4 <LVDS CURR> LVDS current setting for bit and word clock outputs 00 3.5 mA 01 4 mA 10 2.5 mA 11 3 mA D10-D6 <TERM CLK> LVDS internal termination for bit and word clock outputs 00000 No internal termination 00001 166 Ω 18 Submit Documentation Feedback D1 D0 <LVDS DOUBLE> LVDS CURRENT DOUBLE ADS6425 www.ti.com SLWS197 – MARCH 2007 00010 200 Ω 00100 250 Ω 01000 333 Ω 10000 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω 100 Ω 00101 Table 18. Serial Register H REGISTER ADDRESS A4 - A0 11 BITS D10 D9 WORD-WISE CONTROL D8 D7 D6 D5 0 0 0 0 D4 D3 D2 D1 D0 <TERM DATA> LVDS INTERNAL TERMINATION - DATA OUTPUTS D4-D0 <TERM DATA> LVDS internal termination for data outputs 00000 No internal termination 00001 166 Ω 00010 200 Ω 00100 250 Ω 01000 333 Ω 10000 500 Ω Any combination of above bits can also be programmed, resulting in a parallel combination of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω 00101 100 Ω D10-D9 Only when 2-wire interface is selected 00 Byte-wise or bit-wise output, 1x frame clock 11 Word-wise outp