ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS Check for Samples: ADS6445, ADS6444, ADS6443, ADS6442 FEATURES • 1 • • • • • • • • • • Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes Simultaneous Sample and Hold 3.5dB Coarse Gain and up to 6dB Programmable Fine Gain for SFDR/SNR Trade-Off Serialized LVDS Outputs with Programmable Internal Termination Option Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 mVPP Internal Reference with External Reference Support No External Decoupling Required for References 3.3-V Analog and Digital Supply 64 QFN Package (9 mm × 9 mm) • Pin Compatible 12-Bit Family (ADS642X SLAS532A) Feature Compatible Dual Channel Family (ADS624X - SLAS542A, ADS644X - SLAS543A) APPLICATIONS • • • • Base-Station IF Receivers Diversity Receivers Medical Imaging Test Equipment Table 1. ADS64XX Quad Channel Family 125 MSPS 105 MSPS 80 MSPS 65 MSPS ADS644X 14 Bit ADS6445 ADS6444 ADS6443 ADS6442 ADS642X 12 Bit ADS6425 ADS6424 ADS6423 ADS6422 Table 2. Performance Summary Fin = 10MHz (0 dB gain) SFDR, dBc Fin = 170MHz (3.5 dB gain) SINAD, dBFS ADS6445 ADS6444 ADS6443 ADS6442 87 91 92 93 79 83 84 84 Fin = 10MHz (0 dB gain) 73.4 73.4 74.2 74.3 Fin = 170MHz (3.5 dB gain) 68.3 69.3 69.4 70 420 340 300 265 Power, per channel, mW DESCRIPTION The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB. The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling frequencies. An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) LVDD LGND CAP AVDD AGND The ADS644X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C). CLKP CLKM BIT Clock DCLKP DCLKM FRAME Clock FCLKP FCLKM PLL INA_P SHA INA_M INB_P SHA 14-Bit ADC Digital Encoder and Serializer 14-Bit ADC Digital Encoder and Serializer 14-Bit ADC Digital Encoder and Serializer 14-Bit ADC Digital Encoder and Serializer INB_M INC_P SHA INC_M IND_P SHA VCM DA1_P DA1_M DB0_P DB0_M DB1_P DB1_M DC0_P DC0_M DC1_P DC1_M DD0_P DD0_M DD1_P DD1_M REFM REFP IND_M DA0_P DA0_M Reference Parallel Interface Serial Interface 2 Submit Documentation Feedback SCLK RESET SEN SDATA CFG4 CFG3 CFG1 CFG2 PDN ADS644x B0199-03 Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS6445 QFN-64 (2) RGC –40°C to 85°C AZ6445 ADS6444 QFN-64 (2) RGC –40°C to 85°C AZ6444 ADS6443 QFN-64 (2) RGC –40°C to 85°C AZ6443 ADS6442 QFN-64 (2) RGC –40°C to 85°C AZ6442 (1) (2) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS6445IRGCT 250, Tape/reel ADS6445IRGCR 2000, Tape/reel ADS6444IRGCT 250, Tape/reel ADS6444IRGCR 2000, Tape/reel ADS6443IRGCT 250, Tape/reel ADS6443IRGCR 2000, Tape/reel ADS6442IRGCT 250, Tape/reel ADS6442IRGCR 2000, Tape/reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC = 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT AVDD Supply voltage range –0.3 to 3.9 V LVDD Supply voltage range –0.3 to 3.9 V Voltage between AGND and DGND –0.3 to 0.3 V Voltage between AVDD to LVDD –0.3 to 3.3 V Voltage applied to external pin, VCM –0.3 to 2.0 V Voltage applied to analog input pins –0.3V to minimum ( 3.6, AVDD + 0.3V) V TA Operating free-air temperature range –40 to 85 °C TJ Operating junction temperature range 125 °C Tstg Storage temperature range –65 to 150 °C 220 °C Lead temperature 1,6 mm (1/16") from the case for 10 seconds (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 3 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT SUPPLIES AVDD Analog supply voltage 3.0 3.3 3.6 V LVDD LVDS Buffer supply voltage 3.0 3.3 3.6 V ANALOG INPUTS Differential input voltage range 2 Input common-mode voltage Vpp 1.5 ±0.1 Voltage applied on VCM in external reference mode 1.45 1.50 V 1.55 V CLOCK INPUT Input clock sample rate, Fsrated ADS6445 5 125 ADS6444 5 105 ADS6443 5 80 ADS6442 5 Sine wave, ac-coupled Input clock amplitude differential (VCLKP – VCLKM) 0.4 LVPECL, ac-coupled 65 1.5 ± 0.8 LVDS, ac-coupled Vpp ± 0.35 LVCMOS, ac-coupled Input Clock duty cycle MSPS 3.3 35% 50% 65% DIGITAL OUTPUTS Without internal termination CLOAD Maximum external load capacitance from each output pin to DGND RLOAD Differential load resistance (external) between the LVDS output pairs TA Operating free-air temperature 4 Submit Documentation Feedback 5 With internal termination pF 10 Ω 100 –40 85 °C Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). ADS6445 Fs = 125 MSPS PARAMETER MIN RESOLUTION TYP ADS6444 Fs = 105 MSPS MAX MIN TYP ADS6443 Fs = 80 MSPS MAX MIN TYP ADS6442 Fs = 65 MSPS MAX MIN TYP UNIT MAX 14 14 14 14 Bits 2.0 2.0 2.0 2.0 VPP 7 7 7 7 pF Analog input bandwidth 500 500 500 500 MHz Analog input common mode current (per input pin of each ADC) 155 130 100 81 μA ANALOG INPUT Differential input voltage range Differential input capacitance REFERENCE VOLTAGES VREFB Internal reference bottom voltage 1.0 1.0 1.0 1.0 V VREFT Internal reference top voltage 2.0 2.0 2.0 2.0 V ΔVREF Internal reference error (VREFT–VREFB) VCM Common mode output voltage 1.5 1.5 1.5 1.5 V VCM output current capability ±4 ±4 ±4 ±4 mA -15 ±2 15 -15 ±2 15 -15 ±2 15 -15 ±2 15 mV DC ACCURACY No missing codes EO Offset error, across devices and across channels within a device Assured –15 Offset error temperature coefficient, across devices and across channels within a device ±2 Assured 15 –15 0.05 ±2 Assured 15 –15 0.05 Assured ±2 15 –15 0.05 ±2 15 0.05 mV mV/°C There are two sources of gain error - internal reference inaccuracy and channel gain error EGREF Gain error due to internal reference inaccuracy alone, (ΔVREF /2.0) % -0.75 Reference gain error temperature coefficient EGCHAN Gain error of channel alone, across devices and across channels within a device (1) Differential nonlinearity, Fin = 50 MHz INL Integral nonlinearity, Fin = 50 MHz PSRR DC power supply rejection ratio 0.75 -0.75 0.0125 –1 Channel gain error temperature coefficient, across devices and across channels within a device DNL 0.1 ±0.3 0.1 0.75 -0.75 0.0125 1 –1 0.005 0.1 0.75 -0.75 0.0125 ±0.3 1 –1 0.005 0.1 0.75 Δ%/°C 0.0125 ±0.3 1 –1 0.005 ±0.3 % FS 1 % FS Δ%/°C 0.005 –0.9 ±0.6 2.0 –0.9 ±0.6 2.0 –0.9 ±0.5 1.8 –0.9 ±0.5 1.8 LSB -5 ±3 5 -0.5 ±3 5 4.5 ±2 4.5 4.5 ±2 4.5 LSB 0.5 0.5 0.5 0.5 mV/V POWER SUPPLY ICC Total supply current 502 410 360 320 mA IAVDD Analog supply current 410 322 280 245 mA (1) This is specified by design and characterization; it is not tested in production. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 5 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 Fs = 125 MSPS MIN ILVDD LVDS supply current MAX 92 Total power Power down (with input clock stopped) 6 TYP ADS6444 Fs = 105 MSPS Submit Documentation Feedback MIN TYP ADS6443 Fs = 80 MSPS MAX 88 MIN TYP ADS6442 Fs = 65 MSPS MAX 80 MIN TYP UNIT MAX 75 mA 1.65 1.8 1.35 1.5 1.18 1.3 1.05 1.2 W 77 150 77 150 77 150 77 150 mW Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 Fs = 125 MSPS TEST CONDITIONS MIN TYP MAX ADS6444 Fs = 105 MSPS MIN TYP MAX ADS6443 Fs = 80 MSPS MIN TYP MAX ADS6442 Fs = 65 MSPS MIN TYP UNIT MAX DYNAMIC AC CHARACTERISTICS Fin = 10 MHz Fin = 50 MHz 68.5 Fin = 70 MHz SNR Signal to noise ratio Fin = 230 MHz 74.5 73.8 70.5 74 73 73.4 73.6 72.2 72.7 72.8 69.9 70.2 70.5 70.7 3.5 dB Coarse gain 69.4 69.7 69.7 70.2 0 dB gain 68.7 68.8 68.1 69.2 3.5 dB Coarse gain 68.1 68.2 68.2 68.9 73.4 73.4 72.3 71.7 68 Fin = 70 MHz 71.2 Fin = 100 MHz 70 73.7 73.2 71.8 72 72.2 72 0 dB gain 67.9 69.8 69.9 70.3 3.5 dB Coarse gain 68.3 69.3 69.4 70 0 dB gain 67.8 67.7 67.6 68.3 3.5 dB Coarse gain 67.9 67.6 68.1 68.4 Inputs tied to common-mode 1.05 1.05 1.05 1.05 87 91 81 80 Fin = 10 MHz Fin = 50 MHz 73 Fin = 70 MHz 78 Fin = 100 MHz Fin = 170 MHz Fin = 230 MHz 86 88 84 82 0 dB gain 76 79 80 81 3.5 dB Coarse gain 79 83 84 84 0 dB gain 77 77 78 79 3.5 dB Coarse gain 80 80 82 82 93 94 87 88 73 87 Fin = 100 MHz Fin = 230 MHz dBc 97 90 79 92 88 90 92 89 90 87 87 0 dB gain 83 84 86 86 3.5 dB Coarse gain 85 86 88 88 0 dB gain 80 81 82 83 3.5 dB Coarse gain 82 83 84 85 Copyright © 2007–2009, Texas Instruments Incorporated 74 96 77 LSB 88 86 Fin = 70 MHz Fin = 170 MHz 79 86 Fin = 50 MHz dBFS 93 87 81 Fin = 10 MHz 74 92 77 dBFS 74.3 73.5 73 Fin = 230 MHz 68.5 74.2 69.5 72 SINAD Signal to noise and Fin = 170 distortion ratio MHz HD2 Second harmonic 69 74.4 70 72.1 Fin = 50 MHz SFDR Spurious free dynamic range 73.2 0 dB gain Fin = 10 MHz RMS Output noise 73.8 73.1 72.7 Fin = 100 MHz Fin = 170 MHz 73.7 Submit Documentation Feedback Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 dBc 7 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode (unless otherwise noted). PARAMETER ADS6445 Fs = 125 MSPS TEST CONDITIONS MIN Fin = 10 MHz Fin = 50 MHz HD3 Third harmonic THD Total harmonic distortion Cross-talk 8 TYP 91 80 Fin = 100 MHz MIN TYP 77 87.5 MAX ADS6442 Fs = 65 MSPS MIN 92 TYP 88 86 86 88 84 82 0 dB gain 76 79 80 81 3.5 dB Coarse gain 79 83 84 84 0 dB gain 77 77 78 79 3.5 dB Coarse gain 80 80 82 82 Fin = 10 MHz 91 91 94 95 Fin = 50 MHz 87 87 92 93 Fin = 100 MHz 90 91 92 92 Fin = 170 MHz 88 88 90 90 Fin = 230 MHz 87 87 87 87 Fin = 10 MHz 86 89.5 90 Fin = 50 MHz 71 80 Fin = 70 MHz 75 72 85.5 79 86 83 80.5 Fin = 170 MHz 73.5 77 78.5 79.5 Fin = 230 MHz 74 75 76 77 11.1 11.3 11.9 dBc 85.6 84.5 11.7 dBc 91 77 Fin = 100 MHz 11.0 UNIT MAX 93 79 86 Fin = 170 MHz 74 MAX ADS6443 Fs = 80 MSPS 81 11.4 dBc 12 Bits 11.7 F1= 46.09 MHz, F2 = 50.09 MHz 88 90 96 100 F1= 185.09 MHz, F2 = 190.09 MHz 86 88 93 96 Near channel Cross-talk signal frequency = 10 MHz 90 92 94 100 Far channel Cross-talk signal frequency = 10 MHz 103 105 106 108 1 1 1 1 Clock cycles 35 35 35 35 dBc Recovery to within 1% (of final Input overload value) for 6-dB overload with recovery sine wave input AC PSRR Power Supply Rejection Ratio MIN 81 78 ENOB Fin = 50 MHz Effective number of bits Fin = 70 MHz IMD 2-Tone intermodulatio n distortion MAX 87 Fin = 70 MHz Fin = 230 MHz Worst harmonic (other than HD2, HD3) 73 TYP ADS6444 Fs = 105 MSPS dBFS dBc < 100 MHz signal, 100 mVPP on AVDD supply Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 DIGITAL CHARACTERISTICS The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100Ω (1). All LVDS specifications are characterized, but not tested at production. PARAMETER ASD6445/ADS6444 ADS6443/ADS6442 TEST CONDITIONS MIN TYP UNIT MAX DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 10 μA Low-level input current 10 μA 4 pF 1375 mV Input capacitance DIGITAL OUTPUTS High-level output voltage Low-level output voltage 1025 Output differential voltage |VOD| 250 Output offset voltage VOS Common-mode voltage of OUTP and OUTM Output capacitance Output capacitance inside the device, from either output to ground (1) 350 mV 450 mV 1200 mV 2 pF IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 9 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com TIMING SPECIFICATIONS (1) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. PARAMETER tJ TEST CONDITIONS ADS6445 Fs = 125 MSPS MIN Aperture jitter Uncertainty in the sampling instant ADS6444 Fs = 105 MSPS TYP MAX MIN 250 TYP ADS6443 Fs = 80 MSPS MAX MIN 250 ADS6442 Fs = 65 MSPS TYP MAX MIN 250 TYP UNIT MAX 250 fs rms INTERFACE: 2-wire, DDR bit clock, 14x serialization tsu Data setup time (4) (5) (6) From data cross-over to bit clock cross-over 0.35 0.55 0.45 0.65 0.65 0.85 0.8 1.1 ns th Data hold time (4) (5) (6) From bit clock cross-over to data cross-over 0.35 0.58 0.5 0.7 0.7 0.9 0.8 1.1 ns Frame setup time From frame clock rising edge cross-over to bit clock rising edge cross-over 0.35 0.55 0.45 0.65 0.65 0.85 0.8 1.1 ns th Frame hold time From bit clock falling edge cross-over to frame clock falling edge cross-over 0.35 0.58 0.5 0.7 0.7 0.9 0.8 1.1 ns tpd_cl Clock propagation delay (6) Input clock rising edge cross-over to frame clock rising edge cross-over 3.4 4.4 3.4 4.4 3.4 4.4 3.4 4.4 tsu k 5.4 5.4 5.4 5.4 ns Bit clock cycle-cycle jitter (5) 350 350 350 350 ps pp Frame clock cycle-cycle jitter (5) 75 75 75 75 ps pp Below specifications apply for 5 MSPS ≤ Fs ≤ 125 MSPS and all interface options. tA (1) (2) (3) (4) (5) (6) 10 Aperture delay Delay from input clock rising edge to the actual sampling instant Aperture delay variation Channelchannel within same device 1 2 –250 ±80 3 1 2 3 1 2 3 1 2 3 ns 250 –250 ±80 250 –250 ±80 250 –250 ±80 250 ps Timing parameters are ensured by design and characterization and not tested in production. CL is the external single-ended load capacitance between each output pin and ground. Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair. Timing parameters are measured at the end of a 2 inch pcb trace (100-Ω characteristic impedance) terminated by RLand CL. Setup and hold time specifications take into account the effect of jitter on the output data and clock. Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 TIMING SPECIFICATIONS (1) (continued) Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. PARAMETER ADC Latency (7) TEST CONDITIONS ADS6445 Fs = 125 MSPS MIN TYP MAX Time for a sample to propagate to ADC outputs, see Figure 1 ADS6444 Fs = 105 MSPS MIN 12 Time to valid data after coming out of global power down Time to valid data after input Wake up time clock is re-started Time to valid data after coming out of channel standby TYP MAX ADS6443 Fs = 80 MSPS MIN 12 TYP MAX ADS6442 Fs = 65 MSPS MIN 12 TYP UNIT MAX Clock cycles 12 100 100 100 100 μs 100 100 100 100 μs 200 200 200 200 Clock cycles tRISE Data rise time From –100 mV to +100 mV 50 100 200 50 100 50 100 200 50 100 200 ps tFALL Data fall time From +100 mV to –100 mV 50 100 200 50 100 50 100 200 50 100 200 ps tRISE Bit clock and frame clock rise time From –100mV to +100mV 50 100 200 50 100 50 100 200 50 100 200 ps tFALL Bit clock and frame clock fall time From +100mV to –100mV 50 100 200 50 100 50 100 200 50 100 200 ps LVDS Bit clock duty cycle 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55% LVDS Frame clock duty cycle 47% 50% 53% 47% 50% 53% 47% 50% 53% 47% 50% 53% (7) Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as shown in Table 27. Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 11 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Sample N+13 Sample N+12 Sample N+11 Sample N Input Signal tA Input Clock CLKM CLKP tPD_CLK Latency 12 Clocks DCLKP Bit Clock DCLKM Output Data DOM DOP D13 D12 D11 D10 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 Sample N–1 Frame Clock D6 D5 D4 D3 D2 D1 D0 Sample N FCLKM FCLKP T0105-04 Figure 1. Latency DCLKP Bit Clock DCLKM tsu th tsu Output Data P (differential) DA, DB, DC, DD M th Dn+1 Dn tsu th FCLKP Frame Clock FCLKM Figure 2. LVDS Timings 12 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 DEVICE PROGRAMMING MODES ADS644X offers flexibility with several programmable features that are easily configured. The device can be configured independently using either parallel interface control or serial interface programming. In addition, the device supports a third configuration mode, where both the parallel interface and the serial control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table (refer to Table 4). If this additional level of flexibility is not required, the user can select either the serial interface programming or the parallel interface control. USING PARALLEL INTERFACE CONTROL ONLY To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3, CFG4, PDN, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up, the device will automatically get configured as per the parallel pin voltage settings (refer to Table 5 to Table 8) and no reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are controlled in this mode—output data interface and format, power down modes, coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string (with 10% tolerance resistors) as illustrated in Figure 3. Table 3 has a description of the modes controlled by the parallel pins. Table 3. Parallel Pin Definition PIN SEN SCLK, SDATA CONTROL FUNCTIONS Coarse gain and internal/external reference. Sync, deskew patterns and global power down. PDN Dedicated pin for global power down CFG1 1-Wire/2-wire and DDR/SDR bit clock CFG2 14x/16x Serialization and SDR bit clock capture edge CFG3 Reserved function. Tie CFG3 to Ground. CFG4 MSB/LSB First and data format. USING SERIAL INTERFACE PROGRAMMING ONLY In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in more detail. Since the parallel pins (CFG1-4 and PDN) are not used in this mode, they must be tied to ground. The register override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface pins in this serial interface control ONLY mode. USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4 and PDN) can also be used to configure the device. The parallel interface control pins CFG1 to CFG4 and PDN are available. After power-up, the device will automatically get configured as per the parallel pin voltage settings (refer to Table 5 to Table 11) and no reset is required. A simple resistor string can be used as illustrated in Figure 3. SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low. The Serial Interface section describes the register programming and register reset in more detail. Since some functions are controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table (refer to Table 4). Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 13 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Table 4. Priority Between Parallel Pins and Serial Registers PIN FUNCTIONS SUPPORTED PRIORITY As described in Table 8 to Table 11 Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> bit is low, then the control voltage on these parallel pins determines the function. PDN Global Power Down Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is high, device is in global power down. SEN Serial Interface Enable CFG1 to CFG4 Coarse gain is controlled by register bit <COARSE GAIN> only if the <OVRD> bit is high. Else, device has 0 dB coarse gain. Internal/External Reference setting is determined by register bit <REF>. SCLK, SDATA Serial Interface Clock and Serial Interface Data pins Register bits <PATTERNS> control the sync and deskew output patterns. Power down is determined by bit <PDN GLOBAL> LVDD LVDD (5/6) LVDD R (5/8) LVDD GND 2R (5/8) LVDD 3R (5/6) LVDD LVDD GND 2R LVDD (3/8) LVDD (3/6) LVDD (3/8) LVDD (3/6) LVDD 3R 3R To SEN Pin To CFGx Pins GND GND Figure 3. Simple Scheme to Configure Parallel Pins 14 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 ADS6445, ADS6444 ADS6443, ADS6442 www.ti.com SLAS531B – MAY 2007 – REVISED DECEMBER 2009 DESCRIPTION OF PARALLEL PINS Table 5. SCLK, SDATA Control Pins SCLK SDATA LOW LOW NORMAL conversion. DESCRIPTION LOW HIGH SYNC – ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the deserialized data to the frame boundary. See Capture Test Patterns for details. HIGH LOW POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references, PLL and output buffers. HIGH HIGH DESKEW – ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure deserializer uses the right clock edge. See Capture Test Patterns for details. Table 6. SEN Control Pin SEN 0 DESCRIPTION External reference and 0 dB coarse gain (full-scale = 2 VPP) (3/8)LVDD External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP) (5/8)LVDD Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP) LVDD Internal reference and 0 dB coarse gain (full-scale = 2 VPP) Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will automatically configure the device as per the voltage applied (refer to Table 7 to Table 11). Table 7. PDN Control Pin PDN 0 AVDD DESCRIPTION Normal operation Power down global Table 8. CFG1 Control Pin CFG1 DESCRIPTION 0 (default) + 200mV DDR Bit clock and 1-wire interface (3/6) LVDD +/- 200mV Not used (5/6) LVDD +/- 200mV SDR Bit clock and 2-wire interface LVDD - 200mV DDR Bit clock and 2-wire interface Table 9. CFG2 Control Pin CFG2 DESCRIPTION 0 (default) + 200mV 14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode) (3/6) LVDD +/- 200mV 16x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode) (5/6) LVDD +/- 200mV 16x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode) LVDD - 200mV 14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode) Table 10. CFG3 Control Pin CFG3 RESERVED - TIE TO GROUND Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442 15 ADS6445, ADS6444 ADS6443, ADS6442 SLAS531B – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Table 11. CFG4 Control Pin CFG4 DESCRIPTION 0 (default) + 200mV MSB First and 2s complement (3/6) LVDD +/- 200mV MSB First and offset binary (5/6) LVDD +/- 200mV LSB First and offset binary LVDD - 200mV LSB First and 2s complement SERIAL INTERFACE The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with non-50% duty cycle SCLK. The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data. Register Reset After power-up, the internal registers must be reset to their default values. This can be done in one of two ways: 1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR 2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets the registers to their default values and then self-resets the <RST> bit to LOW. When RESET pin is not used, it must be tied to LOW. 16 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS6445, ADS6444 ADS6443, ADS6442