TI ADS5546IRGZRG4

ADS5546
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
•
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Maximum Sample Rate: 190 MSPS
14-Bit Resolution
No Missing Codes
Total Power Dissipation 1.1 W
Internal Sample and Hold
73.2-dBFS SNR at 70-MHz IF
87-dBc SFDR at 70-MHz IF, 0 dB gain
Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR
Trade-Off at High IF
Reduced Power Modes at Lower Sample
Rates
Supports input clock amplitude down to 400
mVPP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock position to ease
data capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
APPLICATIONS
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Wireless Communications Infrastructure
Software Defined Radio
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Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
DESCRIPTION
ADS5546 is a high performance 14-bit, 190-MSPS
A/D converter. It offers state-of-the art functionality
and performance using advanced techniques to
minimize board space. Using an internal sample and
hold and low jitter clock buffer, the ADC supports
both high SNR and high SFDR at high input
frequencies. It features programmable gain options
that can be used to improve SFDR performance at
lower full-scale analog input ranges.
In a compact 48-pin QFN, the device offers fully
differential LVDS DDR (Double Data Rate) interface
while parallel CMOS outputs can also be selected.
Flexible output clock position programmability is
available to ease capture and trade-off setup for hold
times. At lower sampling rates, the ADC can be
operated at scaled down power with no loss in
performance. ADS5546 includes an internal
reference, while eliminating the traditional reference
pins and associated external decoupling. The device
also supports an external reference mode.
The device is specified over
temperature range (-40°C to 85°C).
the
industrial
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
ADS5546
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
CLKP
DRGND
DRVDD
AGND
AVDD
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
CLKOUTP
CLOCKGEN
CLKM
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Digital
Encoder
and
Serializer
INP
14-Bit
ADC
SHA
INM
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
VCM
Control
Interface
Reference
D12_D13_P
D12_D13_M
OVR
MODE
OE
DFS
RESET
SEN
SDATA
SCLK
IREF
ADS5546
LVDS MODE
B0095-01
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
ADS5546
QFN-48 (2)
(1)
(2)
2
PACKAGE
DESIGNATOR
RGZ
SPECIFIED
TEMPERATURE
RANGE
–40°C to 85°C
PACKAGE
MARKING
AZ5546
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS5546IRGZT
Tape and Reel,
250
ADS5546IRGZR
Tape and Reel,
2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 25.41°C/W (0 LFM air flow), θJC
= 16.5°C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in x 3 in PCB.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Supply voltage range, AVDD
–0.3 V to 3.9
V
Supply voltage range, DRVDD
–0.3 V to 3.9
V
Voltage between AGND and DRGND
-0.3 to 0.3
V
Voltage between AVDD to DRVDD
-0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
-0.3 to 1.8
V
–0.3 V to minimum (3.6, AVDD + 0.3 V)
V
Voltage applied to analog input pins, INP and INM
Voltage applied to input clock pins, CLKP and CLKM
TA
Operating free-air temperature range
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
-0.3 V to AVDD + 0.3 V
V
–40 to 85
°C
125
°C
–65 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
Analog supply voltage, AVDD
3
3.3
3.6
V
Digital supply voltage, DRVDD
3
3.3
3.6
V
SUPPLIES
ANALOG INPUTS
Differential input voltage range
2
VPP
1.5 ±0.1
Input common-mode voltage
Voltage applied on VCM in external reference mode
1.45
1.5
V
1.55
V
50
190
MSPS
1
60
CLOCK INPUT
Input clock sample rate
DEFAULT SPEED mode
LOW SPEED mode
Input clock amplitude differential (V(CLKP) - V(CLKM))
Sine wave, ac-coupled
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
3.3
V
Input clock duty cycle (See Figure 34)
0.4
35%
50%
65%
DIGITAL OUTPUTS
CL
Maximum external load capacitance from each output pin to DRGND (LVDS and
CMOS modes)
RL
Differential load resistance between the LVDS output pairs (LVDS mode)
Operating free-air temperature
5
Ω
100
–40
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pF
85
°C
3
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SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
UNIT
14
bits
Differential input voltage range
2
VPP
Differential input capacitance
7
pF
ANALOG INPUT
Analog input bandwidth
–3 dB, source impedance 50 Ω
Analog input common mode current
(per input pin)
500
MHz
310
µA
REFERENCE VOLTAGES
V(REFB)
Internal reference bottom voltage
Internal reference mode
0.5
V
V(REFT)
Internal reference top voltage
Internal reference mode
2.5
V
VCM
Common mode output voltage
Internal reference mode
1.5
V
VCM output current capability
Internal reference mode
±4
mA
DC ACCURACY
No Missing Codes
DNL
Differential non-linearity
INL
Integral non-linearity
Specified
Offset error
0.5
2.5
LSB
–5
±3
5
LSB
5
Offset temperature coefficient
mV
0.002
ppm/°C
±1
Gain error
Gain temperature coefficient
PSRR
–0.9
DC Power supply rejection ratio
%FS
0.01
∆%/°C
0.6
mV/V
POWER SUPPLY
I(AVDD)
I(DRVDD)
ICC
4
Analog supply current
Digital supply current
291
mA
LVDS mode, IO = 3.5 mA,
RL = 100 Ω, CL = 5 pF
51
mA
CMOS mode, FIN = 2.5 MHz,
CL = 5 pF
43
mA
mA
Total supply current
LVDS mode
342
Total power dissipation
LVDS mode
1.13
1.29
W
Standby power
In STANDBY mode with clock
running
100
150
mW
Clock stop power
With input clock stopped
100
150
mW
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
FIN = 10 MHz
73.8
FIN = 40 MHz
73.6
FIN = 70 MHz
SNR
Signal to noise ratio
73
FIN = 150 MHz
72.2
FIN = 300 MHz
0 dB gain, 2 VPP FS (1)
71
3 dB gain, 1.4 VPP FS
69.8
0 dB gain, 2 VPP FS
69
Inputs tied to common-mode
1.1
FIN = 10 MHz
90
77
FIN = 100 MHz
FIN = 300 MHz
84
0 dB gain, 2 VPP FS
75
3 dB gain, 1.4 VPP FS
78
0 dB gain, 2 VPP FS
72
3 dB gain, 1.4 VPP FS
73.5
FIN = 40 MHz
73.1
FIN = 70 MHz
71
FIN = 100 MHz
Signal to noise and distortion ratio
FIN = 300 MHz
71.8
0 dB gain, 2 VPP FS
Second harmonic
68.5
0 dB gain, 2 VPP FS
67.8
3 dB gain, 1.4 VPP FS
67.5
FIN = 10 MHz
92
FIN = 40 MHz
91
90
89
FIN = 150 MHz
87
FIN = 300 MHz
(1)
77
FIN = 100 MHz
FIN = 225 MHz
dBFS
69
3 dB gain, 1.4 VPP FS
FIN = 70 MHz
HD2
72.8
72.1
FIN = 150 MHz
FIN = 225 MHz
dBc
75
FIN = 10 MHz
SINAD
87
84
FIN = 150 MHz
FIN = 225 MHz
LSB
89
FIN = 70 MHz
Spurious free dynamic range
dBFS
70
3 dB gain, 1.4 VPP FS
FIN = 40 MHz
SFDR
73.5
FIN = 100 MHz
FIN = 225 MHz
RMS output noise
71.5
0 dB gain, 2 VPP FS
76
3 dB gain, 1.4 VPP FS
79
0 dB gain, 2 VPP FS
73
3 dB gain, 1.4 VPP FS
75
dBc
FS = Full scale range
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 190 MSPS, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0dB gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
FIN = 10 MHz
84
84
0 dB gain, 2 VPP FS
75
3 dB gain, 1.4 VPP FS
78
0 dB gain, 2 VPP FS
72
3 dB gain, 1.4 VPP FS
74
FIN = 10 MHz
93
FIN = 40 MHz
92
FIN = 70 MHz
91
FIN = 100 MHz
90
FIN = 150 MHz
89
FIN = 225 MHz
87
FIN = 300 MHz
87
FIN = 10 MHz
85
FIN = 40 MHz
85
FIN = 70 MHz
THD
Total harmonic distortion
IMD
PSRR
6
Effective number of bits
Two-tone intermodulation distortion
75
81
FIN = 150 MHz
80
FIN = 225 MHz
72
FIN = 10 MHz
FIN1 = 50.09 MHz, FIN2 = 46.09 MHz, -7 dBFS
each tone
dBc
dBc
83
FIN = 100 MHz
FIN = 300 MHz
ENOB
87
FIN = 150 MHz
FIN = 300 MHz
Worst harmonic (other than HD2, HD3)
77
FIN = 100 MHz
FIN = 225 MHz
UNIT
89
FIN = 70 MHz
Third harmonic
MAX
90
FIN = 40 MHz
HD3
TYP
dBc
68
11.8
bits
95
dBFS
FIN1 = 135.08 MHz, FIN2 = 130.08 MHz, -7 dBFS
each tone
89
AC power supply rejection ratio
30 MHz, 200 mVPP signal on 3.3-V supply
35
dBc
Voltage overload recovery time
Recovery to 1% (of final value) for 6-dB overload
with sine-wave input at Nyquist frequency
1
Clock
cycles
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DIGITAL CHARACTERISTICS
(1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
33
µA
Low-level input current
–33
µA
4
pF
High-level output voltage
3.3
V
Low-level output voltage
0
V
2
pF
1375
mV
1025
mV
350
mV
1200
mV
2
pF
Input capacitance
DIGITAL OUTPUTS – CMOS MODE
Output capacitance
Output capacitance inside the device, from each output to
ground
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage
Low-level output voltage
Output differential voltage, |VOD|
225
VOS Output offset voltage, single-ended
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either output to
ground
(1)
(2)
All LVDS and CMOS specifications are characterized, but not tested at production.
IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, sampling frequency = 190 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA,
RL = 100 Ω (3), no internal termination, unless otherwise noted.
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ta
Aperture delay
1.2
ns
tj
Aperture jitter
150
fs rms
Wake-up time
Time to valid data after coming out of
STANDBY mode
100
Time to valid data after stopping and restarting
the input clock
100
µs
Latency
14
clock
cycles
DDR LVDS MODE (4)
Data setup time (5)
Data valid
1.2
1.7
ns
th
Data hold time (5)
Zero-cross of CLKOUTP to data becoming
invalid (6)
0.4
0.9
ns
tPDI
Clock propagation delay
Input clock rising edge zero-cross to output
clock rising edge zero-cross
4
4.7
tsu
(1)
(2)
(3)
(4)
(5)
(6)
(6)
to zero-cross of CLKOUTP
5.4
ns
Timing parameters are specified by design and characterization and not tested in production.
CL is the effective external single-ended load capacitance between each output pin and ground.
IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margin.
Data valid refers to logic high of +50 mV and logic low of –50 mV.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
45%
50%
55%
UNIT
LVDS bit clock duty cycle
Duty cycle of differential clock,
(CLKOUTP-CLKOUTM)
80 ≤ Fs ≤ 190 MSPS
tr ,
tf
Data rise time,
Data fall time
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 190 MSPS
50
100
200
ps
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 190 MSPS
50
100
200
ps
tOE
Output enable (OE) to valid data
delay
Time to valid data after OE becomes active
1
µs
PARALLEL CMOS MODE
tsu
(5)
(5)
Data valid (7) to 50% of CLKOUT rising edge
2.2
3
ns
50% of CLKOUT rising edge to data becoming
invalid (7)
0.5
0.9
ns
2.4
3.2
th
Data hold time
tPDI
Clock propagation delay
Input clock rising edge zero-cross to 50% of
CLKOUT rising edge
Output clock duty cycle
Duty cycle of output clock (CLKOUT)
80 ≤ Fs ≤ 190 MSPS
tr,
tf
Data rise time,
Data fall time
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 190 MSPS
0.8
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of
DRVDD
Fall time measured from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 190 MSPS
0.4
tOE
Output enable (OE) to valid data
delay
Time to valid data after OE becomes active
(7)
8
Data setup time
Data valid refers to logic high of 2 V and logic low of 0.8 V
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4
ns
1.5
2
ns
0.8
1.2
ns
50
ns
45%
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N+4
N+3
N+2
N+1
Sample
N
N+17
N+16
N+15
N+14
Input
Signal
ta
Input
Clock
CLKP
CLKM
CLKOUTM
CLKOUTP
tsu
Output Data
DXP, DXM
E
E
O
E – Even Bits D0,D2,D4,D6,D8,D10,D12
O – Odd Bits D1,D3,D5,D7,D9,D11,D13
O
N–14
E
O
N–13
E
E
O
N–12
tPDI
th
14 Clock Cycles
DDR
LVDS
E
O
N–11
E
O
N–10
O
E
O
N
N–1
E
E
O
O
N+2
N+1
tPDI
CLKOUT
tsu
Parallel
CMOS
14 Clock Cycles
Output Data
D0–D13
N–13
N–14
N–12
th
N–11
N–10
N
N–1
N+1
N+2
Figure 1. Latency
Input
Clock
CLKM
CLKP
tPDI
Output
Clock
CLKOUTP
CLKOUTM
tsu
th
tsu
Output
Data Pair
(1)
(2)
Dn
Dn_Dn+1_P,
Dn_Dn+1_M
th
Dn
(1)
Dn+1
(2)
– Bits D0, D2, D4, D6, D8, D10, D12
Dn+1 – Bits D1, D3, D5, D7, D9, D11, D13
T0106-01
Figure 2. LVDS Mode Timing
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CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
th
tsu
Output
Data
Dn
Dn
(1)
(1)
Dn – Bits D0–D13
T0107-01
Figure 3. CMOS Mode Timing
10
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DEVICE PROGRAMMING MODES
ADS5546 offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either a parallel interface control or a serial interface
programming.
In addition, the device supports a third mode, where both the parallel interface and the serial control registers
are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority table
(Table 2). If this additional level of flexibility is not required, the user can select either the serial interface
programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using the parallel interface, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,
SCLK, and SDATA are used to directly control certain modes of the ADC. The device is configured by
connecting the parallel pins to the correct voltage levels (as described in Table 4 to Table 7). There is no need
to apply reset.
In this mode, SEN, SCLK, and SDATA function as parallel interface control pins. Frequently used functions are
controlled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,
two's complement/straight binary output format, and position of the output clock edge.
Table 1 has a description of the modes controlled by the four parallel pins.
Table 1. Parallel Pin Definition
PIN
DFS
MODE
CONTROL MODES
DATA FORMAT and the LVDS/CMOS output interface
Internal or external reference
SEN
CLKOUT edge programmability
SCLK
LOW SPEED mode control for low sampling frequencies (< 50 MSPS)
SDATA
STANDBY mode – Global (ADC, internal references and output buffers are powered down)
USING SERIAL INTERFACE PROGRAMMING ONLY
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the
register programming and register reset in more detail.
Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can
also be used to configure the device.
The serial registers must first be reset to their default values, and the RESET pin must be kept low. In this mode
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 in
register 0x6C). The serial interface section describes the register programming and register reset in more detail.
The parallel interface control pins DFS and MODE are used, and their function is determined by the appropriate
voltage levels as described in Table 6 and Table 7. The voltage levels are derived by using a resistor string as
illustrated in Figure 4. Since some functions are controlled using both the parallel pins and serial registers, the
priority between the two is determined by a priority table (Table 2).
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Table 2. Priority Between Parallel Pins and Serial Registers
PIN
MODE
FUNCTIONS SUPPORTED
PRIORITY
Internal/External reference
When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLY
if the MODE pin is tied low.
DATA FORMAT
When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY if
the DFS pin is tied low.
LVDS/CMOS
When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOS
selection independent of the state of DFS pin
DFS
AVDD
(2/3) AVDD
R
(2/3) AVDD
GND
R
AVDD
(1/3) AVDD
(1/3) AVDD
R
To Parallel Pin
Figure 4. Simple Scheme to Configure Parallel Pins
12
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DESCRIPTION OF PARALLEL PINS
Table 3. SCLK Control Pin
SCLK (Pin 29)
0
DRVDD
DESCRIPTION
DEFAULT SPEED - Must be used for sampling frequency > 50 MSPS
LOW SPEED - Must be used for sampling frequency <= 50 MSPS
Table 4. SDATA Control Pin
SDATA (Pin 28)
0
DRVDD
DESCRIPTION
Normal operation (Default)
STANDBY. This is a global power down, where ADC, internal references and the output buffers are powered down.
Table 5. SEN Control Pin
SEN (Pin 27)
CMOS mode: CLKOUT edge later by (3/12)Ts
(1);
LVDS mode: CLKOUT edge aligned with data transition
(1/3)DRVDD
CMOS mode: CLKOUT edge later by (2/12)Ts
(1);
LVDS mode: CLKOUT edge aligned with data transition
(2/3)DRVDD
CMOS mode: CLKOUT edge later by (1/12)Ts
(1);
LVDS mode: CLKOUT edge earlier by (1/12)Ts
DRVDD
(1)
DESCRIPTION
0
(1)
Default CLKOUT position
Ts = 1/Sampling Frequency
Table 6. DFS Control Pin
DFS (Pin 6)
0
DESCRIPTION
2's complement data and DDR LVDS output (Default)
(1/3)DRVDD
2's complement data and parallel CMOS output
(2/3)DRVDD
Offset binary data and parallel CMOS output
DRVDD
Offset binary data and DDR LVDS output
Table 7. MODE Control Pin
MODE (Pin 23)
DESCRIPTION
0
Internal reference
(1/3)AVDD
External reference
(2/3)AVDD
External reference
AVDD
Internal reference
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits form the register data.
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REGISTER INITIALIZATION
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as
shown in Figure 5.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit (D1 in register 0x6C) to high. This
initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case
the RESET pin is kept low.
Register Address
SDATA
A7
A6
A5
A4
A3
A2
Register Data
A1
A0
D7
t(SCLK)
D6
D5
D4
D3
D2
D1
D0
t(DH)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-01
Figure 5. Serial Interface Timing Diagram
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN
tSCLK
SCLK period
TYP
50
SCLK duty cycle
MAX
UNIT
ns
50%
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
14
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RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
MIN
t2
Reset pulse width
t3
tPO
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay
Delay from RESET disable to SEN active
25
ns
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
T0108-01
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
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DESCRIPTION OF SERIAL REGISTERS
Table 8 gives a summary of all the modes that can be programmed through the serial interface.
Table 8. Serial Interface Register Map
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
D2
D1
DESCRIPTION
D0
<STBY> – Global Power Down
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
NORMAL converter operation (Default after
reset)
0
0
0
0
0
0
STANDBY
1
0
Resets all registers to default values
<RST> – Software Reset
0
1
1
0
1
1
0
0
0
0
0
0
0
0
<DF> – Output Data Format
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
2's complement output format (Default after
reset)
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
Straight binary output format
<ODI> – Output Data Interface
0
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
DDR LVDS outputs (D4:D3 defaults to 00
after reset)
0
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
Parallel CMOS outputs
<REF> –Internal/External reference mode
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
Internal reference (Default after reset)
0
1
1
0
1
1
0
1
0
0
0
1
0
0
0
0
External reference – Force voltage on VCM
pin
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Normal operation (Default after reset)
0
1
1
0
0
1
0
1
0
0
1
0
0
0
0
0
All zeros
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
All ones
0
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
Toggle pattern Alternate 1s and 0s on each
data output and across the data outputs.
0
1
1
0
0
1
0
1
1
0
0
0
0
0
0
0
Ramp pattern – Output data ramps from
0x0000 to 0x3FFF every clock cycle
0
1
1
0
0
1
0
1
1
0
1
0
0
0
0
0
Custom pattern. Write the custom pattern in
CUSTOM PATTERN registers A and B.
0
1
1
0
0
1
0
1
X
X
X
0
0
0
0
0
NOT USED
<TEST PATTERN> – Output test pattern on data outputs
<CUSTOM PATTERN> – Output custom pattern on data outputs
0
1
1
0
1
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0 CUSTOM PATTERN D7-D0
0
1
1
0
1
0
1
0
0
0
D13
D12
D11
D10
D9
D8 CUSTOM PATTERN D13-D8
<CLK GAIN> – Clock Buffer gain programmability, Gain decreases monotonically from Gain 4 to Gain 0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
0
Gain 4
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
Gain 3
0
1
1
0
1
0
1
1
0
0
1
0
0
1
1
0
Gain 2
0
1
1
0
1
0
1
1
0
0
1
0
0
0
0
0
Gain 1 (Default after reset)
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
Gain 0 Minimum gain
<POWER SCALING> Power scaling vs sampling frequency. The ADC can be operated at reduced power at lower sampling rates
with no loss in performance.
16
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
0
Default Fs > 150 MSPS (Default after reset)
0
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
Power Mode 1 – 105 < Fs ≤ 150 MSPS
0
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
Power Mode 2 – 50 < Fs ≤ 105 MSPS
0
1
1
0
1
1
0
1
1
1
1
0
0
0
0
0
Power Mode 3 – Fs ≤ 50 MSPS
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Table 8. Serial Interface Register Map (continued)
REGISTER ADDRESS
A7
A6
A5
A4
A3
A2
REGISTER DATA
A1
A0
D7
D6
D5
D4
D3
D2
D1
DESCRIPTION
D0
<GAIN> Gain programming - Channel gain can be programmed from 0 to 6 dB for SFDR/SNR trade-off. For each gain setting, the
input full-scale range has to be proportionally scaled. For 6 dB gain, the full-scale range will be 1 VPP compared to 2 VPP at 0 dB
gain.
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0 dB (Default after reset)
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
2 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
1
3 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
0
4 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
1
5 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
6 dB
<LVDS CURRENT> – LVDS Output data and clock buffers nominal current programmability
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
3.5 mA (Default after reset)
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
2.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
4.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1.75 mA
<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>
register.
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
value specified by <LVDS CURRENT>
(Default after reset)
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
2x data, 2x clock currents
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1x data, 2x clock currents
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2x data, 4x clock currents
<DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination (Default after reset)
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
325 Ω
0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
200 Ω
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
125 Ω
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
170 Ω
0
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
120 Ω
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
100 Ω
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
75 Ω
<CLK TERM> Internal termination - Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination (Default after reset)
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
325 Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
200 Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
125 Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
170 Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
120 Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
100 Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
75 Ω
<CLK