G576 Global Mixed-mode Technology Inc. Dual-Slot PCMCIA/CardBus Power Controllers Features Description Fully Integrated VCC and VPP Switching for The G576 PC Card power-interface switch provides an integrated power-management solution for dual-slot PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit. The circuit allows the distribution of 3.3V, 5V, and/or 12V card power, and is compatible with many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. Dual-Slot PC CardTM Interface Low rDS(on) (180-mΩ Ω 5V VCC Switch and 3.3V VCC Switch) 3.3V Low-Voltage Mode Meets PC Card Standards 12V Supply Can Be Disabled Except During 12V Flash Programming Short Circuit and Thermal Protection 28 Pin SSOP Compatible With 3.3V, 5V, and 12V PC Cards Break-Before-Make Switching The G576 features a 3.3V low voltage mode that allows for 3.3V switching without the need for 5V. Bias power can be derived from either the 3.3V or 5V inputs. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3V is available. Application Notebook PC Electronic Dictionary Personal Digital Assistance Digital still Camera End equipment for the G576 includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras and bar-code scanners. Ordering Information PART NUMBER TEMP. RANGE PACKAGE G576 -40°C to +85°C 28-SSOP Pin Configuration G576 AVCC 1 28 AVCC AVPPD1 2 27 AVPP AVPPD0 3 26 VCC12 ASHDN 4 25 AOC AVCCD0 5 6 24 GND AVCCD1 23 VCC5 VCC3 7 22 VCC5 VCC5 8 21 VCC3 VCC5 9 20 BVCCD1 GND 10 19 BVCCD0 BOC VCC12 11 18 BSHDN 12 17 BVPPD0 BVPP 13 16 BVPPD1 BVCC 14 15 BVCC 28Pin SSOP Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 1 G576 Global Mixed-mode Technology Inc. Typical PC-card Power-distribution application AVCC AVCC 0.1µF VCC1 VCC2 VPP1 AVCCD0 AVCCD1 AVPPD0 AVPPD1 BVCCD0 BVCCD1 BVPPD0 BVPPD1 PCMCIA Controller VPP2 AVPP 0.1µF BVCC BVCC 0.1µF VCC1 VCC2 VPP1 From CPU From CPU ASHDN G576 0.1µF 1µF 0.1µF BSHDN VCC12 VCC5 5V 1µF 0.1µF PC Card Connector B VPP2 BVPP VCC12 12V PC Card Connector A AOC To CPU BOC To CPU VCC5 VCC5 VCC5 VCC3 3.3V 0.1µF 1µF VCC3 GND GND Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AVCC AVPPD1 AVPPD0 ASHDN 1,28 2 3 4 O I I I Switched output that delivers 0V, 3.3V, 5V, or high impedance to card Logic input that controls voltage of AVPP (see control-logic table) Logic input that controls voltage of AVPP (see control-logic table) Logic input that shuts down AVPP/AVCC and sets AVPP/AVCC to high-impedance state AVCCD0 5 I Logic input that controls voltage of AVCC (see control-logic table) AVCCD1 6 I Logic input that controls voltage of AVCC (see control-logic table) VCC3 7,21 I 3.3V VCC input for card power and/or chip power if 5V is not present VCC5 GND I BOC 8,9,22,23 10,24 11 5V VCC input for card power and/or chip power Ground Logic-level overcurrent reporting output that goes low when an overcurrent condition exists VCC12 12,26 I 12V VPP input card power BVPP BVCC BVPPD1 BVPPD0 13 14,15 16 17 O O I I Switched output that delivers 0V, 3.3V, 5V, 12V or high impedance to card Switched output that delivers 0V, 3.3V, 5V, or high impedance to card Logic input that controls voltage of BVPP (see control-logic table) Logic input that controls voltage of BVPP (see control-logic table) BSHDN 18 I Logic input that shuts down BVPP/BVCC and set BVPP/BVCC to high-impedance state BVCCD0 19 I Logic input that controls voltage of BVCC (see control-logic table) BVCCD1 20 I Logic input that controls voltage of BVCC (see control-logic table) AOC 25 O Logic-level overcurrent reporting output that goes low when an overcurrent condition exists AVPP 27 O Switched output that delivers 0V, 3.3V, 5V, 12V or high impedance to card O Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 2 G576 Global Mixed-mode Technology Inc. Absolute Maximum Ratings Over Operating Free-Air Temperature (unless other-wise noted)* Operating free-air temperature range,.TA ……………………………………………………………..……………..-40°C to 85°C Storage temperature range, TSTG ………………………...........….....……….-55°C to 150°C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds.……..………………………………...….260°C Thermal resistance θJA SSOP 28……………………………………….….125°C/W Power dissipation PD (TA ≤ +25°C) SSOP 28……………………………………………800mW ESD…………………………..…………………….…Note1 Input voltage range for card power: VCC5.......................................………..…….-0.3V to 7V VCC3.....…...........................…….……... -0.3V to 7V VCC12.....................................……..…….-0.3V to 14V Logic input voltage...................….........…….-0.3V to 7V Output current (each card):IO (AVCC/BVCC)..internally limited IO(AVPP/BVPP)..…internally limited Operating virtual junction temperature range, TJ. .........…............……………..…….………-40°C to 150°C *Stresses beyond those listed under "absolute maximum ratings”may cause permanent damage to the device. These are stress rating only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions”is not implied. Exposure to absolute–maximum-rated conditions for extended periods may affect device reliability. Note 1: ESD (electrostatic discharge) sensitive device. Proper ESD precautions are recommended to avoid performance degradation or less of functionality. Recommended Operating Conditions Input voltage, VI Output current MIN MAX UNIT VCC5 0 5.25 V VCC3 VCC12 IO (AVCC/BVCC) IO (AVPP/BVPP) 0 0 5.25 13.5 1.0 150 V V A mA -40 125 °C Operating virtual junction temperature, TJ Electrical Characteristics (TA=25°C) Power Switch PARAMETER Switch resistance 5V to AVCC/BVCC 3.3V to AVCC/BVCC 3.3V to AVCC/BVCC 5V to AVPP/BVPP 3.3V to AVPP/BVPP 12V to AVPP/BVPP VO (AVPP/BVPP) Clamp low voltage VO (AVCC/BVCC) Clamp low voltage IOS MIN TYP MAX UNIT 130 130 130 3.6 180 180 180 6 TJ = 25°C TJ = 25°C IPP at 10mA ICC at 10mA 3.4 1.2 0.18 0.13 6 6 0.8 0.8 Input current I PP high-impedance State I CC high-impedance State VCC5 = 5V VCC5= 0V, VCC3 = 3.3V TA = 25°C TA = 25°C VO (AVCC/BVCC)=5V, VO (AVPP/BVPP)=12V VO (AVCC/BVCC)=3.3V, VO (AVPP/BVPP)=12V 1 1 75 75 10 10 150 150 VO (AVCC/BVCC)=VO (AVPP/BVPP)= Hi-Z Output powered into a short to GND 1 Short-circuit Outputcurrent Limit Shutdown mode IO(AVCC/BVCC) IO(AVPP/BVPP) 3 2.2 400 IIKG Leakage current II TEST CONDITIONS* VCC5 = 5V VCC5 = 5V, VCC3 =3.3V VCC5 = 0V, VCC3 =3.3V TJ = 25°C 0.8 120 mΩ Ω V V µA µA A mA *Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately. Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 3 G576 Global Mixed-mode Technology Inc. Logic Section PARAMETER TEST CONDITION* MIN Logic input current Logic input high level Logic input low level MAX 1 µA V V 2 0.8 VCC5=5V, IO=1mA VCC5=0V, IO=1mA, VCC3=3.3V IO=1mA Logic output high level Logic output low level UNIT VCC5 -0.4 VCC3 -0.4 V 0.4 V *Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately. Switching Characteristics ** PARAMETER tr Rise times, output tf Fall times, output TEST CONDITION MIN TYP VO (AVCC/BVCC) VO (AVPP/BVPP) VO (AVCC/BVCC) VO (AVPP/BVPP) VI (AVPPD0/BVPPD0) to VO (AVPP/BVPP) tpd Propagation delay (see Figure 1) VI ( AVCCD1 / BVCCD1 ) to VO (AVCC/BVCC) (3.3V) VI ( AVCCD0 / BVCCD0 ) to VO (AVCC/BVCC) (5V) MAX UNIT 2.6 10 7.5 38 14 44 3.2 17 4.4 20 ton toff ton toff ton toff ms ms **Switching Characteristics are with CL = 147µF. § Refer to Parameter Measurement Information Parameter Measurement Information AVCC AVPP CL CL LOAD CIRCUIT V I(VPPD0) LOAD CIRCUIT V DD 50% V I(VCCD1) 50% (V I(VPPD1)=0V) (V I(VCCD0)=V DD) GND toff V DD 50% 50% GND toff ton ton V I(12V) V O(AVPP) V I(3.3V) V O(AVCC) 90% 10% 90% 10% GND VOLTAGE WAVEFORMS GND VOLTAGE WAVEFORMS Figure 1. Test Circuits and Voltage Waveforms Table of Timing Diagrams FIGURE AVCC/BVCC Propagation Delay and Rise Time With 1µF Load, 3.3V Switch AVCC/BVCC Propagation Delay and Fall Time With 1µF Load, 3.3V Switch AVCC/BVCC Propagation Delay and Rise Time With 147µF Load, 3.3V Switch AVCC/BVCC Propagation Delay and Fall Time With 147µF Load, 3.3V Switch AVCC/BVCC Propagation Delay and Rise Time With 1µF Load, 5V Switch AVCC/BVCC Propagation Delay and Fall Time With 1µF Load, 5V Switch AVCC/BVCC Propagation Delay and Rise Time With 147µF Load, 5V Switch AVCC/BVCC Propagation Delay and Fall Time With 147µF Load, 5V Switch AVPP/BVPP Propagation Delay and Rise Time With 1µF Load, 12V Switch AVPP/BVPP Propagation Delay and Fall Time With 1µF Load, 12V Switch AVPP/BVPP Propagation Delay and Rise Time With 147µF Load, 12V Switch AVPP/BVPP Propagation Delay and Fall Time With 147µF Load, 12V Switch Ver: 1.0 Jan 23, 2003 2 3 4 5 6 7 8 9 10 11 12 13 TEL: 886-3-5788833 http://www.gmt.com.tw 4 Global Mixed-mode Technology Inc. G576 Parameter Measurement Information V C C D 0 = 3.3 V V C C D 0 = 3 .3 V VCCD1 VCCD1 AV C C AV C C Figure 2. AVCC/BVCC Propagation Delay and Rise Time With 1µF Load, 3.3V Switch Figure 3. AVCC/BVCC Propagation Delay and Fall Time With 1µF Load, 3.3V Switch V C C D 0 = 3 .3 V V C C D 0 = 3 .3 V VCCD1 VCCD1 AV C C AV C C Figure 4. AVCC/BVCC Propagation Delay and Rise Time With 147µF Load, 3.3V Switch Figure 5. AVCC/BVCC Propagation Delay and Fall Time With 147µF Load, 3.3V Switch Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 5 Global Mixed-mode Technology Inc. VCCD0 G576 VCCD0 VCCD1=5V VCCD1=5V AVCC AVCC Figure 6. AVCC/BVCC Propagation Delay and Rise Time With 1µF Load, 5V Switch Figure 7. AVCC/BVCC Propagation Delay and Fall Time With 1µF Load, 5V Switch VCCD0 VCCD0 VCCD1=5V VCCD1=5V AVCC AVCC Figure 8. AVCC/BVCC Propagation Delay and Rise Time with 147µF Load, 5V Switch Figure 9. AVCC/BVCC Propagation Delay and Fall Time with 147µF Load, 5V Switch Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 6 Global Mixed-mode Technology Inc. VPPD0 G576 VPPD0 VPPD1=0V VPPD1=0V AVPP AVPP Figure 10. AVPP/BVPP Propagation Delay and Rise Time With 1µF Load, 12V Switch Figure 11. AVPP/BVPP Propagation Delay and Fall Time With 1µF Load, 12V Switch VPPD0 VPPD0 VPPD1=0V VPPD1=0V AVPP AVPP Figure 13. AVPP/BVPP Propagation Delay and Fall Time With 147µF Load, 12V Switch Figure 12. AVPP/BVPP Propagation Delay and Rise Time With 147µF Load, 12V Switch Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 7 Global Mixed-mode Technology Inc. Application Information G576 temperature range. Using the same equations, the PCMCIA specification for output voltage regulation of the 3.3V output is 300mV. Using the voltage drop percentages for power supply regulation (2%) and PCB resistive loss (1%), the allowable voltage drop for the 3.3V switch is 200mV. The 12V outputs AVPP/BVPP of the G576 can deliver 150mA continuously. Overview PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with limited onboard memory. The idea of add-in cards quickly took hold; modems, wireless LANs, Global Positioning Satellite (GPS) systems, multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International Association) was established, comprised of members from leading computer, software, PC Card, and semiconductor manufactures. One key goal was to realize the “plug and play” concept, i.e. cards and hosts from different vendors should be compatible. Overcurrent and overtemperature protection PC Cards are inherently subuect to damage from mishandling. Host systems require protection against short-circuited cards that could lead to power supply or PCB trace damage. Even systems sufficiently robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card, resulting in a sudden loss of system power. Most hosts include fuses for protection. The reliability of fused systems is poor, and requires troubleshooting and repair, usually by the manufacturer. When fuses are blown. PC Card Power Specification System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connectors. This power interface consists of two VCC, two VPP, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two VPP terminals were originally specified as separate signals but are commonly tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage is supplied through the VPP terminals. The G576 uses sense FETs to check for overcurrent conditions in each of the AVCC/BVCC and AVPP/ BVPP outputs.Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent condition is detected, only the power output affected is limited; all other power outputs continue to function normally. The AOC / BOC indicator, normally a ligic high, are a logic low when an overcurrent condition is detected providing for initiation of system diagnostics and/or sending a warning message to the user. During power up, the G576 controls the rise time of the AVCC/BVCC and AVPP/BVPP outputs and limits the current into a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card), current is initially limited only by the impedance between the short and the power supply. In extreme cases, as much as 10A to 15A may flow into the short before the current limiting of the G576 engages. If the AVCC/BVCC or AVPP/BVPP outputs are driven below ground, the G576 may latch nondestructively in an off state, Cycling power will reestablish normal operation. Designing for Voltage Regulation The current PCMCIA specification for output voltage regulation of the 5V output is 5% (250mV). In a typical PC power-system design, the power supply will have an output voltage regulation (VPS(reg)) of 2% (100mV). Also, a voltage drop from the power supply to the PC Card will result from resistive losses (VPCB) in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50mV) of the output voltage. Therefore, the allowable voltage drop (VDS) for the G576 would be the PCMCIA voltage regulation less the power supply regula-tion and less the PCB and connector resistive drops: VDS = VO(reg)-VPS(reg)-VPCB Overcurrent limiting for the AVCC/BVCC outputs is designed to activate if powered up into a short in the range of 0.8A to 2.2A, typically at about 1.5A. The AVPP/BVPP outputs limit from 120mA to 400mA, typically around 200mA. The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full shutdown of the supply. Shutdown occurs only during thermal limiting. Typically, this would leave 100mV for the allowable voltage drop across the G576. The voltage drop is the output current multiplied by the switch resistance of the G576. Therefore, the maximum output current that can be delivered to the PC Card in regulation is the allowable voltage drop across the G576 divided by the output switch resistance. Thermal limiting prevents destruction of the IC from overheating if the package power dissipation rating are exceeded. Thermal limiting disables power output until the device has cooled. IOmax = VDS / RDS(on) The AVCC/BVCC outputs deliver 1A continuous at 3.3V and 5.5V within regulation over the operating Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 8 Global Mixed-mode Technology Inc. 12V Supply Not Required Most PC Card switches use the externally supplied 12V to power gate drive and other chip functions, which require that power be present at all times. The G576 offers considerable power savings by using an internal charge pump to generate the required higher voltages from 5V input; Therefore, the external 12V supply can be disable except when needed for flash-memory functions, thereby extending battery lifetime. Do not ground the 12V switch inputs when the 12-V input is not used. Additional power savings are realized by the G576 during a software shutdown in which quiescent current drops to a maximum of 3µA. G576 subjected to any residual 5V charge. The G576 offer a selectable VCC and VPP ground state, in accordance with PCMCIA 3.3V/5V switching specifications. Output Ground Switches PC Card specification requires that AVCC/BVCC be discharged within 100 ms. PC Card resistance can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. Power Supply Considerations The G576 has multiple pins for each of its 3.3V, and 5V power inputs and for switched AVCC/BVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. it is recommended that all input and output power pins be paralleled for optimum operation. 3.3V Low Voltage Mode The G576 will operates in a 3.3V low voltage mode when 3.3V is only available input voltage (VCC5=0). This allows host and PC Cards to be operated in low-power 3.3V-only modes such as sleep modes or pager modes. Note that in these operation mode, the G576 will derive its bias current from the 3.3V input pin and only 3.3V can be delivered to the PC Card. To increase the noise immunity of the G576, the power supply inputs should be bypassed with a 1µF electrolytic or tantalum capacitor paralleled by a 0.047µF to 0.1µF ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1µF or larger, ceramic capacitor; doing so improves the immunity of the G576 to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the G576 and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similary, no pin should be taken below -0.3V. Voltage Transitioning Requirement PC Cards are migrating from 5V to 3.3V to minimize power consumption, optimize board space, and increase logic speeds. The G576 meets all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3V/5V systems by first powering the card with 5V, then polling it to determine its 3.3V compatibility. The PCMCIA specification requires that the capacitors on 3.3V-compatible cards be discharged to below 0.8V before applying 3.3V power. This function is a power reset and ensures that sensitive 3.3V circuitry is not Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 9 G576 Global Mixed-mode Technology Inc. G576 3.3V 3.3V 5V S1 Card A cs VCC1 S2 VCC2 S3 S4 5V S5 S6 cs 12V See Note A ASHDN BSHDN CPU VPP1 VPP2 AVPPD0 AVPPD1 AVCCD0 AVCCD1 Controller Thermal BVPPD0 BVPPD0 BVCCD0 BVCCD1 AOC BOC GND See Note A S10 cs 12V S11 5V 5V 3.3V 3.3V Card B VPP1 S12 S7 S8 S9 VPP2 VCC2 cs VCC1 Note : MOSFET switch S6/S10 has a back-gate diode from the source to the drain. Unused switch inputs should never be grounded. Figure 14. Internal Switching Matrix Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 10 G576 Global Mixed-mode Technology Inc. G576 Control Logic AVCC CONTROL SIGNALS ASHDN AVCCD1 AVCCD0 INTERNAL SWITCH SETTINGS S1 S2 S3 OUTPUT AVCC 1 0 0 CLOSED OPEN OPEN 0V 1 1 1 0 0 1 1 × 1 0 1 × OPEN OPEN CLOSED OPEN CLOSED OPEN OPEN OPEN OPEN CLOSED OPEN OPEN 3.3V 5V 0V Hi-Z AVPP ASHDN CONTROL SIGNALS AVPPD0 INTERNAL SWITCH SETTINGS S4 S5 S6 OUTPUT AVPP AVPPD1 1 1 1 0 0 1 0 1 0 CLOSED OPEN OPEN OPEN CLOSED OPEN OPEN OPEN CLOSED 0V AVCC* VPP (12V) 1 0 1 × 1 × OPEN OPEN OPEN OPEN OPEN OPEN Hi-Z Hi-Z * Output depends on AVCC BVCC CONTROL SIGNALS BVCCD0 INTERNAL SWITCH SETTINGS S7 S8 S9 OUTPUT BVCC BSHDN BVCCD1 1 0 0 CLOSED OPEN OPEN 0V 1 1 1 0 0 1 1 × 1 0 1 × OPEN OPEN CLOSED OPEN CLOSED OPEN OPEN OPEN OPEN CLOSED OPEN OPEN 3.3V 5V 0V Hi-Z BVPP BSHDN CONTROL SIGNALS BVPPD0 BVPPD1 INTERNAL SWITCH SETTINGS S10 S11 S12 OUTPUT BVPP 1 1 1 0 0 1 0 1 0 CLOSED OPEN OPEN OPEN CLOSED OPEN OPEN OPEN CLOSED 0V BVCC* VPP (12V) 1 0 1 × 1 × OPEN OPEN OPEN OPEN OPEN OPEN Hi-Z Hi-Z * Output depends on BVCC Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 11 G576 Global Mixed-mode Technology Inc. Package Information C L E1 E h x 45° θ D A2 A A1 0.004 C SEATING PLANE b e SYMBOL MIN. DIMENSION IN MM NOM. A MAX. MIN. DIMENSION IN INCH NOM. 2.0 MAX. 0.079 A1 0.05 A2 1.65 1.75 1.85 0.065 0.069 0.073 b 0.22 0.30 0.33 0.009 0.012 0.013 c 0.09 0.15 0.21 0.004 0.006 0.008 e 0.002 0.65 BASIC D 9.90 10.20 0.026 BASIC 10.50 0.390 0.402 0.413 E 7.40 7.80 8.20 0.291 0.307 0.323 E1 5.00 5.30 5.60 0.197 0.209 0.220 L θ 0.55 0.75 0.95 0.022 0.030 0.038 0 4 8 0 4 8 JEDEC MO-150 (AH) Taping Specification Feed Direction Typical SSOP Package Orientation GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications. Ver: 1.0 Jan 23, 2003 TEL: 886-3-5788833 http://www.gmt.com.tw 12