SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 D D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Power Off Disables Outputs, Permitting Live Insertion High-Impedance State During Power Up and Power Down Prevents Driver Conflict Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating Output Ports Have Equivalent 30-Ω Series Resistors, So No External Resistors Are Required Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method Flow-Through Architecture Facilitates Printed Circuit Board Layout Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package SN54ALVTH162827 . . . WD PACKAGE SN74ALVTH162827 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 1Y7 GND 1Y8 1Y9 1Y10 2Y1 2Y2 2Y3 GND 2Y4 2Y5 2Y6 VCC 2Y7 2Y8 GND 2Y9 2Y10 2OE1 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE2 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 1A10 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2A9 2A10 2OE2 NOTE: For order entry: The DGG package is abbreviated to G, and the DGV package is abbreviated to V. description The ’ALVTH162827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 description (continued) The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1 and 1OE2, or 2OE1 and 2OE2) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state. When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. All outputs are designed to sink up to 12 mA, and include equivalent 30-Ω resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ALVTH162827 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALVTH162827 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 10-bit section) INPUTS A OUTPUT Y OE1 OE2 L L L L L L H H H X X Z X H X Z logic diagram (positive logic) 1OE1 1OE2 1A1 1 2OE1 56 55 2OE2 2 1Y1 2A1 28 29 42 To Nine Other Channels 2 POST OFFICE BOX 655303 15 2Y1 To Nine Other Channels • DALLAS, TEXAS 75265 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output current in the low state, IO: SN54ALVTH162827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ALVTH162827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Output current in the high state, IO: SN54ALVTH162827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA SN74ALVTH162827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3) SN54ALVTH162827 MIN VCC VIH Supply voltage 2.3 High-level input voltage 1.7 VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate TYP SN74ALVTH162827 MAX MIN 2.7 2.3 TYP 2.7 1.7 0 Low-level output current Outputs enabled VCC 5.5 0.7 0 UNIT V V 0.7 Input voltage MAX VCC V 5.5 V –6 –8 mA 8 12 mA 10 10 ns/V ∆t/∆VCC Power-up ramp rate 200 200 µs/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3) SN54ALVTH162827 MIN VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 TYP SN74ALVTH162827 MAX MIN 3.6 3 TYP 3.6 2 0 Low-level output current Outputs enabled VCC 5.5 0.8 0 UNIT V V 0.8 Input voltage MAX VCC V 5.5 V –8 –12 mA 8 12 mA 10 10 ns/V µs/V 200 125 –40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 electrical characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER VIK VOH VCC = 2.3 V, VCC = 2.3 V to 2.7 V, II = –18 mA IOH = –100 µA 3V VCC = 2 2.3 IOH = –6 mA IOH = –8 mA VCC = 2.3 V to 2.7 V, VOL SN54ALVTH162827 MIN TYP† MAX TEST CONDITIONS VCC = 2 2.3 3V SN74ALVTH162827 MIN TYP† MAX –1.2 VCC–0.2 1.7 –1.2 V 1.7 IOL = 100 µA IOL = 8 mA 0.2 0.2 V 0.7 IOL = 12 mA VI = VCC or GND 0.7 ±1 ±1 VI = 5.5 V VI = 5.5 V 10 10 10 10 1 1 Control inputs Data inputs VCC = 2.7 V VI = VCC VI = 0 VCC = 0, VCC = 2.3 V, VI or VO = 0 to 4.5 V VI = 0.7 V VCC = 2.3 V, VCC = 2.7 V, VI = 1.7 V VI = 0 to VCC IEX|| VCC = 2.7 V, VCC = 2.3 V, VI = 0 to VCC VO = 5.5 V IOZ(PU/PD)k VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care IOZH VCC = 2.7 V IOZL VCC = 2.7 V Outputs high ICC VCC = 2.7 V, IO = 0, VI = VCC or GND 2.3 5 2.3 5 Outputs disabled 0.04 0.1 0.04 0.1 VCC = 2.5 V, VCC = 2.5 V, VI = 2.5 V or 0 VO = 2.5 V or 0 3.5 Ioff IBHL‡ IBHH§ IBHLO¶ IBHHO# Ci V VCC–0.2 VCC = 2.7 V, VCC = 0 or 2.7 V, II UNIT –5 µA –5 ±100 115 –10 µA 115 µA –10 µA 300 300 µA –300 –300 µA 125 125 µA ±100 ±100 µA VO = 2.3 V, VI = 0.7 V or 1.7 V 5 5 µA VO = 0.5 V, VI = 0.7 V or 1.7 V –5 –5 µA 0.04 Outputs low 0.1 0.04 3.5 0.1 mA pF Co 6 6 pF † All typical values are at VCC = 2.5 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK VOH VCC = 3 V, VCC = 3 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 3 V IOH = –8 mA IOH = –12 mA VCC = 3 V to 3.6 V, VOL SN54ALVTH162827 MIN TYP† MAX TEST CONDITIONS VCC = 3 V –1.2 VCC–0.2 2 2 0.2 V 0.8 IOL = 12 mA VI = VCC or GND 0.8 ±1 ±1 VI = 5.5 V VI = 5.5 V 10 10 10 10 1 1 Data inputs VCC = 3.6 V VI = VCC VI = 0 VCC = 0, VCC = 3 V, VI or VO = 0 to 4.5 V VI = 0.8 V VCC = 3 V, VCC = 3.6 V, IEX|| VCC = 3.6 V, VCC = 3 V, IOZ(PU/PD)k VCC ≤ 1.2 V, VO = 0.5 V to VCC, VI = GND or VCC, OE = don’t care IOZH VCC = 3.6 V IOZL VCC = 3.6 V ICC VCC = 3.6 V, IO = 0, VI = VCC or GND IBHLO¶ IBHHO# V V 0.2 Control inputs Ioff IBHL‡ IBHH§ –1.2 UNIT VCC–0.2 IOL = 100 µA IOL = 8 mA VCC = 3.6 V, VCC = 0 or 3.6 V, II SN74ALVTH162827 MIN TYP† MAX –5 µA –5 ±100 µA 75 75 µA VI = 2 V VI = 0 to VCC –75 –75 µA 500 500 µA VI = 0 to VCC VO = 5.5 V –500 –500 µA 125 125 µA ±100 ±100 µA VO = 3 V, VI = 0.8 V or 2 V 5 5 µA VO = 0.5 V, VI = 0.8 V or 2 V –5 –5 µA Outputs high Outputs low Outputs disabled ∆ICCh VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VCC = 3.3 V, VCC = 3.3 V, VI = 3.3 V or 0 VO = 3.3 V or 0 0.07 0.1 0.07 0.1 3.2 0.07 5.5 3.2 5.5 0.1 0.07 0.1 0.4 3.5 0.4 3.5 mA mA pF Co 6 6 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHLshould be measured after lowering VIN to GND and then raising it to VIL max. § The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. ¶ An external driver must source at least IBHLO to switch this node from low to high. # An external driver must sink at least IBHHO to switch this node from high to low. || Current into an output in the high state when VO > VCC k High-impedance state during power up or power down h This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 switching characteristics over recommended operating free-air temperature range, CL = 30 pF, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y OE Y tPHZ tPLZ SN54ALVTH162827 SN74ALVTH162827 MIN MAX MIN MAX 1.7 4.1 1.7 4.1 1.6 4 1.6 4 2.1 4.8 2.1 4.8 1.9 4.8 1.9 4.8 2.4 6 2.4 6 1.7 5 1.7 5 UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y OE Y tPHZ tPLZ SN54ALVTH162827 SN74ALVTH162827 MIN MAX MIN MAX 1 3.9 1 3.9 1.5 3.7 1.5 3.7 1 5.6 1 5.6 1.7 4.1 1.7 4.1 3.6 6.3 3.6 6.3 1.7 5.1 1.7 5.1 UNIT ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALVTH162827, SN74ALVTH162827 2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCES079E – JULY 1996 – REVISED DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V 1.5 V 3V 1.5 V 0V 0V Output Output Waveform 1 S1 at 6 V (see Note B) 3V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ tPZH tPHL VOH 1.5 V tPLZ tPZL 1.5 V tPLH 1.5 V 0V 3V 1.5 V 1.5 V Output Control VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 0V 0V tsu Data Input 1.5 V Input 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74ALVTH162827GRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVTH162827VRE4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH162827DL ACTIVE SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH162827GR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH162827LR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVTH162827VR ACTIVE TVSOP DGV 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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