CXD2443Q Timing Generator for LCD Panels Description The CXD2443Q is a timing generator for the LCD panel LCX011 and LCX019 driver. This chip has a built-in serial interface circuit which allows various settings to be performed through external control from a microcomputer, etc. Features • Generates the LCD panel LCX011/LCX019 drive pulse • Supports NTSC/PAL (PAL supported by scanning line conversion of video signal to 525H or pulse eliminate.) • Supports WIDE mode (when driving the LCX011) • Supports HD mode (when driving the LCX011) • Supports up/down and/or right/left inversion • Supports 3-panel projectors • Generates timing signal of external sample-andhold circuit • Generates line inversion and field inversion signals • AC drive of LCD panels during no signal • Line double-speed display realized with a built-in double-speed controller (NTSC/PAL) (4:3 mode only) (Line memory µPD485505: NEC) 100 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25°C, VSS = 0V) • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr V –20 to +75 °C Applications LCD projectors, etc. Structure Silicon CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96X31-PS CXD2443Q CKI1 CKO1 88 11 10 CKO2 CKI2 CKO3 91 89 9 RPD2 87 RPD3 93 FPD1 CKI3 98 99 92 5 83 97 RPD1 CKI5 CKSL TC3 TC1 TC2 Block Diagram 6 HD 16 : 9 LOOP FILTER 4:3 PHASE COMPARATOR 8 PWM1 86 PWM2 95 PWM3 7 PEO1 85 PEO2 FPD2 84 94 MASTER CLOCK PEO3 FPD3 96 PLL COUNTER HSYNC 13 H-SYNC DETECTOR VSYNC 14 V-SYNC SEPARATOR 100 HDR DECODER 43 HSTA 38 HCK1A 37 HCK2A V-CONTROL COUNTER 36 ENB 35 VCK V-POSITION COUNTER VST 34 DECODER & V-TIMING PULSE GENERATOR FLDO 21 VWA 30 VWB 2 49 FRP FIELD & LINE CONTROLLER 50 XFRP 31 PCG1 H-POSITION COUNTER SCTR 16 XCLP1 48 XCLP2 46 PCG2 DECODER & H-TIMING PULSE GENERATOR PULSE ELIMINATOR 47 51 SH1A 52 SH2A 55 SH3A SCLK 17 56 SH4A SERIAL I/F SDAT 18 57 SH5A PRE 19 58 SH6A 59 SH7A DOUBLE SCAN CONVERTER H-SYNC DETECTOR 42 HSTB 41 RPD4 76 FPD4 77 HCK1B 39 HCK2B PHASE COMPARATOR 61 SH1B TC4 82 CLOCK2 LOOP FILTER 81 44 45 32 PEO4 PWM4 XRGT TEST: 12, 20, 22, 23, 24, 25, 26, 27, 33, 60, 69 VDD: 3, 28, 53, 78 VSS: 4, 15, 29, 40, 54, 65, 79, 90 –2– DWN 80 RGT 74 CKO4 CKI4 WCK RSTR 75 RCK 70 71 72 73 RSTW DECODER DIRECT CLEAR 1 XCLR PLL COUNTER2 62 SH2B 63 SH3B 64 SH4B 66 SH5B 67 SH6B 68 SH7B CXD2443Q Pin Description Pin No. Symbol I/O 1 XCLR I System clear (Low: All clear) H 2 VWB O V window pulse B output — 3 VDD — Power supply — 4 VSS — GND — 5 TC1 I/O FPD1 output pulse width adjustment (NTSC/PAL 4:3) — 6 FPD1 O Phase comparator 1 output (NTSC/PAL 4:3) — 7 PEO1 I/O Loop filter integrator 1 output (NTSC/PAL 4:3) — 8 PWM1 O Loop filter integrator 1 input (NTSC/PAL 4:3) — 9 RPD1 O Phase comparator 1 output (NTSC/PAL 4:3) — 10 CKO1 I/O Oscillation cell 1 output (NTSC/PAL 4:3) — 11 CKI1 I Oscillation cell 1 input (NTSC/PAL 4:3) — 12 TEST2 I Test (Not connected.) — 13 HSYNC I Horizontal sync signal input (Polarity set by serial data HPOL.) — 14 VSYNC I Vertical sync signal input (Polarity set by serial data VPOL.) — 15 VSS GND — 16 SCTR I Chip select input (serial transfer block) — 17 SCLK I Serial clock input (serial transfer block) — 18 SDAT I Serial data input (serial transfer block) — 19 PRE I Preset setting (Set to NTSC 4:3 mode when Low.) H 20 TEST11 — Test (Not connected.) — 21 FLDO O Field discrimination signal output — 22 TEST1 — Test (Not connected.) — 23 TEST3 — Test (Not connected.) — 24 TEST4 — Test (Not connected.) — 25 TEST5 — Test (Not connected.) — 26 TEST6 — Test (Not connected.) — 27 TEST7 — Test (Connect to GND.) — 28 VDD — Power supply — 29 VSS — GND — 30 VWA O V window pulse A output — 31 PCG1 O PCG1 pulse output (positive polarity) — 32 DWN O Up/down inversion identification signal output (High: Down, Low: Up) — 33 TEST8 — Test (Not connected.) — 34 VST O V start pulse output (positive polarity) — 35 VCK O V clock pulse output — — Description –3– Input pin for open status CXD2443Q Pin No. Symbol I/O 36 ENB O ENB pulse output (negative polarity) — 37 HCK2A O H clock 2A pulse output — 38 HCK1A O H clock 1A pulse output — 39 HCK2B O H clock 2B pulse output — 40 VSS — GND — 41 HCK1B O H clock 1B pulse output — 42 HSTB O H start B pulse output (positive polarity) — 43 HSTA O H start A pulse output (positive polarity) — 44 RGT O Right/left inversion identification signal output (High: Right, Low: Left) — 45 XRGT O Right/left inversion identification signal output (Low: Left, High: Right) — 46 PCG2 O PCG2 pulse output (positive polarity) — 47 XCLP1 O Pedestal clamp pulse 1 output (negative polarity) — 48 XCLP2 O Pedestal clamp pulse 2 output (negative polarity) — 49 FRP O AC drive inversion timing output — 50 XFRP O AC drive inversion timing output (reverse polarity of FRP) — 51 SH1A O Sample-and-hold pulse 1A output (positive polarity) — 52 SH2A O Sample-and-hold pulse 2A output (positive polarity) — 53 VDD — Power supply — 54 VSS — GND — 55 SH3A O Sample-and-hold pulse 3A output (positive polarity) — 56 SH4A O Sample-and-hold pulse 4A output (positive polarity) — 57 SH5A O Sample-and-hold pulse 5A output (positive polarity) — 58 SH6A O Sample-and-hold pulse 6A output (positive polarity) — 59 SH7A O Sample-and-hold pulse 7A output (positive polarity) — 60 TEST9 — Test (Not connected.) — 61 SH1B O Sample-and-hold pulse 1B output (positive polarity) — 62 SH2B O Sample-and-hold pulse 2B output (positive polarity) — 63 SH3B O Sample-and-hold pulse 3B output (positive polarity) — 64 SH4B O Sample-and-hold pulse 4B output (positive polarity) — 65 VSS — GND — 66 SH5B O Sample-and-hold pulse 5B output (positive polarity) — 67 SH6B O Sample-and-hold pulse 6B output (positive polarity) — 68 SH7B O Sample-and-hold pulse 7B output (positive polarity) — 69 TEST10 — Test (Not connected.) — 70 RCK O Read clock output (for line buffer) — Description –4– Input pin for open status CXD2443Q Pin No. Symbol I/O 71 RSTR O Read reset output (for line buffer, negative polarity) — 72 WCK O Write clock output (for line buffer) — 73 RSTW O Write reset output (for line buffer, negative polarity) — 74 CKO4 I/O Oscillation cell 4 output (line double-speed controller) — 75 CKI4 I Oscillation cell 4 input (line double-speed controller) — 76 RPD4 O Phase comparator 4 output (line double-speed controller) — 77 FPD4 O Phase comparator 4 output (line double-speed controller) — 78 VDD — Power supply — 79 VSS — GND — 80 PEO4 I/O Loop filter integrator 4 output (line double-speed controller) — 81 PWM4 O Loop filter integrator 4 input (line double-speed controller) — 82 TC4 I/O FPD4 output pulse width adjustment (line double-speed controller) — 83 TC2 I/O FPD2 output pulse width adjustment (NTSC/PAL 16:9) — 84 FPD2 O Phase comparator 2 output (NTSC/PAL 16:9) — 85 PEO2 I/O Loop filter integrator 2 output (NTSC/PAL 16:9) — 86 PWM2 O Loop filter integrator 2 input (NTSC/PAL 16:9) — 87 RPD2 O Phase comparator 2 output (NTSC/PAL 16:9) — 88 CKO2 I/O Oscillation cell 2 output (NTSC/PAL 16:9) — 89 CKI2 I Oscillation cell 2 input (NTSC/PAL 16:9) — 90 VSS — GND — 91 CKO3 I/O Oscillation cell 3 output (HD) — 92 CKI3 I Oscillation cell 3 input (HD) — 93 RPD3 O Phase comparator 3 output (HD) — 94 PEO3 I/O Loop filter integrator 3 output (HD) — 95 PWM3 O Loop filter integrator 3 input (HD) — 96 FPD3 O Phase comparator 3 output (HD) — 97 TC3 I/O FPD3 output pulse width adjustment (HD) — 98 CKSL I PLL system switching (High: Built-in PLL, Low: External PLL) H 99 CKI5 I External clock input (for external phase comparison) — 100 HDR O Phase comparator output (for external phase comparison) — Input pin for open status Description ∗ H: Pull up, L: Pull down –5– CXD2443Q Electrical Characteristics 1. DC characteristics Item Supply voltage (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C) Symbol Conditions VDD Input, output voltages VI, Vo Input voltage 1 VIH VIL Vt– Typ. Max. Unit 4.5 5.0 5.5 V VDD V Vss CMOS input Vt+ Input voltage 2 Min. 0.7VDD Vt– ∗1 0.8 V HSYNC, SCTR, VSYNC, SCLK, SDAT 0.2VDD V TC1, TC2, TC3, TC4 V ∗2 V ∗3 V RCK, WCK V PEO1, PEO2, PEO3, PEO4, CKO4 V CKO1, CKO2, CKO3 2.2 Vt+ – Vt– Input voltage 3 V 0.3VDD TTL Schmitt trigger input 0.4 Vt+ Applicable pins 0.8VDD CMOS Schmitt trigger input Vt+ – Vt– 0.6 VOH IOH = –2mA VOL IOL = 4mA VOH IOH = –4mA VOL IOL = 8mA VOH IOH = –4mA VOL IOL = 6mA VOH IOH = –3mA VOL IOL = 3mA VOH IOH = –12mA VOL IOL = 12mA II ∗4 –10 IIL ∗6 –40 II ∗8 –40 40 Output leak current IOZ ∗10 –40 40 µA ∗11 Current consumption IDD ∗12 110 mA At a 30pF load∗13 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Input leak current VDD – 0.8 0.4 VDD – 0.8 0.4 VDD – 0.8 0.4 VDD/2 VDD/2 VDD/2 VDD/2 ∗5 10 –100 –240 µA ∗7 ∗9 ∗1 XCLR, PRE, CKSL, CKI1, CKI2, CKI3, CKI4, CKI5, CKO1, CKO2, CKO3, CKO4, PWM1, PWM2, PWM3, PWM4, PEO1, PEO2, PEO3, PEO4 ∗2 HDR, ENB, PCG1, PCG2, XCLP1, XCLP2, VST, FRP, XFRP, VCK, DWN, FLDO, RGT, XRGT, VWA, VWB, RPD1, RPD2, RPD3, RPD4, FPD1, FPD2, FPD3, FPD4, TC1, TC2, TC3, TC4, RSTR, RSTW ∗3 HSTA, HCK1A, HCK2A, SH1A, SH2A, SH3A, SH4A, SH5A, SH6A, SH7A, HSTB, HCK1B, HCK2B, SH1B, SH2B, SH3B, SH4B, SH5B, SH6B, SH7B ∗4 Normal input pins (VIN = VSS or VDD) ∗5 HSYNC, VSYNC, SCLK, SDAT, SCTR, CKI5 ∗6 Pins with pull-up resistors (VIN = VSS) ∗7 PRE, XCLR, CKSL ∗8 Bidirectional pins (input status, VIN = VSS or VDD) ∗9 CKO1, CKO2, CKO3, CKO4, PEO1, PEO2, PEO3, PEO4, TC1, TC2, TC3, TC4 ∗10 At high impedance (VIN = VSS or VDD) ∗11 RPD1, RPD2, RPD3, RPD4, FPD1, FPD2, FPD3, FPD4 ∗12 fclk = 67MHz, VDD = 5.5V ∗13 HSTA, HSTB, HCK1A, HCK2A, HCK1B, HCK2B, SH1A, SH2A, SH3A, SH4A, SH5A, SH6A, SH7A, SH1B, SH2B, SH3B, SH4B, SH5B, SH6B, SH7B, VCK, ENB, FRP, PCG1, PCG2, XCLP1, XCLP2, RGT, DWN –6– CXD2443Q 2. AC characteristics (VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C) Item Symbol Clock input cycle Output fall time tr tf Cross-point time difference ∆t Output rise delay time tpr tpf tH/(tH + tL) tL/(tH + tL) Output rise time Output fall delay time HCK1 Duty HCK2 Duty Applicable pins Min. CKI1 21.3 CKI2 16.0 CKI3 15 CKI4 28.2 CKI5 15 Typ. max. Conditions Unit ns All outputs 20 CL = 30pF All outputs ∗1 20 CL = 30pF 10 CL = 30pF All outputs 15 CL = 30pF All outputs 15 CL = 30pF –10 HCK1A, HCK1B 48 52 CL = 30pF HCK2A, HCK2B 48 52 CL = 30pF % ∗1 HCK1A, 2A HCK1B, 2B 3. Serial transfer AC characteristics tw1L tw1H tw2 tw3 Min. Item Symbol ts0 ts1 th0 th1 (VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C) SCTR setup time, activated by rise of SCLK 4T SDAT setup time, activated by rise of SCLK 2T SCTR hold time, activated by rise of SCLK 4T SDAT hold time, activated by rise of SCLK 2T SCLK pulse width 2T SCLK pulse width 2T Typ. Max. Unit ns 5T 5T T: Master clock cycle (ns) –7– CXD2443Q 4. Timing definitions AC characteristics 100% CKI1, CKI2 CKI3, CKI4 VDD 0V tpr Output VDD 90% 10% 0V tr tf 90% Output VDD 10% 0V tpf HCK1A HCK1B VDD 50% 50% 0V VDD HCK2A HCK2B 50% 50% 0V ∆t HCK1A HCK1B ∆t 50% 50% 50% tH tL Note) HCK2 is the reverse phase of HCK1. Serial transfer AC characteristics ts0 SCTR th0 50% 50% tw1L SCLK tw2 tw1H 50% 50% ts1 SDAT 50% tw3 th1 D15 ts1 D14 D9 th1 D8 D7 D0 Note) See "Serial transfer timing" on P. 17 for the timing relationship between D15 to D0 and each pulse. –8– D15 –9– 2 dots 480 dots (effective 31.6701mm) 2 dots G2 B2 R1 DL2 GATE SW G2 B2 R1 1 GATE SW G2 B2 R1 2 GATE SW ODD = 200 dots EVEN = 200 dots • • • • 34 GATE SW B2 R1 • • • • GATE SW B2 (effective 23.7501mm) ODD = 1200 dots EVEN = 1199 dots R1 234 GATE SW B2 R1 • • • • GATE SW B2 • • • • ODD = 200 dots EVEN = 200 dots B1 267 GATE SW G2 B2 R1 • • • • DR1 GATE SW G2 B2 R1 ODD = 13 dots EVEN = 13 dots DR2 GATE SW JTP JTN WDX WD VSS VDD PCX PC SID 480 479 4 3 2 1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B2 B2 B2 B2 B2 B2 B2 B2 B2 G2 B2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B2 B2 B2 B2 B2 B2 B2 B2 B2 G2 B2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B2 B2 B2 B2 B2 B2 B2 B2 B2 G2 B2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 G1 B1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G1 G1 G1 G1 G1 G1 G1 G1 G1 R2 G1 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G1 G1 G1 G1 G1 G1 G1 G1 G1 R2 G1 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 AA AA A A AA A AA AA A A AA A AA AA A A AA A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA A AA AA A A AA A AA AA A A AA A A AA A AA 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A AA A A AA A A AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA A A A A AA A A A A A A A AA A A A A A A A AA A A A A AA A A A AA A A A A AA A A A A A AA A A A A A A A AAAA AA AAA AAA AAAAA AAA AA A A AA A AA A A A AA A A AA A AA A AA A A AA A AA A A AA A A AA A A A AA A AA A A A A AA A AA A A AA A A AA A AA A AA A A AA A AA A A AA A AA A AA A A AA AA A AA A A AA A AA A AA A A AA AA A AA A A A AA AA A A A AA AA A A A A AA AA A A A AA AA A A AA A A AA A A AA AA A A A AA AA A AA A A AA A AA A A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA AA A AA A AAA AA AA AA AA AA A AAAA AA AA AA AAAAAAAA A AAAAAA AAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAA AAAAAA AAAAAAAA AAA AAAAA DL1 GATE SW ODD = 13 dots EVEN = 14 dots ODD = 1626 dots EVEN = 1626 dots LCX011 Dot Arrangement (1) (4:3 display) The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed. R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6. CXD2443Q – 10 – 2 dots 480 dots (effective 31.6701mm) 2 dots G2 B2 R1 DL2 GATE SW G2 B2 R1 1 GATE SW G2 B2 R1 2 GATE SW • • • • 34 GATE SW B2 R1 • • • • GATE SW B2 (effective 31.6701mm) ODD = 1600 dots EVEN = 1599 dots R1 234 GATE SW B2 R1 • • • • GATE SW B2 • • • • B1 267 GATE SW G2 B2 R1 • • • • DR1 GATE SW G2 B2 R1 ODD = 13 dots EVEN = 13 dots DR2 GATE SW JTP JTN WDX WD VSS VDD PCX PC SID 480 479 4 3 2 1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R2 R2 R2 R2 R2 R2 R2 R2 R2 R2 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R1 G2 B1 R2 R2 R2 R2 R2 R2 R2 R2 R2 B2 R2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 B2 G2 B2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 B2 R2 G2 R1 G2 B1 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B2 B2 B2 B2 B2 B2 B2 B2 B2 G2 B2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B2 B2 B2 B2 B2 B2 B2 B2 B2 G2 B2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B2 B2 B2 B2 B2 B2 B2 B2 B2 G2 B2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 G2 R2 G2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 G1 R1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 R1 G1 B1 B1 B1 B1 B1 B1 B1 B1 B1 G1 B1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 G1 R1 G1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G1 G1 G1 G1 G1 G1 G1 G1 G1 R2 G1 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G1 G1 G1 G1 G1 G1 G1 G1 G1 R2 G1 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B2 R1 R2 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 B1 G1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 R1 B1 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 G2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 B2 R2 AA AA A A AA A AA AA A A AA A AA AA A A AA A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA A AA AA A A AA A AA AA A A AA AA AA AA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AA AAA AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A A AA A A A AA A A A A AA A A A AA A A A AA A A A AA A A A AA A AA A A AA A AA A AA A AA A AA AA A A AA A AA AA A A AA A AA AA A AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A A AA A AA AA A AA A A AA A AA AA A A AA A AA AAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAAAA AAAAAA AAAAAAA AAAAAAAA AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA AA A AA A A A AA AA A A AA A AA A A AA A A AA AA A AA A AA A AA A A AA A A AA A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A A AA A A AA AA A AA A A AA A A AA AAA AAA AA AA A AA A AA A A AA A AA A AA AA A A AA A AA A A AA A AA A A AA A AA A A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA AA AAAAA AAA AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A A A A A AA A AA A A AA A AA A A AA A A AA A AA A AA A A AA A AA A A AA A AA A AA A A AA AA A AA A A AA A AA A AA A A AA AA A AA A A AA A AA A A A AA AA A A A A AA AA A A A AA AA A A AA A A AA A A AA AA A A A AA AA A AA A A AA A AA A A A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A AA A AA A A AA A AA A A AA AA A AA A AAA AA AA AA AA AA A AA AA AA AA AA AA A AAAAAAAAAAA A AAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAA AAAAAA AAAAA AAA AAAAAAAA DL1 GATE SW ODD = 13 dots EVEN = 14 dots ODD = 1626 dots EVEN = 1626 dots LCX011 Dot Arrangement (2) (16:9 display) The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed. R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6. CXD2443Q 2 dots – 11 – 480 dots 2 dots B G R B G R DR2 GATE SW B G R B G R 1 GATE SW B G R B G R GATE SW B G R B G R 201 GATE SW B G R B G R DL2 GATE SW B G R B G R DR1 GATE SW R G G G R R R PCX PC PSIG R G G G R 480 R 479 G G G G R 4 R 3 2 1 R R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B G G G G G G G G G R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B B B B B B B B B B G G G G G G G G G G R R R R R R R R R R B G B B B B B B B B B B G G G G G G G G G B B B B B B B B B AA A A AA A A AA A AA A A AA A AA A A AA A AA A A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A AA A AA A A A AA AA A A AA A AA A A AA A A AA A A AA A AA A A AA A A AA A AA A AA A A AA A AA A A AA A A A AA A AA AA A A AA A AA A A AA A AA A AA AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A AA AA A AA A A AA A AA A A AA AA A AA A A AA A AA A AA A A AA AA A AA A A AA A AA A A A AA AA A A AA A A AA AA A A A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A AA A AA A AA A A A AA AA A A AA A AA A A AA A A AA A A AA A AA A A AA A A AA A AA A AA A A AA A AA A A AA A A A A A AA A A A A A A A AA A A A A A A A AA A A A AA A A A A AA A A A AA A AA AA A A AA A AA A A AA A AA A AA AA A A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A A A AA A AA A AA A AA A AA A A AA A AA A AA A AA A AA A AA A A AA A AA A A AA A AA A A AA A AA A AA A A AA A AA AAAA AAAAAAAAA AAAAAAAA AAA AAA AAAAAA DR1 GATE SW ODD = 1200 dots EVEN = 1199 dots LCX019 Dot Arrangement The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed. R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6. CXD2443Q CXD2443Q Input Signal Protocol 1. Horizontal sync signal • A double-speed HSYNC or standard HSYNC (or CSYNC) should be input for NTSC and PAL display modes. Double-speed HSYNC and standard HSYNC input switching is set by the serial data (SNSL). Note) The double-speed HSYNC should have a cycle and width 1/2 that of the standard HSYNC. • The signal obtained by cutting off only the bottom of the ternary SYNC should be input for HD display mode. • The input sync signal polarity is not fixed, and is set by the serial data (HPOL). • When using the built-in line double-speed controller, set serial data SNSL to Low. The built-in line doublespeed controller supports only the standard HSYNC (or CSYNC). 2. Vertical sync signal • A normal-speed VSYNC (or CSYNC) should be input for NTSC and PAL display modes. • A VSYNC that has been sync separated by SYNC SEP. should be input for HD display mode. • The input sync signal polarity is not fixed, and is set by the serial data (VPOL). • The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2443Q. (1) Double-speed NTSC Double-speed HSYNC VSYNC Sync signal phase reference (2) Double-speed PAL Double-speed HSYNC VSYNC Sync signal phase reference (3) NTSC (CSYNC input) ODD FIELD CSYNC EVEN FIELD Sync signal phase reference CSYNC (4) PAL (CSYNC input) ODD FIELD CSYNC EVEN FIELD Sync signal phase reference CSYNC (5) HD ODD FIELD HSYNC VSYNC Sync signal phase reference EVEN FIELD HSYNC VSYNC Sync signal phase reference – 12 – CXD2443Q Description of Operation Clock input The CXD2443Q supports two types of PLL circuits. PLL switching is performed by CKSL (Pin 98). (High: Built-in PLL, Low: External PLL) Note) The built-in line double-speed controller PLL is supported only by the built-in PLL. (1) Built-in PLL (CKI1, CKI2, CKI3, CKI4) A PLL circuit is comprised by the built-in phase comparator and an external VCO circuit. There are four clock inputs which support the following modes. CKI1: NTSC/PAL 4:3 CKI2: NTSC/PAL 16:9 CKI3: HD CKI4: For built-in line double-speed controller The PLL lock for this system is adjusted by setting the RPD and FPD transition points so that they fall at the center of the windows as shown in the diagram below. (See the Application Circuit.) a a HSYNC RPD b b Output waveform during PLL lock FPD 800ns (2) External PLL (CKI5) The CKI5 pin is the clock input pin when using an external PLL IC. The 1/N frequency divider output is output from the HDR pin (frequency division ratio N/2) for the PLL IC. Set CKSL (Pin 98) to Low to switch to the external PLL. N fH HSYNC HDR N/2 fH AC driving of LCD panels for no signal The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. • Horizontal direction pulse The PLL is set to free running status. The frequency of the horizontal direction pulse at this time is dependent on the PLL free running frequency. • Vertical direction pulse The number of lines is counted by an internal counter and the vertical direction pulses (VST, FRP) are output at a specified cycle. For the CXD2443Q, no signal (free running) status is judged if there is no VSYNC input for longer than the following (free running detection) periods. Mode V cycle for no signal Free running detection NTSC 544H (272H) PAL 640H (320H) HD 576H 1024H (512H) Note) Numbers in parentheses are for when using the built-in line double-speed controller. – 13 – CXD2443Q Right/left and/or up/down inversion In delta arrangement LCD panels, the same signal lines are separated by 1.5 dots for each horizontal line. Therefore, a 1.5 dot offset is added between lines to the LCD's horizontal direction start pulses HST and HCK and sample-and-hold pulse (SH). When driving an LCD panel with right and left inversed, the dot arrangement is asymmetrical so an offset is attached to HST, HCK and SH. When driving with up and down inversed, the relationship between the panel's odd and even line offsets is reversed. Right scan Left scan H SCANNER V SCANNER Down scan Effective display area Up scan 1.5fH 1.5fH MCK Down scan, odd line Up scan, even line HST Right and down scan, even line Right and up scan, odd line Left and down scan, even line Left and up scan, odd line – 14 – CXD2443Q When using three LCD panels B outputs (HSTB, HCK1B, HCK2B, SH1B to 7B) are provided for driving three LCD panels with and without right/left inversion at the same time. These B outputs are the right/left inversed timings of the A outputs (HSTA, HCK1A, HCK2A, SH1A to 7A). XRGT (RGT inversed output) is also provided for right/left inversion scanning. Application circuit (driving three LCD panels) TG SH1A 51 SH2A 52 Panel 1 (right scan) SH3A 55 SH4A 56 Right scan (A outputs) SIGNAL DRIVER SH5A 57 SH6A 58 SIGNAL DRIVER SH7A 59 HSTA 43 HCK1A 38 Panel 2 (right scan) HCK2A 37 RGT 44 SH1B 61 SH2B 62 SH3B 63 SH4B 64 Left scan (B outputs) SIGNAL DRIVER SH5B 66 Panel 3 (left scan) SH6B 67 SH7B 68 HSTB 42 HCK1B 41 HCK2B 39 XRGT 45 DWN 32 ENB 36 Common VCK 35 PCG1 31 or PCG2 46 Note) All three panels face the same direction. VST 34 – 15 – CXD2443Q Built-in line double-speed controller This controller is designed to use the µPD485505 (NEC/high-speed line buffer) as the system line memory IC, and generates the double-speed processing pulses RSTW (reset write), WCK (write clock), RSTR (reset read) and RCK (read clock). Operation is as follows. Write operation is started at the RSTW timing, and this memory information is read twice at double speed at the RSTR timing which is delayed by 1/2H and 1H from the RSTW timing. The write and read clock frequencies at this time are generated by the built-in PLL (CKI4). See the specifications for a detailed description of µPD485505 operation. ADC R, G, B IN DAC LINE Mem. µPD485505 RSTW WCK HSYNC VSYNC CSYNC RSTR RCK CXD2443Q MCK : f Double-speed display system block HSYNC RSTW WCK f/2 RSTR RCK f HSYNC RSTW RSTR Double-speed display timing Note) See the timing charts for details. – 16 – CXD2443Q XCLR pin The CXD2443Q should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. Serial transfer operation 1. Control method The CXD2443Q operation timing is controlled by serial data. The control data is comprised of an 8-bit address and 8-bit data, and the individual data is fetched at the rise of SCLK. This fetching operation starts from the fall of SCTR and is completed at the next rise of SCTR. Serial transfer timing SCTR SCLK SDAT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 Address D4 D3 D2 D1 D0 Data 2. Control data When using the CXD2443Q, set the control data corresponding to each signal source according to the formats in the table below. Data Address D15 D14D13 D12 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function 0 0 0 0 0 0 0 0 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 (A) H-POSITION 0 0 0 0 0 0 0 1 — — — — VP4 VP3 VP2 VP1 (B) V-POSITION 0 0 0 0 0 0 1 0 — — — — 0 0 0 0 0 0 1 1 — — — — — — 0 0 0 0 0 1 0 0 — — — — — — PCGW2 PCGW1 (E) PCG-POSITION 0 0 0 0 0 1 0 1 — — — — — — VM9J VM8J 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 VM7J VM6J VM5J VM4J VM3J VM2J VM1J VM0J (F) VWA-POSITION (VWA pulse) 1 — — — — — VM9K VM8K — 0 0 0 0 1 0 0 0 VM7K VM6K VM5K VM4K VM3K VM2K VM1K VM0K 0 0 0 0 1 0 0 1 — — — — — — 0 0 0 0 1 0 1 0 — — — — — — 0 0 0 0 1 0 1 1 — — — — — — 0 0 0 0 1 1 0 0 — — 0 0 0 0 1 1 0 1 — — — — 0 0 0 0 1 1 1 0 — — — — SLSH4 SLSH3 SLSH2 SLSH1 (C) SH-POSITION CP2 CP1 TEST1 SLBA MA TEST2 DWN RGT TEST4 TEST3 SL3B VPOL HPOL SLFR — — SLVWB SLEG (D) XCLP-POSITION (G) Double-speed setting (H) Double-speed PAL pulse eliminate (I) Right/left and/or up/down inversion (J) Various settings SNSL XHD XWID NT-PAL (K) Mode settings Note) 1. Set "High" as the TEST1, TEST2, TEST3 and TEST4 data. 2. "—" indicates not set. – 17 – CXD2443Q Serial settings during power on The CXD2443Q should be forcibly reset during power on using the XCLR pin. After being forcibly reset, the master clock for the CXD2443Q is supplied from CKI3. The initial serial data after power on is loaded to the CXD2443Q using the clock from CKI3. Serial settings during PLL free running When the PLL is in free running status, the serial clock cycle (F ns) may be less than F ≥ 2T with respect to the master clock cycle (T ns). Take care that the serial clock cycle setting is such that F ≥ 2T during PLL free running. Each control data is described in detail below. (A) H-POSITION (HP1, HP2, HP3, HP4, HP5, HP6, HP7, HP8) These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of up to ±128 dots is possible with respect to the design center value. (data: 8 bits) Design center value HP1 HP2 HP3 HP4 HP5 HP6 HP7 HP8 L L L L L L L H MODE Variable time (±128fH) NTSC (4:3) ±2.8µs NTSC (16:9) ±2.1µs PAL (4:3) ±2.7µs PAL (16:9) ±2.0µs HD ±1.9µs (B) V-POSITION (VP1, VP2, VP3, VP4) These bits set the vertical display start position. The minimum adjustment width is 1H, and adjustment of up to ±8H is possible with respect to the design center value. (data: 4 bits) Design center value VP1 VP2 VP3 VP4 L L L H – 18 – CXD2443Q (C) SH-POSITION (SLSH1, SLSH2, SLSH3, SLSH4) These bits control the phase relationship between HCK1, HCK2 and SH1, 2, 3, 4, 5, 6 and 7. The minimum adjustment width is 0.5 dots, and adjustment of up to 6 dots is possible. (data: 4 bits) RGT = High: A output RGT = Low: B output SLSH1, 2, 3, 4 LLLL (0) HLLL (1) LHLL (2) HHLL (3) HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 RGT = Low: A output RGT = High: B output HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 – 19 – LLHL (4) HLHL (5) LHHL (6) CXD2443Q RGT = High: A output RGT = Low: B output SLSH1, 2, 3, 4 HHHL (7) LLLH (8) HLLH (9) HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 RGT = Low: A output RGT = High: B output HCKn SH1 SH2 SH3 SH4 SH5 SH6 SH7 – 20 – LHLH (A) HHLH (B) ∗∗HH (C, D, E, F) CXD2443Q (D) XCLP-POSITION (CP1, CP2) These bits control the phase relationship between pedestal clamp pulses XCLP1 and XCLP2 and HSYNC. The phase can be adjusted in 400ns units to four levels. (data: 2 bits) –250ns 150ns –650ns 0 950ns 550ns 1750ns 1350ns 2550ns 2150ns HSYNC XCLP1 CP1 = H, CP2 = H CP1 = L, CP2 = H (design center value) CP1 = H, CP2 = L CP1 = L, CP2 = L XCLP2 CP1 = H, CP2 = H CP1 = L, CP2 = H (design center value) CP1 = H, CP2 = L CP1 = L, CP2 = L (E) PCG-POSITION (PCGW1, PCGW2) These bits control the PCG1 pulse width (falling edge). The width can be adjusted in 200ns units to four levels. (data: 2 bits) 1.4µs 1.2µs Fixed 1.8µs 1.6µs PCG pulse PCGW1, 2 = – 21 – LL HL LH HH CXD2443Q (F) VWA-POSITION (VM0J, VM1J, VM2J, VM3J, VM4J, VM5J, VM6J, VM7J, VM8J, VM9J, VM0K, VM1K, VM2K, VM3K, VM4K, VM5K, VM6K, VM7K, VM8K, VM9K) The VWA pulse rise and fall can be varied in 1H units in the vertical direction. Rise position: VW0J to 9J (10 bits) Fall position: VW0K to 9K (10 bits) Rise, fall transition points: ENB pulse fall position Reference (0): 1.5H before the VST output position Reference (0) Double-speed HSYNC VST (G) Double-speed setting (SLBA) • This bit sets the built-in line double-speed controller. SLBA High: Line double-speed controller off Low: Line double-speed controller on • The loop counter is an N multiple of the following. NTSC PAL 910fH 1135fH Notes on operation The built-in line double-speed controller is supported only when driving a single LCD panel in NTSC/PAL 4:3 mode. When using the CXD2443Q in other modes (NTSC/PAL 16:9 mode, HD mode, 3-panel mode), be sure to set the line double-speed controller to off (SLBA = High). – 22 – CXD2443Q (H) Double-speed PAL pulse eliminate (MA) This bit sets the double-speed PAL pulse eliminate (conversion from 575 to 480 vertical lines by 6, 7 pulse eliminate). The setting is as follows. MA High: Pulse eliminate off Low: Pulse eliminate on The 2N + 1 field pulse eliminate position is shifted 1H (line) to the rear with respect to the 2N field pulse eliminate position. (I) Right/left and/or up/down inversion (RGT, DWN) These bits switch the right/left inversion and/or up/down inversion timing for the LCD panel. Output Setting RGT DWN A outputs B outputs RGT XRGT DWN H L H L H H L L Right scan, down scan Left scan, down scan Right scan, up scan Left scan, up scan Left scan, down scan Right scan, down scan Left scan, up scan Right scan, up scan H L H L L H L H H H L L Note) The B outputs (HSTB, HCKnB, SHnB) are the outputs for 3-panel projectors, and are output at the right/left inversed timing of the A outputs. (J) Various settings SLFR This bit sets the cycle of the LCD AC drive signals FRP and XFRP. High: 1H (line) inversion Low: 1F (field) inversion VPOL, HPOL These bits set the input SYNC polarity. High: Negative polarity Low: Positive polarity – 23 – CXD2443Q SL3B This bit sets the 3-panel projector output (B outputs) switching. The HSTB, HCKnB, and SHnB outputs can be switched on and off. High: B outputs off Low: B outputs on Note) When driving a single LCD panel, set the B outputs to off (SL3B = High). SLVWB This bit sets the VWB output. High: VWB off Low: VWB on SLEG This bit sets the VWB transition timing. High: HSYNC front edge Low: HSYNC rear edge Note) VWB is the equalizing pulse masking pulse. The rise position is counted from the VD inside the previous field. Therefore, when the number of lines within one field differs from the standard protocol, the phase between the next field's VSYNC and the VWB rise position changes. The phase also changes when a value other than the default value is used as the V-POSITION setting. (K) Mode settings SNSL This bit sets the double-speed HSYNC and standard HSYNC (or CSYNC) input switching. High: Double-speed HSYNC input Low: Standard HSYNC (CSYNC) input Note) When using the built-in line double-speed controller, only the standard HSYNC is supported. Set SNSL to standard HSYNC input (SNSL = Low). NT-PAL, XWID, HD These bits set the various display modes. NTSC (4:3) NTSC (16:9) PAL (4:3) PAL (16:9) HD NT-PAL H H L L ∗ XWID H L H L ∗ XHD H H H H L Note) Test mode Serial data TEST1, TEST2, TEST3 and TEST4 are test mode data. Care should be taken as these bits are not used, and must be set to High. – 24 – – 25 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 0 60 2.35µs (108fH) 40 1.0µs (46fH) 20 100 120 2.1µs (97fH) 1.8µs (83fH) 140 0.4µs (18fH) 4.38µs (202fH) 0.15µs (7fH) 0.55µs (26fH) 80 Note) The FRP polarity is not specified for each line and field. 1444 180 ODD LINE 0.3µs (14fH) 1.2µs (55fH) 6fH 2.0µs (92fH) 1.2µs (55fH) 160 12fH 200 220 240 260 NTSC (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: H XHD: H 280 300 320 340 360 380 Loop counter 1464fH Master Clock 46.07MHz CXD2443Q 80 2.35µs (108fH) 60 100 120 – 26 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A 4.38µs (202fH) 40 HSTB 20 4.38µs (202fH) 0 HSTA HSYNC MCK 1444 140 6fH 180 ODD LINE 160 NTSC (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: H XHD: H 12fH 12fH 200 220 240 260 280 300 320 340 360 380 Loop counter 1464fH Master Clock 46.07MHz CXD2443Q – 27 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 0 60 2.35µs (108fH) 40 1.0µs (46fH) 20 100 120 2.1µs (97fH) 1.8µs (83fH) 140 0.4µs (18fH) 4.35µs (200.5fH) 0.15µs (7fH) 0.55µs (26fH) 80 Note) The FRP polarity is not specified for each line and field. 1444 180 EVEN LINE 0.3µs (14fH) 1.16µs (53.5fH) 6fH 2.0µs (92fH) 1.2µs (55fH) 160 12fH 200 220 240 260 NTSC (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: H XHD: H 280 300 320 340 360 380 Loop counter 1464fH Master Clock 46.07MHz CXD2443Q 40 80 2.35µs (108fH) 60 100 120 – 28 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A 4.42µs (203.5fH) 20 HSTB 0 4.35µs (200.5fH) 1444 HSTA HSYNC MCK 140 6fH 180 EVEN LINE 160 NTSC (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: H XHD: H 12fH 12fH 200 220 240 260 280 300 320 340 360 380 Loop counter 1464fH Master Clock 46.07MHz CXD2443Q – 29 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 0 20 60 1.0µs (47fH) 100 0.15µs (7fH) 120 140 2.1µs (98fH) 1.8µs (84fH) 0.55µs (25fH) 80 4.99µs (234fH) 2.35µs (110fH) 40 Note) The FRP polarity is not specified for each line and field. 1480 ODD LINE 0.4µs (19fH) 2.0µs (93fH) 6fH 220 1.2µs (57fH) 200 0.3µs (14fH) 180 1.2µs (57fH) 160 12fH 240 260 PAL (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: H XHD: H 280 300 320 340 360 380 Master Clock 46.88MHz Loop counter 1500fH CXD2443Q 40 80 2.35µs (110fH) 60 100 120 140 – 30 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A 4.99µs (234fH) 20 HSTB 0 4.99µs (234fH) 1480 HSTA HSYNC MCK 160 ODD LINE 180 PAL (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: H XHD: H 200 6fH 220 12fH 12fH 240 260 280 300 320 340 360 380 Loop counter 1500fH Master Clock 46.88MHz CXD2443Q – 31 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 0 20 60 1.0µs (47fH) 100 0.15µs (7fH) 120 140 2.1µs (98fH) 1.8µs (84fH) 0.55µs (25fH) 80 4.96µs (232.5fH) 2.35µs (110fH) 40 Note) The FRP polarity is not specified for each line and field. 1480 180 200 6fH 220 0.3µs (14fH) 1.18µs (55.5fH) EVEN LINE 0.4µs (19fH) 2.0µs (93fH) 1.2µs (57fH) 160 12fH 240 260 PAL (4:3) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: H XHD: H 280 300 320 340 360 380 Loop counter 1500fH Master Clock 46.88MHz CXD2443Q 80 2.35µs (110fH) 60 100 120 140 – 32 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A 5.02µs (235.5fH) 40 HSTB 20 4.96µs (232.5fH) 0 HSTA HSYNC MCK 1480 160 EVEN LINE 180 PAL (4:3) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: H XHD: H 200 6fH 220 12fH 12fH 240 260 280 300 320 340 360 380 Loop counter 1500fH Master Clock 46.88MHz CXD2443Q – 33 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 0 20 80 100 140 0.55µs (34fH) 120 160 2.1µs (129fH) 1.8µs (111fH) 0.15µs (9fH) 4.54µs (279fH) 2.35µs (144fH) 60 1.0µs (61fH) 40 Note) The FRP polarity is not specified for each line and field. 1932 220 240 260 0.3µs (18fH) 1.2µs (74fH) 2.0µs (123fH) 1.2µs (74fH) 200 0.4µs (25fH) ODD LINE 6fH 180 NTSC (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: L XHD: H 12fH 280 300 320 340 360 380 Loop counter 1952fH Master Clock 61.43MHz CXD2443Q 40 80 2.35µs (144fH) 60 100 120 140 – 34 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A 4.54µs (279fH) 20 HSTB 0 4.54µs (279fH) 1932 HSTA HSYNC MCK 160 ODD LINE 6fH 180 NTSC (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: L XHD: H 200 220 240 260 12fH 12fH 280 300 320 340 360 380 Loop counter 1952fH Master Clock 61.43MHz CXD2443Q 80 – 35 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA 100 120 4.52µs (277.5fH) 140 6fH 220 240 260 0.3µs (18fH) 1.18µs (72.5fH) 2.0µs (123fH) 1.2µs (74fH) 200 0.4µs (25fH) 180 EVEN LINE 160 2.1µs (129fH) 1.8µs (111fH) Note) The FRP polarity is not specified for each line and field. 1.0µs (61fH) 2.35µs (144fH) 60 0.15µs (9fH) 40 XCLP2 20 0.55µs (34fH) 0 XCLP1 HSYNC MCK 1932 NTSC (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: H XWID: L XHD: H 12fH 280 300 320 340 360 380 Loop counter 1952fH Master Clock 61.43MHz CXD2443Q 40 80 2.35µs (144fH) 60 100 120 140 – 36 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A 4.57µs (280.5fH) 20 HSTB 0 4.52µs (277.5fH) 1932 HSTA HSYNC MCK 6fH 180 EVEN LINE 160 NTSC (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: H XWID: L XHD: H 200 220 240 260 12fH 12fH 280 300 320 340 360 380 Loop counter 1952fH Master Clock 61.43MHz CXD2443Q – 37 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 0 20 40 80 100 1.0µs (63fH) 5.17µs (323fH) 2.35µs (147fH) 60 140 0.15µs (10fH) 0.55µs (35fH) 120 Note) The FRP polarity is not specified for each line and field. 1980 180 ODD LINE 2.1µs (131fH) 1.8µs (112fH) 160 200 240 0.4µs (25fH) 6fH 2.0µs (125fH) 1.2µs (75fH) 220 300 1.2µs (75fH) 280 0.3µs (19fH) 260 PAL (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: L XHD: H 12fH 320 340 360 380 Loop counter 2000fH Master Clock 62.5MHz CXD2443Q 40 80 2.35µs (147fH) 60 100 120 140 160 180 – 38 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A ODD LINE 5.17µs (323fH) 20 HSTB 0 5.17µs (323fH) 1980 HSTA HSYNC MCK PAL (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: L XHD: H 200 6fH 220 240 260 280 300 12fH 12fH 320 340 360 380 Master Clock 62.5MHz Loop counter 2000fH CXD2443Q 40 80 2.35µs (147fH) 60 100 120 140 – 39 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA Note) The FRP polarity is not specified for each line and field. 1.0µs (63fH) 0.15µs (10fH) 5.14µs (321.5fH) 20 XCLP2 0 0.55µs (35fH) 1980 XCLP1 HSYNC MCK 180 200 EVEN LINE 2.1µs (131fH) 1.8µs (112fH) 160 240 6fH 0.4µs (25fH) 2.0µs (125fH) 1.2µs (75fH) 220 300 1.18µs (73.5fH) 280 0.3µs (19fH) 260 PAL (16:9) Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H SNSL: H NT-PL: L XWID: L XHD: H 12fH 320 340 360 380 Loop counter 2000fH Master Clock 62.5MHz CXD2443Q 40 80 2.35µs (147fH) 60 100 120 140 160 180 – 40 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A EVEN LINE 5.19µs (324.5fH) 20 HSTB 0 5.14µs (321.5fH) 1980 HSTA HSYNC MCK PAL (16:9) Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L SNSL: H NT-PL: L XWID: L XHD: H 200 6fH 220 240 260 280 300 340 12fH 12fH 320 360 380 Master Clock 62.5MHz Loop counter 2000fH CXD2443Q – 41 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 1936 1956 20 60 80 100 120 140 2.1µs (140fH) 160 200 220 1.2µs (80fH) 0.3µs (20fH) 180 6fH 0.4µs (26fH) ODD LINE 2.0µs (133fH) 1.2µs (80fH) 1.8µs (120fH) 3.84µs (256fH) 0.55µs (36fH) 40 0.15µs (9fH) 0.59µs (40fH) 1.0µs (67fH) 0 Note) The FRP polarity is not specified for each line and field. 1916 HD Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H XHD: L 240 12fH 260 280 300 320 340 Master Clock 66.69MHz Loop counter 1976fH CXD2443Q 0 0.59µs (40fH) 20 40 60 80 100 120 140 – 42 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A ODD LINE 3.84µs (256fH) 1956 HSTB 1936 3.84µs (256fH) 1916 HSTA HSYNC MCK HD Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L XHD: L 160 6fH 180 200 220 240 12fH 12fH 260 280 300 320 340 Loop counter 1976fH Master Clock 66.69MHz CXD2443Q – 43 – HDR PCG2 PCG1 FRP VCK ENB SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2A HCK1A HSTA XCLP2 XCLP1 HSYNC MCK 1936 1956 20 0.15µs (9fH) 0.59µs (40fH) 1.0µs (67fH) 0 60 80 100 120 2.1µs (140fH) 160 6fH EVEN LINE 0.4µs (26fH) 140 2.0µs (133fH) 1.2µs (80fH) 1.8µs (120fH) 3.82µs (254.5fH) 0.55µs (36fH) 40 Note) The FRP polarity is not specified for each line and field. 1916 220 1.18µs (78.5fH) 200 0.3µs (20fH) 180 HD Horizontal Direction Timing Chart HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL CP1, 2: LH PCGW1, 2: HH RGT: H DWN: H HPOL: H SLFR: H XHD: L 240 12fH 260 280 300 320 340 Master Clock 66.69MHz Loop counter 1976fH CXD2443Q 0 0.59µs (40fH) 20 40 60 80 100 120 140 – 44 – SH7B SH6B SH5B SH4B SH3B SH2B SH1B SH7A SH6A SH5A SH4A SH3A SH2A SH1A HCK2B HCK1B HCK2A HCK1A EVEN LINE 3.86µs (257.5fH) 1956 HSTB 1936 3.82µs (254.5fH) 1916 HSTA HSYNC MCK HD Horizontal Direction Timing Chart (B outputs) HP1, 2, 3, 4, 5, 6, 7, 8: LLLLLLLH SLSH1, 2, 3, 4: LLLL RGT: H DWN: H HPOL: H SLFR: H SL3B: L XHD: L 160 6fH 180 200 220 240 12fH 12fH 260 280 300 320 340 Loop counter 1976fH Master Clock 66.69MHz CXD2443Q – 45 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 483 485 484 520 0 10 21H 20 40 Display start 1 2 3 4 5 6 7 8 9 10 1112 Double-speed HSYNC input 30 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 510 50 NTSC (double-speed HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: H NT-PL: H XHD: H 60 70 CXD2443Q – 46 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 483 485 484 520 0 10 21H 30 40 Display start 1 2 3 4 5 6 7 8 9 10 11 12 ODD FIELD (standard HSYNC input) 20 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 510 50 NTSC (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: H XHD: H 60 70 CXD2443Q – 47 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 483 485 484 520 0 10 21H 30 40 Display start 1 2 3 4 5 6 7 8 9 10 1112 EVEN FIELD (standard HSYNC input) 20 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 510 50 NTSC (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: H XHD: H 60 70 CXD2443Q – 48 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 598 600 599 620 0 10 25H 20 Double-speed HSYNC input 30 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 610 40 Display start 1 2 3 4 5 6 7 8 9 10 1112 50 PAL (double-speed HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: H NT-PL: L XHD: H 60 70 CXD2443Q – 49 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 598 600 599 620 0 10 25H 30 ODD FIELD (standard HSYNC input) 20 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 610 40 Display start 1 2 3 4 5 6 7 8 9 10 1112 50 PAL (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H 60 70 CXD2443Q – 50 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 598 600 599 620 0 10 25H 30 EVEN FIELD (standard HSYNC input) 20 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 610 40 Display start 1 2 3 4 5 6 7 8 9 10 1112 50 PAL (standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H 60 70 CXD2443Q – 51 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 598 600 599 620 0 10 25H 30 ODD FIELD (standard HSYNC input) 20 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 610 40 Display start 1 2 3 4 5 6 7 8 9 10 1112 50 PAL (pulse eliminate display, standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: L SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H 60 70 CXD2443Q – 52 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 598 600 599 620 0 10 25H 30 EVEN FIELD (standard HSYNC input) 20 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 610 40 Display start 1 2 3 4 5 6 7 8 9 10 1112 50 PAL (pulse eliminate display, standard HSYNC input) Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: L SL3B: L VPOL: H SNSL: L NT-PL: L XHD: H 60 70 CXD2443Q – 53 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 1033 1035 1034 1120 0 10 45H 20 ODD FIELD 30 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 1110 50 60 Display start 1 2 3 4 5 6 7 8 9 10 1112 13 1415 16 1718 19 20 21 22 2324 25 26 2728 40 HD Vertical Direction Timing Chart VP1, 2, 3, 4: LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H XHD: L 70 CXD2443Q – 54 – VWB VWA FLDO PCG2 PCG1 FRP (1F inversed) FRP (1H inversed) VCK ENB HSTB HSTA HDR VST (BLK) HSYNC VD 563 573 45H 583 EVEN FIELD 593 Note) The FRP polarity is not specified for each line and field. (BLK) in the timing chart is a pulse indicated as a reference and is not a pulse output from pins. 515 517 516 553 613 623 Display start 518 520 522 524 526 528 530 532 534 536 538 540 542 544 519 521 523 525 527 529 531 533 535 537 539 541 543 545 603 HD Vertical Direction Timing Chart VP1, 2, 3, 4 : LLLH VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLLLLLL VM0J, 1J, 2J, 3J, 4J, 5J, 6J, 7J, 8J, 9J: LLLLHLLLL MA: H SL3B: L VPOL: H XHD: L 633 CXD2443Q – 55 – RSTR RCK RSTW WCK HSYNC MCK PAL RSTR RCK RSTW WCK HSYNC MCK NTSC SLBA = L 40 40 30 30 10 20 10 4.7µs (83fH) 0 10 1135fH, 10 910fH, 4.7µs (68fH) 0 Loop counter 20 Loop counter Line Double-Speed Timing Chart 20 20 40 30 40 Master Clock 30 Master Clock 1130 35.5MHz 900 28.6MHz 1140 910 2230 1780 2240 1790 2250 1800 2260 1810 4.7µs (83fH) 0 4.7µs (68fH) 0 10 10 20 20 30 30 40 40 CXD2443Q CXD2443Q Application Circuit RPD4 FPD4 +5V 1M 5.1k 1k 1M 0.1µ +5V 33k L D4 +5V 10k 50k 0.1µ 33µ 25V 3.3µ 16V 0.01µ 0.01µ 100p 33k +13V 10k 33µ 16V 50k L : NTSC 1.8µH PAL 1.2µH 1000p 0.01µ 3.3k µPD485505 (NEC) 47µ 16V 22p 0.01µ 0.1µ 0.1µ 47µ 16V 1M 1k 0.1µ 33k +13V 33k TC2 XCLP2 48 84 FPD2 XCLP1 47 FRP 49 85 PEO2 PCG2 46 86 PWM2 XRGT 45 87 RPD2 RGT 44 88 CKO2 HSTA 43 HSTB 42 CKI2 90 VSS 92 HCK2A 37 PWM3 ENB 36 96 FPD3 VCK 35 97 TC3 98 CKSL TEST8 33 99 CKI5 DWN 32 PCG1 31 50k TEST7 TEST6 TEST5 TEST4 TEST1 TEST3 TEST11 VSYNC HSYNC VDD FLDO 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PRE 8 SDAT 7 SCLK 6 SCTR 5 VSS 4 CKI1 3 2 CKO1 RPD1 1 100 HDR 50k TEST2 VST 34 PWM1 +5V +5V PEO3 95 PEO1 0.01µ HCK1A 38 94 FPD1 0.01µ 62p TC1 0.01µ 3.3k VSS 50k 33µ 25V 3.3µ 16V VSS 40 HCK2B 39 CKI3 93 RPD3 VDD 0.39µ XCLR VWB 10k HCK1B 41 91 CKO3 D2 10k SH2A SH1A VSS VDD SH3A SH4A SH5A SH7A SH6A SH1B TEST9 SH2B SH3B VSS SH4B SH5B SH6B SH7B RCK TEST10 WCK RSTR RSTW CKI4 CKO4 FPD4 PWM4 TC4 83 89 1000p XFRP 50 82 VSS VWA 5.1k RPD4 81 +5V 1M VSS FPD2 VDD PEO4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RPD2 +5V 33µ 16V 0.01µ 100p 33µ 16V 0.01µ 100p 33k 47µ 16V 1µ RPD3 0.1µ FPD3 RPD1 +5V +5V 1M 680 0.1µ 0.1µ 1M FPD1 Sync signal 1M 5.1k 1k 5.1k 1M Serial I/F 0.1µ +13V 33k 1000p 0.1µ +5V 0.33µ 33k +13V D3 47p 10k 50k 33k 1000p 33k D1 10k 33µ 25V 0.01µ OFF ON 50k 50k 3.3µ 16V 47p 10k 10k 0.01µ 0.68µ 3.3k 0.01µ 33µ 16V 0.01µ 100p 0.01µ 3.3µ 16V 33µ 25V 0.01µ 3.3k 0.01µ PRE D1, D2, D3, D4 : 1T363A (Sony) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 56 – 47µ 16V CXD2443Q Package Outline Unit: mm 100PIN QFP (PLASTIC) + 0.4 14.0 – 0.01 17.9 ± 0.4 15.8 ± 0.4 + 0.1 0.15 – 0.05 23.9 ± 0.4 + 0.4 20.0 – 0.1 A 0.65 + 0.35 2.75 – 0.15 ±0.12 M 0° to 15° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE SONY CODE QFP-100P-L01 EIAJ CODE ∗QFP100-P-1420-A JEDEC CODE – 57 – PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.4g