SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING SCDS025K – MAY 1995 – REVISED NOVEMBER 1998 D SN54CBTD3384 . . . JT OR W PACKAGE SN74CBTD3384 . . . DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Designed to Be Used in Level-Shifting Applications Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB, DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Package, Ceramic DIPs (JT), and Ceramic Chip Carriers (FK) 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND description The ’CBTD3384 devices provide ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switches allows connections to be made without adding propagation delay. A diode to VCC is integrated on the die to allow for level shifting between 5-V inputs and 3.3-V outputs. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE 1A1 1B1 1OE NC V CC SN54CBTD3384 . . . FK PACKAGE (TOP VIEW) These devices are organized as two 5-bit switches with separate output-enable (OE) inputs. When OE is low, the switch is on and port A is connected to port B. When OE is high, the switch is open and a high-impedance state exists between the two ports. 1A2 1B2 1B3 NC 1A3 1A4 1B4 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 2A4 2B4 2B3 NC 2A3 2A2 2B2 1B5 1A5 GND NC 2OE 2A1 2B1 The SN54CBTD3384 is characterized for operation over the full military temperature range from –55°C to 125°C. The SN74CBTD3384 is characterized for operation from –40°C to 85°C. 5 2B5 2A5 D D D NC – No internal connection FUNCTION TABLE (each 5-bit bus switch) INPUTS INPUTS/OUTPUTS 1OE 2OE 1B1–1B5 2B1–2B5 L L 1A1–1A5 2A1–2A5 L H 1A1–1A5 Z H L Z 2A1–2A5 H H Z Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING SCDS025K – MAY 1995 – REVISED NOVEMBER 1998 logic diagram (positive logic) 1A1 3 2 11 10 1A5 1OE 2A1 1B5 1 14 15 22 23 2A5 2OE 1B1 2B1 2B5 13 Pin numbers shown are for the DB, DBQ, DGV, DW, JT, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54CBTD3384 VCC VIH Supply voltage VIL TA Low-level control input voltage High-level control input voltage SN74CBTD3384 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Operating free-air temperature –55 125 –40 UNIT V V 0.8 V 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING SCDS025K – MAY 1995 – REVISED NOVEMBER 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54CBTD3384 TYP† MAX TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, See Figure 2 II = –18 mA II ICC VCC = 5.5 V, VCC = 5.5 V, VI = 5.5 V or GND IO = 0, VI = VCC or GND ∆ICC‡ Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci Control inputs Cio(OFF) VI = 3 V or 0 VO = 3 V or 0, ron§ VCC = 4.5 V OE = VCC VI = 0 II = 64 mA II = 30 mA SN74CBTD3384 TYP† MAX MIN UNIT –1.2 –1.2 V ±1 ±1 µA 1.5 1.5 mA 2.5 2.5 mA 3 3 pF 3.5 3.5 pF 5 5 7 5 5 7 Ω VI = 2.4 V, II = 15 mA 35 35 50 † Typical values are at VCC = 5 V, TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. switching characteristics over recommended ranges of supply voltage and operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54CBTD3384 PARAMETER FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A ten OE A or B 2.2 9.7 tdis OE A or B 1.5 8.6 MIN MAX SN74CBTD3384 MIN 0.25 MAX UNIT 0.25 ns 2.3 7 ns 1.7 5.3 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING SCDS025K – MAY 1995 – REVISED NOVEMBER 1998 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V tPLZ 3.5 V 1.5 V VOL + 0.3 V tPZH tPHL VOH Output Output Waveform 1 S1 at 7 V (see Note B) 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54CBTD3384, SN74CBTD3384 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING SCDS025K – MAY 1995 – REVISED NOVEMBER 1998 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 4 TA = 25°C 100 µA 3.75 3.5 6 mA 12 mA 3.5 100 µA 3.25 6 mA 12 mA 3 24 mA 3.25 VOH – Output Voltage High – V 3.75 24 mA 3 2.75 2.5 2.25 2 1.75 1.5 4.5 2.75 2.5 2.25 2 1.75 4.75 5 5.25 5.5 5.75 1.5 4.5 4.75 VCC – Supply Voltage – V 5 5.25 5.5 5.75 VCC – Supply Voltage – V OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE 4 TA = 0°C 3.75 VOH – Output Voltage High – V VOH – Output Voltage High – V TA = 85°C 3.5 100 µA 3.25 6 mA 12 mA 3 24 mA 2.75 2.5 2.25 2 1.75 1.5 4.5 4.75 5 5.25 5.5 VCC – Supply Voltage – V 5.75 Figure 2. VOH Values POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 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