TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 LOW-POWER 16-CHANNEL CONSTANT-CURRENT LED SINK DRIVER FEATURES 1 • • • • • • 16 Constant-Current Output Channels Constant Output Current Invariant to Load Voltage Change Excellent Output Current Accuracy: – Between Channels: < ±4% (Max) – Between ICs: < ±6% (Max) Constant Output Current Range: 3 mA to 45 mA Output Current Adjusted By External Resistor Fast Response of Output Current, OE (Min): 100 ns • • • • • 30-MHz Clock Frequency Schmitt-Trigger Inputs 3.3-V to 5-V Supply Voltage Thermal Shutdown for Overtemperature Protection ESD Performance: 1-kV HBM APPLICATIONS • • • • • Gaming Machine / Entertainment General LED Applications LED Display Systems Signs LED Lighting White Goods DESCRIPTION/ORDERING INFORMATION The TLC5925 is designed for LED displays and LED lighting applications. The TLC5925 contains a 16-bit shift register and data latches, which convert serial input data into parallel output format. At the TLC5925 output stage, 16 regulated-current ports provide uniform and constant current for driving LEDs within a wide range of VF variations. Used in system design for LED display applications (e.g., LED panels), the TLC5925 provides great flexibility and device performance. Users can adjust the output current from 3 mA to 45 mA through an external resistor, Rext, which gives flexibility in controlling the light intensity of LEDs. TLC5925 is designed for up to 17 V at the output port. The high clock frequency, 30 MHz, also satisfies the system requirements of high-volume data transmission. The serial data is transferred into TLC5925 via SDI, shifted in the shift register, and transferred out via SDO. LE can latch the serial data in the shift register to the output latch. OE enables the output drivers to sink current. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING PW Reel of 2000 TLC5925IPWR Y5925 W-SOIC – DW Reel of 2000 TLC5925IDWR PREVIEW SSOP – DBQ Reel of 2000 TLC5925IDBQR TLC5925I For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TLC5925 SLVS765 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com BLOCK DIAGRAM OUT0 R-EXT OUT1 OUT14 OUT15 I/O REGULATOR VDD 8 OUTPUT DRIVER OE CONTROL LOGIC 16 16 16-BIT OUTPUT LATCH LE CONFIGURATION LATCHES 16 CLK 8 SDI 16-BIT SHIFT REGISTER SDO 16 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 DBQ, DW, OR PWP PACKAGE (TOP VIEW) GND SDI CLK LE OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 1 24 2 23 3 22 4 5 21 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VDD R-EXT SDO OE OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 Terminal Descriptions TERMINAL NAME DESCRIPTION CLK Clock input for data shift on rising edge GND Ground for control logic and current sink LE Data strobe input Serial data is transferred to the respective latch when LE is high. The data is latched when LE goes low. LE has an internal pull-down resistor. OE Output enable When OE is active (low), the output drivers are enabled. When OE is high, all output drivers are turned OFF (blanked). OE has an internal pullup resistor. OUT0–OUT15 R-EXT Constant-current outputs Input used to connect an external resistor (Rext) for setting output currents SDI Serial-data input to the Shift register SDO Serial-data output to the following SDI of next driver IC or to the microcontroller VDD Supply voltage Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 3 TLC5925 SLVS765 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com Timing Diagram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK OE 1 LE 0 SDI off OUT0 on off OUT1 on off OUT2 on off OUT3 on off OUT15 on SDO Don't care Figure 1. Timing Diagram Truth Table in Normal Operation 4 CLK LE OE SDI OUT0...OUT15...OUT15 SDO ↑ H L Dn Dn...Dn – 7...Dn – 15 Dn – 15 ↑ L L Dn + 1 No change Dn – 14 ↑ H L Dn + 2 Dn + 2...Dn – 5...Dn – 13 Dn – 13 ↓ X L Dn + 3 Dn + 2...Dn – 5...Dn – 13 Dn – 13 ↓ X H Dn + 3 off Dn – 13 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN MAX 0 7 V Input voltage –0.4 VDD + 0.4 V VO Output voltage –0.5 20 V IOUT Output current 45 mA IGND GND terminal current 750 mA TA Free-air operating temperature range –40 125 °C TJ Operating junction temperature range –40 150 °C Tstg Storage temperature range –55 150 °C MAX UNIT VDD Supply voltage VI UNIT Power Dissipation and Thermal Impedance MIN PD Power dissipation Mounted on JEDEC 4-layer board (JESD 51-7), No airflow, TA = 25°C, TJ = 125°C Mounted on JEDEC 1-layer board (JESD 51-3), No airflow θJA Thermal impedance, junction to free air Mounted on JEDEC 4-layer board (JESD 51-7), No airflow DBQ package 1.6 DW package 2.2 PW package 1.1 DBQ package 99.8 DW package 80.5 PW package 118.8 DBQ package 61.0 DW package 45.5 PW package 87.9 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 W °C/W 5 TLC5925 SLVS765 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS MIN MAX 3 5.5 UNIT V 17 V VDD Supply voltage VO Output voltage OUT0 to OUT15 IO Output current DC test circuit IOH High-level output current SDO IOL Low-level output current SDO VIH High-level input voltage CLK, OE, LE, and SDI 0.7 × VDD VDD V VIL Low-level input voltage CLK, OE, LE, and SDI GND 0.3 × VDD V tR Rise Time CLK 500 ns tF Fall Time CLK 500 ns MAX UNIT VO ≥ 0.6 V 3 VO ≥ 1 V 45 –1 mA mA 1 mA Recommended Timing VDD = 3 V to 5.5 V (unless otherwise noted) TEST CONDITIONS MIN tw(L) LE pulse duration 15 ns tw(CLK) CLK pulse duration 15 ns tw(OE) OE pulse duration 300 ns tsu(D) Setup time for SDI 3 ns th(D) Hold time for SDI 2 ns tsu(L) Setup time for LE 5 ns th(L) Hold time for LE 5 fCLK Clock frequency 6 Cascade operation Submit Documentation Feedback ns 30 MHz Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 Electrical Characteristics VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP UNIT Input voltage VO Output voltage IO Output current IOH High-level output current, source IOL Low-level output current, sink VIH High-level input voltage 0.7 × VDD VDD VIL Low-level input voltage GND 0.3 × VDD Ileak Output leakage current VOH = 17 V VOH High-level output voltage SDO, IOL = –1 mA VOL Low-level output voltage SDO, IOH = 1 mA Output current 1 VOUT = 0.6 V, Rext = 1680 Ω 13 Output current error, die-die IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±3 ±6 % Output current error, channel-to-channel IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±1.5 ±4 % Output current 2 VO = 0.8 V, Rext = 840 Ω 26 Output current error, die-die IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±3 ±6 % Output current error, channel-to-channel IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±1.5 ±4 % Output current vs output voltage regulation VO = 1 V to 3 V, IO = 13 mA ±0.1 Pullup resistance OE 500 kΩ Pulldown resistance LE 500 kΩ IO(1) IO(2) IOUT vs VOUT 3 MAX VDD VO ≥ 0.6 V -1 Restart temperature hysteresis TJ = 25°C CIN (1) 2 VDD – 0.4 Supply current Input capacitance µA mA %/V ±1 175 V mA 200 °C °C 7 10 Rext = 1680 Ω 9 12 Rext = 840 Ω 11 13 VI = VDD or GND, CLK, SDI, SDO, OE V V 0.4 15 Rext = Open IDD 0.5 TJ = 125°C 150 mA mA 1 (1) Overtemperature shutdown V 45 VDD = 3.0 V to 5.5 V, IO = 13 mA to 45 mA Thys V 17 3 VO ≥ 1 V Tsd 5.5 10 mA pF Specified by design Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 7 TLC5925 SLVS765 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com Electrical Characteristics VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP UNIT Input voltage VO Output voltage IO Output current IOH High-level output current, source IOL Low-level output current, sink VIH High-level input voltage 0.7 × VDD VDD VIL Low-level input voltage GND 03 × VDD Ileak Output leakage current VOH = 17 V VOH High-level output voltage SDO, IOL = –1 mA VOL Low-level output voltage SDO, IOH = 1 mA Output current 1 VOUT = 0.6 V, Rext = 1680 Ω 13 Output current error, die-die IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±3 ±6 % Output current error, channel-to-channel IOL = 13 mA, VO = 0.6 V, Rext = 1680 Ω, TJ = 25°C ±1.5 ±4 % Output current 2 VO = 0.8 V, Rext = 840 Ω 26 Output current error, die-die IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±3 ±6 % Output current error, channel-to-channel IOL = 26 mA, VO = 0.8 V, Rext = 840 Ω, TJ = 25°C ±1.5 ±4 % Output current vs output voltage regulation VO = 1 V to 3 V , IO = 26 mA ±0.1 Pullup resistance OE 500 kΩ Pulldown resistance LE 500 kΩ IO(1) IO(2) IOUT vs VOUT 3 MAX VDD VO ≥ 0.6 V -1 Restart temperature hysteresis TJ = 25°C CIN (1) 8 2 VDD – 0.4 Supply current Input capacitance µA mA %/V ±1 175 V mA 200 °C °C 9 11 Rext = 1680 Ω 12 14 Rext = 840 Ω 14 16 VI = VDD or GND, CLK, SDI, SDO, OE V V 0.4 15 Rext = Open IDD 0.5 TJ = 125°C 150 mA mA 1 (1) Overtemperature shutdown V 45 VDD = 3.0 V to 5.5 V, IO = 13 mA to 45 mA Thys V 17 3 VO ≥ 1 V Tsd 5.5 10 mA pF Specified by design Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 Switching Characteristics VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted) MIN TYP MAX tPLH1 Low-to-high propagation delay time, CLK to OUTn PARAMETER TEST CONDITIONS 30 45 60 UNIT ns tPLH2 Low-to-high propagation delay time, LE to OUTn 30 45 60 ns tPLH3 Low-to-high propagation delay time, OE to OUTn 30 45 60 ns tPLH4 Low-to-high propagation delay time, CLK to SDO 30 40 ns tPHL1 High-to-low propagation delay time, CLK to OUTn 40 65 100 ns tPHL2 High-to-low propagation delay time, LE to OUTn 40 65 100 ns tPHL3 High-to-low propagation delay time, OE to OUTn 40 65 100 ns tPHL4 High-to-low propagation delay time, CLK to SDO 30 40 ns tw(CLK) Pulse duration, CLK tw(L) Pulse duration LE tw(OE) Pulse duration, OE th(D) 15 ns 15 ns 300 ns Hold time, SDI 2 ns tsu(D) Setup time, SDI 3 ns th(L) Hold time, LE 5 ns tsu(L) Setup time, LE 5 ns (1) tr Rise time, CLK tf Fall time, CLK (1) tor Rise time, outputs (off) tof Rise time, outputs (on) fCLK Clock frequency (1) VIH = VDD, VIL = GND, Rext = 840 Ω, VL = 4 V, RL = 88 Ω, CL = 10 pF Cascade operation 500 ns 500 ns ns 35 50 70 15 50 120 ns 30 MHz If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 9 TLC5925 SLVS765 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com Switching Characteristics VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted) MIN TYP MAX tPLH1 Low-to-high propagation delay time, CLK to OUTn PARAMETER TEST CONDITIONS 20 35 55 UNIT ns tPLH2 Low-to-high propagation delay time, LE to OUTn 20 35 55 ns tPLH3 Low-to-high propagation delay time, OE to OUTn 20 35 55 ns tPLH4 Low-to-high propagation delay time, CLK to SDO 20 30 ns tPHL1 High-to-low propagation delay time, CLK to OUTn 15 28 42 ns tPHL2 High-to-low propagation delay time, LE to OUTn 15 28 42 ns tPHL3 High-to-low propagation delay time, OE to OUTn 15 28 42 ns tPHL4 High-to-low propagation delay time, CLK to SDO 20 30 ns tw(CLK) Pulse duration, CLK tw(L) Pulse duration LE tw(OE) Pulse duration, OE th(D) 10 ns 10 ns 200 ns Hold time, SDI 2 ns tsu(D) Setup time, SDI 3 ns th(L) Hold time, LE 5 ns tsu(L) Setup time, LE 5 ns (1) tr Rise time, CLK tf Fall time, CLK (1) tor Rise time, outputs (off) tof Rise time, outputs (on) fCLK Clock frequency (1) 10 VIH = VDD, VIL = GND, Rext = 840 Ω, VL = 4 V, RL = 88 Ω, CL = 10 pF Cascade operation 500 ns 500 ns ns 25 45 65 7 12 20 ns 30 MHz If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 PARAMETER MEASUREMENT INFORMATION IDD VDD OE IIH, IIL IOUT OUT0 CLK LE OUT15 SDI VIH, VIL R-EXT GND SDO Iref Figure 2. Test Circuit for Electrical Characteristics IDD IOUT VDD VIH, VIL OE CLK LE Function Generator OUT0 OUT15 RL CL SDI Logic input waveform VIH = VDD VIL = 0V R-EXT GND SDO Iref CL VL Figure 3. Test Circuit for Switching Characteristics Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 11 TLC5925 SLVS765 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) tw(CLK) CLK 50% tsu(D) SDI 50% 50% th(D) 50% 50% tPLH4, tPHL4 50% SDO tw(L) 50% LE tsu(L) th(L) OE Low OE LOW tPLH2, tPHL2 Output off OUTn 50% Output on tPLH1, tPHL1 tw(OE) HIGH 50% OE Pulsed OE 50% tPLH3 tPHL3 Output off 90% OUTn 90% 50% 50% 10% 10% tof tor Figure 4. Normal Mode Timing Waveforms 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 APPLICATION INFORMATION Operating Principles Constant Current In LED display applications, TLC5925 provides nearly no current variations from channel to channel and from IC to IC. While IOUT ≤ 45 mA, the maximum current skew between channels is less than ±5% and between ICs is less than ±6%. Adjusting Output Current TLC5925 sets IOUT based on the external resistor Rext. Users can follow the below formulas to calculate the target output current IOUT,target in the saturation region: IOUT,target = (1.21 V / Rext) × 18, where Rext is the external resistance connected between R-EXT and GND. IOUT – mA Therefore, the default current is approximately 26 mA at 840 Ω and 13 mA at 1680 Ω. The default relationship after power on between IOUT,target and Rext is shown in Figure 5. 45 40 35 30 25 20 15 10 5 0 0 500 1000 1500 2000 Rext – 8W 2500 3000 3500 4000 Figure 5. Default Relationship Curve Between IOUT,target and Rext After Power Up Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 13 TLC5925 SLVS765 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com Propagation Delay Times Figure 6. CLK to OUT7 Figure 7. OE to OUT1 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 TLC5925 www.ti.com .............................................................................................................................................................................................. SLVS765 – OCTOBER 2008 Figure 8. OE to OUT7 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TLC5925 15 PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC5925IDBQR ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5925IDBQRG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC5925IDWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) Cu NIPDAU Level-1-260C-UNLIM TLC5925IDWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) Cu NIPDAU Level-1-260C-UNLIM TLC5925IPWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC5925IPWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Oct-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLC5925IDBQR SSOP/ QSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC5925IPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Oct-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5925IDBQR SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 TLC5925IPWR TSSOP PW 24 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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