SN55183-SP www.ti.com ....................................................................................................................................................................................................... SLLS932 – JULY 2008 RAD-TOLERANT CLASS V, DUAL DIFFERENTIAL LINE DRIVER FEATURES 1 • • • • • 1A 1B 1C 1D 1Y 1Z GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2D 2C 2B 2A 2Y 2Z SN55183 . . . FK PACKAGE (TOP VIEW) 1C NC 1D NC 1Y 4 3 2 1 20 19 18 5 6 17 16 7 8 15 14 9 10 11 12 13 2C NC 2B NC 2A 1Z GND NC 2Z 2Y • • SN55183 . . . J OR W PACKAGE (TOP VIEW) Single 5-V Supply Differential Line Operation Dual Channels TTL Compatibility Short-Circuit Protection of Outputs Output Clamp Diodes to Terminate Line Transients High-Current Outputs Quad Inputs Single-Ended or Differential AND/NAND Outputs Designed for Use With Dual Differential Drivers SN55182 and SN75182 Designed to Be Interchangeable With National Semiconductor DS7830 and DS8830 Rad-Tolerant: >40 KRad(Si) TID QML-V Qualified, SMD 5962-79008 1B 1A NC VCC 2D • • • • • • NC − No internal connection DESCRIPTION The SN55183 dual differential line driver is designed to provide differential output signals with high current capability for driving balanced lines, such as twisted pair, at normal line impedances without high power dissipation. The device can be used as a TTL expander/phase splitter, because the output stages are similar to TTL totem-pole outputs. The driver is of monolithic single-chip construction, and both halves of the dual circuits use common power supply and ground terminals. The SN55183 is characterized for operation over the full military temperature range of –55°C to 125°C. PACKAGING/ORDERING INFORMATION (1) TA –55°C to 125°C (1) (2) PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING J package 5962-7900801VCA 5962-7900801VCA W package 5962-7900801VDA 5962-7900801VDA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN55183-SP SLLS932 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com Logic Symbol† 1A 1B 1C 1D 2A 2B 2C 2D 1 & 5 2 3 6 4 1Y 1Z 10 9 11 12 8 13 2Y 2Z † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the J and W packages. Logic Diagram (Positive Logic) 1 1A 5 1Y 2 1B 1C 3 6 1Z 4 1D 10 2A 9 2Y 11 2B 2C 12 8 13 2Z 2D Positive logic: y = ABCD, Z = ABCD Pin numbers shown are for the J and W packages. 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP SN55183-SP www.ti.com ....................................................................................................................................................................................................... SLLS932 – JULY 2008 Schematic (Each Driver) 14 VCC 545 Ω V 2 kΩ 3 kΩ 9Ω 6, 8 Z 1, 10 A 300 Ω 2, 11 B 545 Ω V 3, 12 C 4 kΩ 3.2 kΩ 3 kΩ 9Ω 4, 13 D 5, 9 Y 300 Ω 2 kΩ 7 GND Resistor values shown are nominal. Pin numbers shown are for the J and W packages. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage (2) VI Input voltage Duration of output short circuit (3) Continuous total power dissipation Tstg (2) (3) UNIT 7 V 5.5 V 1 s See Dissipation Ratings Table Storage temperature range –65 Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds (1) MAX J or W package 150 °C 300 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Not more than one output should be shorted to ground at any one time. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP 3 SN55183-SP SLLS932 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com DISSIPATION RATINGS (1) PACKAGE (1) TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 125°C POWER RATING J 1375 mW 11.0 mW/°C 880 mW 275 mW W 1000 mW 8.0 mW/°C 640 mW 200 mW SN55183 chips are alloy mounted. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX 4.5 5 5.5 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –40 mA IOL Low-level output current 40 mA TA Operating free-air temperature 125 °C 4 2 –55 Submit Documentation Feedback V V Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP SN55183-SP www.ti.com ....................................................................................................................................................................................................... SLLS932 – JULY 2008 ELECTRICAL CHARACTERISTICS over recommended ranges of VCC and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN IOH = –0.8 mA 2.4 IOH = –40 mA 1.8 TYP (1) MAX UNIT VOH High-level output voltage Y (AND) outputs VIH = 2 V VOL Low-level output voltage Y (AND) outputs VIL = 0.8 V VOH High-level output voltage Z (NAND) outputs VIL = 0.8 V VOL Low-level output voltage Z (NAND) outputs VIH = 2 V IIH High-level input current VIH = 2.4 V 120 µA II Input current at maximum input voltage VIH = 5.5 V 2 mA IIL Low-level input current VIL = 0.4 V –4.8 mA –100 –120 mA 10 18 mA (2) IOS Short-circuit output current ICC Supply current (average per driver) (1) (2) (3) IOL = 32 mA 0.2 IOL = 40 mA 0.22 IOH = –0.8 mA 2.4 IOH = –40 mA 1.8 0.2 IOL = 40 mA 0.22 VCC = 5 V, TA =125°C VCC = 5 V, All inputs at 5 V, –40 No load 0.4 V V 3.3 IOL = 32 mA (3) V 3.3 0.4 V All typical values are at VCC = 5 V, TA = 25°C. Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second. TA = 125°C is applicable to SN55183 only. SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8 12 ns tPLH Propagation delay time, low- to high-level Y output AND gates CL = 15 pF, See FIgure 1(a) tPHL Propagation delay time, high- to low-level Y output AND gates CL = 15 pF, See FIgure 1(a) 12 18 ns tPLH Propagation delay time, low- to high-level Z output NAND gates CL = 15 pF, See FIgure 1(a) 6 12 ns tPHL Propagation delay time, high- to low-level Z output NAND gates CL = 15 pF, See FIgure 1(a) 6 8 ns tPLH Propagation delay time, low- to high-level differential output Y output with respect to Z output, RL = 100 Ω in series with 5000 pF, See Figure 1(b) 9 16 ns tPHL Propagation delay time, high- to low-level differential output Y output with respect to Z output, RL = 100 Ω in series with 5000 pF, See Figure 1(b) 8 16 ns Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP 5 SN55183-SP SLLS932 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION 2.5 V Input VCC = ±5 V Input 1.5 V 1.5 V 0V tPLH Pulse Generator (see Note A) CL = 15 pF (see Note B) CL = 15 pF (see Note B) Y Output tPHL VOH Y Output 1.5 V 1.5 V VOL tPHL Z Output VOH Z Output TEST CIRCUIT tPLH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS (a) OUTPUTS Y AND Z Input VCC = 5 V 3V Y Output Pulse Generator (see Note A) Input 1.5 V 1.5 V 100 W 0V tPLH 5000 pF Z Output tPHL VYS Differential Output Voltage 0V 0V −VYS TEST CIRCUIT VOLTAGE WAVEFORMS (b) DIFFERENTIAL OUTPUT NOTES: A. The pulse generators have the following characteristics: ZO = 50 Ω, tr ≤ 10 ns, tf ≤ 10 ns, tw = 0.5 µs, PRR ≤ 1 MHz. B. CL includes probe and jig capacitance. C. Waveforms are monitored on an oscilloscope with ri ≥ 1 MΩ. Figure 1. Test Circuits and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP SN55183-SP www.ti.com ....................................................................................................................................................................................................... SLLS932 – JULY 2008 TYPICAL CHARACTERISTICS (1) ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC = 5 V VO = 1.5 V V T − Input Threshold Voltage − V 2.2 2 1.8 1.6 4 VIH min V OH − High-Level Output Voltage − V 2.4 NAND Gate 1.4 AND Gate 1.2 1 VIL max 0.8 0.6 0.4 −75 −25 0 25 50 75 100 50-Ω Load 3 2.5 TA = 25°C 2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.5 1 125 0 −20 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VOL − Low-Level Output Voltage − V V OD − Differential Output Voltage − V (1) ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ VCC = 5 V TA = 125°C TA = 25°C 2 TA = −55°C 1 75 −100 −120 −140 −160 3 VCC = 5 V 50 −80 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 25 −60 Figure 3. DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL OUTPUT CURRENT 0 −40 IOH − High-Level Output Current − mA Figure 2. 0 TA = − 55°C TA = 125°C 0.5 TA − Free-Air Temperature − °C 3 VCC = 5 V 200-Ω Load 100-Ω Load 3.5 0 −50 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE 100 125 2 TA = 25°C TA = −55°C 1 TA = 125°C 0 0 20 40 60 80 100 120 140 160 180 200 IOD − Differential Output Current − mA IOL − Low-Level Output Current − mA Figure 4. Figure 5. Operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP 7 SN55183-SP SLLS932 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (2) (continued) TOTAL POWER DISSIPATION (BOTH DRIVERS) vs FREQUENCY PROPAGATION DELAY TIME (DIFFERENTIAL OUTPUT) vs FREE-AIR TEMPERATURE 20 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 240 15 10 220 PD − Total Power Dissipation − mW t pd − Propagation Delay Time − ns VCC = 5 V See Figure 1(b) tPLH tPHL 5 200 180 ÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁ ÎÎÎÎÎÎÎ VCC = 5 V No Load Input: 3-V Square Wave TA = 25°C 160 140 120 100 80 60 0 −75 −50 −25 0 25 50 75 100 125 40 0.1 TA − Free-Air Temperature − °C Figure 6. 8 Submit Documentation Feedback 0.4 1 4 10 40 100 f − Frequency − MHz Figure 7. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP SN55183-SP www.ti.com ....................................................................................................................................................................................................... SLLS932 – JULY 2008 APPLICATION INFORMATION VCC = 5 V VCC = 5 V 1/2 ’183 Inputs A B C D Inverting Input Z 1/2 ’182 0.002 µF (see Note A) Output RT Resp Time Cont Y Twisted Pair 100 pF (see Note B) Noninverting Input Strobe GND GND NOTES: A. When the inputs are open circuited, the output is high. A capacitor may be used for dc isolation of the line-terminating resistor. At the frequency of operation, the impedance of the capacitor should be relatively small. Example: let f = 5 MHz C = 0.002 µF 1 1 Z(circuit) + + 2pfC 2pǒ5 106Ǔǒ0.002 Z(circuit) [ 16W 10*6Ǔ B. Use of a capacitor to control response time is optional. Figure 8. Transmission of Digital Data Over Twisted-Pair Line Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN55183-SP 9 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 5962-7900901VCA ACTIVE CDIP J Pins Package Eco Plan (2) Qty 14 1 TBD Lead/Ball Finish A42 MSL Peak Temp (3) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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