TI PCA9544APWT

4-CHANNEL
www.ti.com
I2C
PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
FEATURES
•
•
•
•
•
•
•
•
•
•
•
1-of-4 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Four Active-Low Interrupt Inputs
Active-Low Interrupt Output
Three Address Pins, Allowing up to Eight
Devices on the I2C Bus
Channel Selection Via I2C Bus
Power Up With All Switch Channels
Deselected
Low RON Switches
Allows Voltage-Level Translation Between
1.8-V, 2.5-V, 3.3-V, and 5-V Buses
No Glitch on Power Up
Supports Hot Insertion
•
•
•
•
•
•
Low Standby Current
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
5.5-V Tolerant Inputs
0 to 400-kHz Clock Frequency
Latch-Up Performance Exceeds 100 mA Per
JESD 78
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The PCA9544A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair
fans out to four downstream pairs, or channels. One SCL/SDA pair can be selected at a time, and this is
determined by the contents of the programmable control register. Four interrupt inputs (INT3–INT0), one for
each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND of the four interrupt
inputs.
A power-on reset function puts the registers in their default state and initializes the I2C state machine, with no
channel selected.
The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high
voltage, which will be passed by the PCA9544A. This allows the use of different bus voltages on each pair, so
that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. External
pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.
ORDERING INFORMATION
PACKAGE (1)
TA
Reel of 3000
PCA9544ARGWR
PREVIEW
QFN – RGY
Reel of 1000
PCA9544ARGYR
PD544A
Tube of 25
PCA9544ADW
Reel of 2000
PCA9544ADWR
Reel of 250
PCA9544ADWT
Tube of 70
PCA9544APW
Reel of 2000
PCA9544APWR
Reel of 250
PCA9544APWT
Reel of 2000
PCA9544ADGVR
PD544A
Reel of 250
PCA9544ADGVT
PREVIEW
VFBGA – GQN
Reel of 1000
PCA9544AGQNR
PD544A
VFBGA – ZQN (Pb-free)
Reel of 1000
PCA9544AZQNR
PD544A
TSSOP – PW
TVSOP – DGV
(1)
TOP-SIDE MARKING
QFN – RGW
SOIC – DW
–40°C to 85°C
ORDERABLE PART NUMBER
PCA9544A
PREVIEW
PD544A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
17
5
16
6
15
7
14
8
13
9
12
10
11
1
15 INT
2
14 SC3
3
13 SD3
4
12 INT3
11
5
6
7
SC2
8 9 10
A1
A2
INT0
SD0
SC0
INT1
SD1
SC1
2
3
4
5
6
7
8
9
VCC
4
20 19 18 17 16
A2
INT0
SD0
SC0
INT1
1
20
10
11
INT2
18
A0
3
VCC
SDA
SCL
INT
SC3
SD3
INT3
SC2
SD2
INT2
GND
19
SDA
SCL
20
2
VCC
1
RGY PACKAGE
(TOP VIEW)
SD1
SC1
GND
INT2
SD2
A0
A1
A2
INT0
SD0
SC0
INT1
SD1
SC1
GND
RGW PACKAGE
(TOP VIEW)
A1
A0
DGV, DW, OR PW PACKAGE
(TOP VIEW)
19
18
17
16
15
14
13
12
SDA
SCL
INT
SC3
SD3
INT3
SC2
SD2
TERMINAL FUNCTIONS
NO.
2
NAME
FUNCTION
DGV, DW, PW,
AND RGY
RGW
1
19
A0
Address input 0. Connect directly to VCC or ground.
2
20
A1
Address input 1. Connect directly to VCC or ground.
3
1
A2
Address input 2. Connect directly to VCC or ground.
4
2
INT0
Active-low interrupt input 0. Connect to VCC through a pullup
resistor.
5
3
SD0
Serial data 0. Connect to VCC through a pullup resistor.
6
4
SC0
Serial clock 0. Connect to VCC through a pullup resistor.
7
5
INT1
Active-low interrupt input 1. Connect to VCC through a pullup
resistor.
8
6
SD1
Serial data 1. Connect to VCC through a pullup resistor.
9
7
SC1
Serial clock 1. Connect to VCC through a pullup resistor.
10
8
GND
Ground
11
9
INT2
Active-low interrupt input 2. Connect to VCC through a pullup
resistor.
12
10
SD2
Serial data 2. Connect to VCC through a pullup resistor.
13
11
SC2
Serial clock 2. Connect to VCC through a pullup resistor.
14
12
INT3
Active-low interrupt input 3. Connect to VCC through a pullup
resistor.
15
13
SD3
Serial data 3. Connect to VCC through a pullup resistor.
16
14
SC3
Serial clock 3. Connect to VCC through a pullup resistor.
17
15
INT
Active-low interrupt output. Connect to VCC through a pullup
resistor.
18
16
SCL
Serial clock line. Connect to VCC through a pullup resistor.
19
17
SDA
Serial data line. Connect to VCC through a pullup resistor.
20
18
VCC
Supply power
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I2C
PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
TERMINAL ASSIGNMENTS
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
1
2
3
4
A
A1
A0
VCC
SDA
A
B
INT0
INT
A2
SCL
B
C
SC0
SD0
SD3
SC3
C
D
SD1
SC2
INT1
INT3
E
GND
SC1
INT2
SD2
D
E
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
BLOCK DIAGRAM
PCA9544A
SC0
SC1
SC2
SC3
SD0
SD1
6
9
13
16
5
8
12
SD2
SD3
GND
VCC
SCL
SDA
INT0
INT1
INT2
INT3
15
Switch Control Logic
10
20
Power-on Reset
18
19
1
Input Filter
I2C
4
7
11
14
2
Bus Control
Interrupt Logic
Pin numbers shown are for DGV, DW, PW, and RGY packages.
4
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3
Output
Filter
17
A0
A1
A2
INT
4-CHANNEL
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I2C
PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9544A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address
1
1
0
1
A2
A1
A0 R/W
Hardware
Selectable
Fixed
Figure 1. PCA9544A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
Control Register
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9544A,
which is stored in the control register. If multiple bytes are received by the PCA9544A, it saves the last byte
received. This register can be written and read via the I2C bus.
Channel-Selection Bits
(Read/Write)
Interrupt Bits
(Read Only)
7
6
5
4
INT3 INT2 INT1 INT0
3
2
1
0
X
B2
B1
B0
Enable Bit
INT0
INT1
INT2
INT3
Figure 2. Control Register
Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register
(see Table 1). This register is written after the PCA9544A has been addressed. The three LSBs of the control
byte are used to determine which channel (or channels) is to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time
of connection. A stop condition always must occur right after the acknowledge cycle.
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1)
(1)
INT3
INT2
INT1
INT0
D3
B2
B1
B0
COMMAND
X
X
X
X
X
0
X
X
No channel selected
X
X
X
X
X
1
0
0
Channel 0 enabled
X
X
X
X
X
1
0
1
Channel 1 enabled
X
X
X
X
X
1
1
0
Channel 2 enabled
X
X
X
X
X
1
1
1
Channel 3 enabled
0
0
0
0
0
0
0
0
No channel selected,
power-up default state
Only one channel may be selected at a time.
Interrupt Handling
The PCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. When
an interrupt is generated by any device, it is detected by the PCA9544A, and the interrupt output is driven low.
The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (see
Table 2).
Bits 4–7 of the control register correspond to channels 0–3 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the
control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0
causes bit 4 of the control register to be set on the read. The master then can address the PCA9544A and read
the contents of the control register to determine which channel contains the device generating the interrupt. The
master can reconfigure the PCA9544A to select this channel and locate the device generating the interrupt and
clear it. Once the device responsible for the interrupt clears, the interrupt clears.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC.
Table 2. Control Register Read (Interrupt) (1)
INT3
INT2
INT1
X
X
X
X
X
0
1
(1)
6
X
0
1
X
D3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
INT0
0
1
COMMAND
No interrupt on channel 0
Interrupt on channel 0
No interrupt on channel 1
Interrupt on channel 1
No interrupt on channel 2
Interrupt on channel 2
No interrupt on channel 3
Interrupt on channel 3
Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt
on channels 0 and 3, and there is interrupt on channels 1 and 2.
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I2C
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PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
Power-On Reset
When power is applied to VCC, an internal power-on reset holds the PCA9544A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released, and the PCA9544A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below 0.2 V to reset the device.
Voltage Translation
The pass-gate transistors of the PCA9544A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the electrical characteristics section of this data sheet). In order for the PCA9544A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7
V to effectively clamp the downstream bus voltages. As shown in Figure 3, Vpass (max) is at 2.7 V when the
PCA9544A supply voltage is 3.5 V or lower, so the PCA9544A supply voltage could be set to 3.3 V. Pullup
resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12).
5
4.5
Maximum
Vpass (V)
4
Typical
3.5
3
2.5
2
Minimum
1.5
1
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 3. Vpass Voltage vs VCC
I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see
Figure 4).
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while
the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is
high is defined as the stop condition (P) (see Figure 5).
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master, and the devices that are controlled by the master are the slaves (see
Figure 6).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I2C
Multiplexer
Slave
Figure 6. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit.
8
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PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.
Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the
SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold
times must be taken into account.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Condition
Clock Pulse for ACK
Figure 7. Acknowledgment on the I2C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the PCA9544A control register using the write mode shown in Figure 8.
Slave Address
SDA
S
1
1
1
0
Control Register
A2 A1 A0
Start Condition
0
A
X
X
X
X
X
B2 B1 B0
R/W ACK From Slave
A
ACK From Slave
P
Stop Condition
Figure 8. Write Control Register
Data is read from the PCA9544A control register using the read mode shown in Figure 9.
Slave Address
SDA
S
1
Start Condition
1
1
0
A2
A1
Control Register
A0
1
R/W
A
INT3 INT2 INT1 INT0
ACK From Slave
B2
0
B1
B0
NA
NACK From Master
P
Stop Condition
Figure 9. Read Control Register
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (2)
–0.5
7
V
II
Input current
±20
mA
IO
Output current
±25
mA
±100
mA
±100
mA
Continuous current through VCC
Continuous current through GND
θJA
DGV package (3)
92
DW package (3)
58
GQN
Package thermal impedance
package (3)
78
PW package (3)
83
RGW package (4)
TBD
RGY package (4)
37
UNIT
°C/W
Ptot
Total power dissipation
400
mW
Tstg
Storage temperature range
–65
150
°C
TA
Operating free-air temperature range
–40
85
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
(1)
10
MIN
MAX
2.3
5.5
SCL, SDA
0.7 × VCC
6
A2–A0, INT3–INT0
0.7 × VCC
VCC + 0.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, INT3–INT0
–0.5
0.3 × VCC
–40
85
UNIT
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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V
V
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I2C
PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VPOR
Power-on reset
voltage (2)
TEST CONDITIONS
No load,
VI = VCC or GND
VCC
MIN TYP (1)
MAX
VPOR
1.7
2.1
5V
3.6
4.5 V to 5.5 V
Vpass
Switch output voltage
VSWin = VCC,
ISWout = –100 µA
2.6
3.3 V
3 V to 3.6 V
IOH
INT
VO = VCC
1.6
VOL = 0.6 V
INT
2.8
2.3 V to 5.5 V
VOL = 0.4 V
2
10
3
7
6
10
3
7
SC3–SC0, SD3–SD0
A2–A0
VI = VCC or GND
ICC
±1
fSCL = 100 kHz
VI = VCC or GND,
VI = GND,
IO = 0
IO = 0
Standby mode
High inputs
INT3–INT0
Supply-current
change
SCL, SDA
A2–A0
Ci
INT3–INT0
Cio(OFF) (3)
RON
(1)
(2)
(3)
µA
±1
Low inputs
∆ICC
mA
±1
2.3 V to 5.5 V
INT3–INT0
Operating mode
µA
±1
SCL, SDA
II
V
1.5
1.1
2.3 V to 5.5 V
VOL = 0.4 V
SCL, SDA
IOL
V
4.5
1.9
2.5 V
2.3 V to 2.7 V
UNIT
SCL, SDA
SC3–SC0, SD3–SD0
Switch-on resistance
VI = VCC,
IO = 0
5.5 V
3
12
3.6 V
3
11
2.7 V
3
10
5.5 V
0.3
1
3.6 V
0.1
1
2.7 V
0.1
1
5.5 V
0.3
1
3.6 V
0.1
1
2.7 V
0.1
1
8
15
8
15
8
15
8
15
4.5
6
4.5
6
15
19
6
8
One INT3–INT0 input at 0.6 V,
Other inputs at VCC or GND
One INT3–INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
µA
2.3 V to 5.5 V
SCL or SDA inputs at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
2.3 V to 5.5 V
VI = VCC or GND,
Switch OFF
VO = 0.4 V,
IO = 15 mA
VO = 0.4 V,
IO = 10 mA
µA
2.3 V to 5.5 V
4.5 V to 5.5 V
4
9
16
3 V to 3.6 V
5
11
20
2.3 V to 2.7 V
7
16
45
pF
pF
Ω
All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device.
Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
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SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12)
STANDARD-MODE
I2C BUS
MIN
MAX
100
FAST-MODE
I2C BUS
UNIT
MIN
MAX
0
400
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
0.6
µs
tscl
I2C clock low time
4.7
1.3
µs
tsp
I2C
tsds
I2C serial-data setup time
250
100
ns
tsdh
I2C serial-data hold time
0 (1)
0 (1)
µs
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time (10-pF to 400-pF bus)
tbuf
I2C bus free time between stop and start
4.7
1.3
µs
tsts
I2C start or repeated start condition setup
4.7
0.6
µs
tsth
I2C start or repeated start condition hold
4
0.6
µs
tsps
I2C stop condition setup
4
0.6
µs
spike time
50
input fall time
low) (3)
tvdL(Data)
Valid-data time (high to
tvdH(Data)
Valid-data time (low to high) (3)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
Cb
I2C bus capacitive load
(1)
(2)
(3)
50
kHz
ns
1000
20 + 0.1Cb (2)
300
ns
300
20 + 0.1Cb
(2)
300
ns
300
20 + 0.1Cb (2)
300
ns
1
1
µs
0.6
0.6
µs
1
1
µs
400
400
pF
SCL low to SDA output low valid
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
Cb = total bus capacitance of one bus line in pF
Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 10).
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 10)
PARAMETER
RON = 20 Ω, CL = 15 pF
FROM
(INPUT)
TO
(OUTPUT)
SDA or SCL
SDn or SCn
MIN
MAX
0.3
UNIT
µs
tpd (1)
Propagation delay time
tiv
Interrupt valid time (2)
INTn
INT
4
µs
tir
Interrupt reset delay time (2)
INTn
INT
2
µs
(1)
(2)
RON = 20 Ω, CL = 50 pF
1
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 11).
Interrupt Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tPWRL
Low-level pulse duration rejection of INTn
inputs (1)
1
µs
tPWRH
High-level pulse duration rejection of INTn inputs (1)
0.5
µs
(1)
12
Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 11).
Submit Documentation Feedback
4-CHANNEL
I2C
www.ti.com
PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 kΩ
SDn, SCn
DUT
CL = 50 pF
(See Note A)
I2C-PORT LOAD CONFIGURATION
Two Bytes for Complete
Device Programming
Start
Address
Stop
Address
Bit 7
Condition Condition
Bit 6
(P)
(S)
(MSB)
BYTE
DESCRIPTION
1
I2C address + R/W
2
Control register data
Address
Bit 1
tscl
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
ACK
(A)
Stop
Condition
(P)
tsch
0.7 × VCC
SCL
ticr
ticf
tbuf
tsp
tvd(ACK)
or tvdL
tvdH
0.3 × VCC
tsts
0.7 × VCC
SDA
0.3 × VCC
ticf
ticr
tsth
tsdh
tsds
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
Stop
Condition
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 10. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
Submit Documentation Feedback
13
PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
VCC
RL = 4.7 kΩ
DUT
INT
CL = 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
INTn
(input)
0.5 × VCC
INTn
(input)
tir
tiv
INT
(output)
0.5 × VCC
0.5 × VCC
INT
(output)
VOLTAGE WAVEFORMS (tiv)
0.5 × VCC
VOLTAGE WAVEFORMS (tir)
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
14
Submit Documentation Feedback
4-CHANNEL
www.ti.com
I2C
PCA9544A
AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006
APPLICATION INFORMATION
VCC = 2.7 V to 5.5 V
VCC = 3.3 V
VCC = 2.7 V to 5.5 V
20
SDA
I2C/SMBus
SCL
Master
19
18
17
SDA
SCL
INT
See Note A
SD0
5
SC0
6
4
INT0
Channel 0
VCC = 2.7 V to 5.5 V
See Note A
SD1
SC1
INT1
8
9
7
Channel 1
VCC = 2.7 V to 5.5 V
PCA9544A
See Note A
SD2
SC2
INT2
3
A2
2
A1
1
A0
10
GND
12
13
Channel 2
11
VCC = 2.7 V to 5.5 V
See Note A
SD3
SC3
INT3
15
16
Channel 3
14
NOTES: A. If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pullup resistor is required.
If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pullup resistor is not required.
The interrupt inputs should not be left floating.
B. Pin numbers shown are for DGV, DW, PW, and RGY packages.
Figure 12. Typical Application
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
PCA9544ADGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
PCA9544ADGVT
PREVIEW
TVSOP
DGV
20
250
TBD
Call TI
PCA9544ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544ADWT
PREVIEW
SOIC
DW
20
250
TBD
Call TI
Call TI
PCA9544AGQNR
NRND
GQN
20
1000
TBD
SNPB
Level-1-240C-UNLIM
PCA9544APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544APWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544APWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544APWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9544ARGWR
PREVIEW
QFN
RGW
20
3000
TBD
Call TI
PCA9544ARGYR
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
PCA9544ARGYRG4
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
PCA9544AZQNR
ACTIVE
ZQN
20
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BGA MI
CROSTA
R JUNI
OR
BGA MI
CROSTA
R JUNI
OR
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-1-260C-UNLIM
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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