HD151012 8-bit Binary Programmable Counter with Synchronous Preset Enable ADE-205-132 (Z) Preliminary 1st. Edition Mar. 1996 Description The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider. Features • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) • High output current Fanout of 10 LS TTL Loads • Wide operating voltage VCC = 2 to 6 V • Low supply current (Ta = 25°C) ICC (Static) = 4 µA (max) HD151012 Function Table Control Inputs CLR PR SPE Mode Operation Description H H H Generally count Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) X X L Synchronous preset Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) L H — Initialize of Q output Initialize of Q = “L” H L — Initialize of Q output Initialize of Q = “H” Notes: 1. Synchronous preset (SPE) input can set max 256 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. H : High level L : Low level X : Immaterial — : Irrespective of condition Pin Arrangement J0 1 16 VCC J1 2 15 CLK J2 3 14 CLK J3 4 13 Q J4 5 12 PR J5 6 11 SPE J6 7 10 CLR GND 8 9 J7 (Top view) 2 HD151012 Pin Description Pin Name Input pins Output pins Pin Description J0 to J7 Count data input for option CLK, CLK Clock inputs SPE Preset input for Jn data PR Preset input for D-type Flip Flop (Initialize “L” at Q output) CLR Clear input for D-type Flip Flop (Initialize “H” at Q output) Q Output for D-type Flip Flop CLK : Rise edge trigger CLK : Fall edge trigger Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC –0.5 to 7.0 V Input / output voltage VIN/V OUT –0.5 to VCC +0.5 V VCC, GND current I CC, IGND ±50 mA Output current / pin I OUT ±25 mA Power dissipation PT 500 mW Storage temperature Tstg –65 to 150 °C Input diode current I IK ±20 mA Output diode current I OK ±20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal. 3 HD151012 Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage VCC 2 — 6 V Input/output voltage VIN/ OUT 0 — VCC V Operating temperature Topr –40 — +85 °C t r, t f 0 — 1000 ns VCC = 4.5 V 0 — 500 VCC = 5.5 V 0 — 400 1 Input rise/fall time* Note: VCC = 2.5 V 1. This item guarantees maximum limit when one input switches. Logic Diagram J0 J1 J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7 CLK CLK 8-bit binary counter J0 CLK PR PR D CO SPE Q CK Q Q CLR SPE CLR 4 HD151012 Electrical Characteristics Ta = –40 to 85°C Ta = 25°C Item Symbol VCC Min Typ Max Min Max Unit Test Conditions High level input VIH 2.0 1.5 — — 1.5 — V J0 to J7 4.5 3.15 — — 3.15 — SPE 6.0 4.2 — — 4.2 — PR, CLR 2.0 1.5 — — 1.5 — CLK, CLK 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 SPE 6.0 — — 1.8 — 1.8 PR, CLR 2.0 — — 0.5 — 0.5 CLK, CLK 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 4.31 — 4.13 — I OH = –4 mA 6.0 5.68 5.80 — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — 0.17 0.26 — 0.33 I OL = 4 mA 6.0 — 0.18 0.26 — 0.33 I OL = 5.2 mA voltage Low level input VIL voltage High level output VOH voltage Low level output VOL voltage V V J0 to J7 VIN = I OH = –20 mA VIH or VIL V VIN = I OL = 20 mA VIH or VIL Input capacitance I IN 6.0 — — ±0.1 — ±1.0 mA VIN = VCC or GND Supply current I CC 6.0 — — 4.0 — 40.0 mA VIN = VCC or GND 5 HD151012 Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) Sym- Ta = –40 to 85°C Ta = 25°C Item bol VCC Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 4 — 3 MHz 4.5 — 36 20 — 16 6.0 — — 24 — 19 t TLH 2.0 — 30 75 — 95 t THL 4.5 — 8 15 — 19 6.0 — 7 13 — 16 frequency Output rise/fall time Propagation delay t PLH 2.0 — — 300 — 380 time t PHL 4.5 — 35 60 — 75 6.0 — — 53 — 65 t PLH 2.0 — — 150 — 185 t PHL 4.5 — 18 30 — 38 6.0 — — 25 — 32 2.0 80 — — 100 — 4.5 16 — — 20 — 6.0 14 — — 17 — 2.0 100 — — 125 — (Jn - CLK, CLK) 4.5 20 — — 25 — (SPE, CLK, CLK) 6.0 17 — — 21 — 2.0 15 — — 15 — (Jn - CLK, CLK) 4.5 10 — — 10 — (SPE, CLK, CLK) 6.0 5 — — 5 — Pulse width tw (CLK, CLK, PR, CLR) Setup time Hold time ts th ns CLK or CLK to Q PR or CLR to Q ns ns ns Input capacitance CIN — — 5 10 — 10 pF Power dissipation capacitance* 1 CPD — — 48 — — — pF Note: 6 Test Conditions 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. I CC (opr) = CPD • VCC • fIN + ICC HD151012 Test Circuit VCC VCC Input J0 J1 Pulse generator See Function Table Zout = 50 Ω Input Pulse generator Zout = 50 Ω Output Q J7 CLK CLK CL SPE PR CLR Note: 1. CL includes probe and jig capacitance. Waveforms – 1 tw tw 6 ns 6 ns CLK 50 % CLK VCC 90 % 90 % 50 % 10 % 10 % t PLH 90 % 50 % Q GND t PHL 10 % t TLH VOH 90 % 50 % 10 % t THL VOL 7 HD151012 Waveforms – 2 6 ns 90 % Jn VCC 90 % 50 % 10 % 10 % GND ts CLK 90 % VCC 10 % 6 ns GND 50 % 10 % CLK VOH F/F Output *1 50 % VOL Internal delay Waveforms – 3 6 ns 90 % Jn 90 % VCC 50 % 10 % 10 % th CLK GND 90 % VCC 10 % 6 ns GND 50 % 10 % CLK VOH F/F Output *1 50 % Internal delay Note: 8 1. F/F output is internal signal of IC. VOL HD151012 Waveforms – 4 6 ns 90 % SPE VCC 90 % 50 % 10 % 10 % GND ts CLK 90 % VCC 10 % 6 ns GND 50 % 10 % CLK VOH F/F Output *1 50 % VOL Internal delay Waveforms – 5 6 ns 90 % SPE 90 % VCC 50 % 10 % 10 % th CLK GND 90 % VCC 10 % 6 ns GND 50 % 10 % CLK VOH F/F Output *1 50 % Internal delay Note: 1. VOL F/F output is internal signal of IC. 9 HD151012 Waveforms – 6 tf tr VCC 90 % 90 % CLR 50 % 50 % 10 % 10 % GND tw tf tr 90 % 90 % VCC PR 50 % 50 % 10 % 10 % GND tw t PHL t PLH VOH Q 50 % 50 % VOL 10 HD151012 Timing Chart CLK SPE J0 J1 J2 J3 J4 J5 J6 J7 (CO=SPE) CLR (Initialize of CLR) Q PR (Initialize of PR) Q Count 5 4 3 2 1 0 3 2 1 0 35 34 11 HD151012 Example of Application Circuit AC Signal Generator for STN Type Liquid Crystal Panel Initialize counter: 50 J0 V CC J1 CLK J2 CLK J3 Q J4 PR J5 SPE J6 CLR GND Note: 12 When initializing output D-F/F apply “L” J7 * * HD151012 Timing Chart Example of AC Signal Generator 1 2 3 49 50 51 52 53 101 102 1 0 103 104 CLK SPE J0 J1 J2 J3 50 J4 J5 J6 J7 (CO=SPE) CLR Q PR Q Count 50 49 48 2 1 0 50 49 50 49 13 HD151012 Package Dimensions Unit : mm TTP-16DA 9 1 8 4.40 16 4.50 Max 5.20 5.4 Max 0.65 0.10 M 0.03 Min 0.1Max 0.10 6.40 ± 0.20 0.17 ± 0.05 1.10 Max 0.20 ± 0.10 0 – 10° 0.50 ± 0.10 14 HD151012 Package Dimensions Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 0.13 M *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Mass (reference value) TTP-16DA — — 0.05 g 15 HD151012 Cautions 1. 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