IT7001M/IT7001N Programmable 8-Bit Binary Counter with Synchronous Preset Enable Preliminary Specification V0.2 Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives. Copyright 2000 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE, Inc. for the latest document(s). All sales are subject to ITE’ s Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT7001M/IT7001N is a trademark of ITE, Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE (USA) Inc. Marketing Department 1235 Midas Way Sunnyvale, CA 94086 U.S.A. Phone: Fax: (408) 530-8860 (408) 530-8861 ITE (USA) Inc. Eastern U.S.A. Sales Office 896 Summit St., #105 Round Rock, TX 78664 U.S.A. Phone: Fax: (512) 388-7880 (512) 388-3108 ITE, Inc. Marketing Department 7F, No. 435, Nei Hu District, Jui Kuang Rd., Taipei 114, Taiwan, R.O.C. Phone: Fax: (02) 2657-9896 (02) 2657-8561, 2657-8576 If you have any marketing or sales questions, please contact: Lawrence Liu, at ITE Taiwan: E-mail: [email protected], Tel: 886-2-26579896 X6071, Fax: 886-2-26578561 David Lin, at ITE U.S.A: E-mail: [email protected], Tel: (408) 530-8860 X238, Fax: (408) 530-8861 Don Gardenhire, at ITE Eastern USA Office: E-mail: [email protected] Tel: (512) 388-7880, Fax: (512) 388-3108 To find out more about ITE, visit our World Wide Web at: http://www.ite.com.tw http://www.iteusa.com Or email [email protected] for more product information/services. Revision History Revision History Section Revision Page No. To avoid the custom misunderstanding of CLR and PR signal in the IT7001 specification, CLR and PR signals were replaced by CLR_N and PR_N respectively. - l Sections 6, 7, 8 in the previous version were removed. - l The section arrangement was adjusted as follows: l - Section 9 was changed to section 6. - Section 10 was changed to section 7. - Section 11 was changed to section 9. Section 12 was changed to section 10. 1 l Section 1 Features was revised. 1 7 l Figure 7-1. Timing Diagram When Jn is fixed was revised. 13 8 l Section 8 Electrical Characteristics was revised. 15 www.ite.com.tw www.iteusa.com 1 IT7001M/IT7001N V0.2 Contents CONTENTS 1. Features ...................................................................................................................................................1 2. General Description..................................................................................................................................3 3. Block Diagram ..........................................................................................................................................5 4. Pin Configuration ......................................................................................................................................7 5. IT7001M/IT7001N Pin Description ............................................................................................................9 6. Example of Application Circuit ................................................................................................................ 11 7. Timing Chart: Example of AC Signal Generator ...................................................................................... 13 8. DC Characteristics.................................................................................................................................. 15 9. Package Information............................................................................................................................... 17 10. Ordering Information............................................................................................................................... 19 Tables Table 5-1. Function Table of CLR_N, PR_N and SPE_N Pins ........................................................................9 Figures Figure 6-1. Example of Application Circuit .................................................................................................... 11 Figure 7-1. Timing Diagram When Jn is fixed ............................................................................................... 13 Figure 7-2. Timing Diagram When Jn is changed ......................................................................................... 14 www.ite.com.tw www.iteusa.com i IT7001M/IT7001N V0.2 Features 1. Features n Wide Operation Voltage − Vcc = 2.5 to 5.5 V n Low Static Current (Ta = 25°C) − Icc (Static) = 10 µA (max) n Package: − IT7001M: 16-SOP − IT7001N: 16-TSSOP www.ite.com.tw www.iteusa.com Specifications Subject to Change without Notice 1 IT7001M/IT7001N V0.2 By Felix Sun, 12/18/2000 ITPM-PN-200045 www.ite.com.tw www.iteusa.com 2 IT7001M/IT7001N V0.2 General Description 2. General Description The IT7001M/IT7001N consists of 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE_N) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rising edge. It is applied to generate AC signal for STN-type liquid crystal and divider for general usage. www.ite.com.tw www.iteusa.com 3 IT7001M/IT7001N V0.2 www.ite.com.tw www.iteusa.com 4 IT7001M/IT7001N V0.2 Logic Diagram 3. Block Diagram J0 CLK_N J0 CLK J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7 CLK 8-bit binary counter J1 PR_N PR Q_N D CO_N CK Q Q CLR SPE_N SPE_N CLR_N www.ite.com.tw www.iteusa.com 5 IT7001M/IT7001N V0.2 www.ite.com.tw www.iteusa.com 6 IT7001M/IT7001N V0.2 Pin Configuration 4. Pin Configuration J0 1 16 Vcc J1 2 15 CLK_N J2 3 14 CLK J3 4 13 Q J4 5 12 PR_N J5 6 11 SPE_N J6 7 10 CLR_N IT7001M/N GND 8 9 J7 Top View www.ite.com.tw www.iteusa.com 7 IT7001M/IT7001N V0.2 www.ite.com.tw www.iteusa.com 8 IT7001M/IT7001N V0.2 IT7001M/IT7001N Pin Description 5. IT7001M/IT7001N Pin Description Signal Pin(s) No. Attribute Description VCC 16 Power GND 8 Ground J0 to J7 1-7,9 I Count data input for option CLK, CLK_N 14,15 I Clock inputs CLK: Rising edge trigger CLK_N: Falling edge trigger SPE_N 11 I Preset input for Jn data Please refer to the table below PR_N 12 I Preset input for D-type Flip Flop (Initialize “L” at Q output) Please refer to the table below CLR_N 10 I Clear input for D-type Flip Flop (Initialize “H” at Q output) Please refer to the table below Q 13 O Output for D-type Flip Flop Table 5-1. Function Table of CLR_N, PR_N and SPE_N Pins Control Inputs CLR_N PR_N SPE_N H H H Mode Operation Description Generally count Down count at the rising edge of clock (CLK) Down count at the falling edge of clock (CLK_N) X X L Synchronous preset Jn data is preset at the rise of clock (CLK) , the fall of clock (CLK_N) L H Initialize of Q output Initialize of Q = “L” H L Initialize of Q output Initialize of Q = “H” H: High level X: Immaterial L: Low level : Irrespective of condition 1) Synchronous preset (SPE_N) input can set max 256 down counts. 2) When the count value is 0, the next clock pulse presets the data to invert the output. 3) CLR_N and PR_N inputs initialize the output data. www.ite.com.tw www.iteusa.com 9 IT7001M/IT7001N V0.2 www.ite.com.tw www.iteusa.com 10 IT7001M/IT7001N V0.2 Example of Application Circuit 6. Example of Application Circuit • AC Signal Generator for STN-Type Liquid Crystal Panel Initialize counter: 50 J0 Vcc J1 CLK_N J2 CLK J3 Q J4 PR_N J5 SPE_N J6 CLR_N GND * * J7 *When initializing output D-F/F, apply "L". Figure 6-1. Example of Application Circuit www.ite.com.tw www.iteusa.com 11 IT7001M/IT7001N V0.2 www.ite.com.tw www.iteusa.com 12 IT7001M/IT7001N V0.2 Timing Chart: Example of AC Signal Generator 7. Timing Chart: Example of AC Signal Generator 2 1 3 49 ..... 50 51 52 53 101 102 49..... 1 0 ..... 103 104 ..... CLK SPE_N J0 J1 J2 J3 50 J4 J5 J6 J7 (CO_N) CLR_N (initialize of CLR_N) Q PR_N (initialize of PR_N) Q Count 50 49 48..... 2 1 0 50 50 49..... Figure 7-1. Timing Diagram When Jn is fixed www.ite.com.tw www.iteusa.com 13 IT7001M/IT7001N V0.2 IT7001M/IT7001N CLK SPE_N J0 J1 J2 J3 J4 J5 J6 J7 (CO_N) CLR_N (Initialize of CLR_N) Q PR_N (Initialize of PR_N) Q Count 5 4 3 2 1 0 3 2 1 0 35 34 Figure 7-2. Timing Diagram When Jn is changed www.ite.com.tw www.iteusa.com 14 IT7001M/IT7001N V0.2 DC Characteristics 8. DC Characteristics Absolute Maximum Ratings *Comments Power Supply (VCC) -0.3V to 6.0V input Voltage (VIN ) -0.3V to VCC + 0.3V Output Voltage (VOUT) -0.3V to VCC + 0.3V Output current / pin (IOUT) Storage Temperature (TSTG) 24mA -40°C to 125°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied, and exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (Operation Condition Vcc=2.5V~5.5V, VIN / VOUT=0~Vcc, Tj=-30°C~85°C) (Note : This item guarantees maximum limit when one input switches.) Item Symbol Conditions Min Typ Max Unit High Level Input Voltage VIH CMOS 0.7*Vcc V Low Level Input Voltage VIL CMOS 0.3*Vcc V High Level Output Voltage VOH IOH =-2mA 0.7*Vcc V Low Level Output Voltage VOL IOL =2mA 0.3*Vcc V Input Leakage Current IIL VIN = Vcc or GND ±1.0 µA Static Current ICC VIN = Vcc or GND 10 µA Maximum clock frequency fmax Vcc = 3.3V 20 MHz www.ite.com.tw www.iteusa.com 15 IT7001M/IT7001N V0.2 www.ite.com.tw www.iteusa.com 16 IT7001M/IT7001N V0.2 Package Information 9. Package Information SOP 16L Outline Dimensions 16 Unit: inches/mm 1 b HE E 9 L 8 Detail F L1 A1 D e A A2 C D y Seating Plane See Detail F Dimension in inches Dimension in mm Symbol Min Nom Max Min Nom Max A 0.053 0.064 0.069 1.35 1.63 1.75 A1 0.004 0.006 0.010 0.10 0.15 0.25 A2 0.051 0.055 0.059 1.30 1.40 1.50 b 0.013 0.016 0.020 0.33 0.41 0.51 C 0.007 0.010 0.19 0.25 D 0.386 0.390 0.394 9.80 9.91 10.01 E 0.150 0.154 0.157 3.80 3.90 4.00 e 0.050 HE 0.228 0.236 0.244 5.80 6.00 6.20 L 0.016 0.025 0.050 0.40 0.64 1.27 L1 www.ite.com.tw www.iteusa.com 1.27 0.042 1.07 y 0.004 0.10 θ 0° 8° 0° 8° 17 IT7001M/IT7001N V0.2 IT7001M/IT7001N TSSOP 16L Outline Dimensions 16 Unit: inches/mm 1 b HE E 9 L 8 Detail F A1 D e A A2 C D y L1 Seating Plane See Detail F Dimension in inches Dimension in mm Symbol Min Nom Max Min Nom Max A 0.047 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.035 0.041 0.80 0.90 1.05 b 0.007 0.012 0.19 0.30 C 0.004 0.008 0.09 0.20 D 0.193 0.197 0.201 4.90 5.00 5.10 E 0.169 0.173 0.177 4.30 4.40 4.50 e 0.026BSC. HE L 0.252BSC. 0.020 L1 www.ite.com.tw www.iteusa.com 0.65BSC. 0.024 6.40BSC. 0.030 0.50 0.039REF. 0.60 0.75 1.0REF. y 0.004 0.10 θ 0° 8° 0° 8° 18 IT7001M/IT7001N V0.2 Ordering Information 10. Ordering Information Part No. Package IT7001M 16-SOP IT7001N 16-TSSOP www.ite.com.tw www.iteusa.com 19 IT7001M/IT7001N V0.2