HD74ALVCHR162269A 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs ADE-205-125 (Z) Preliminary 1st. Edition January 1998 Description The HD74ALVCHR162269A is a 12-bit to 24-bit registered bus exchanger, which is intended for applications where two separate ports must be multiplexed onto, or de-multiplexed from, a single port. It is particularly suitable as an interface between synchronous DRAMs and high speed microprocessors. The HD74ALVCHR162269A is designed specifically for low voltage (from 2.5 V to 3.3 V) VCC operation. Data is stored in the internal B-port registers on the low to high transition of the CLK input, provided that the appropriate CLKENA inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B-port. For data transfer in the B to A direction, a single storage register is provided. The SEL line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period that the data will be valid on the bus. The control pins are registered so that all transactions are synchronous with the clock. Data flows is controlled by the active low output enables (OEA, OEB1, OEB2). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. Features • All outputs have equivalent 26 Ω series resistors, so no external resistors are required. • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors. HD74ALVCHR162269A Function Table Inputs Outputs CLK OEA OEB A 1B, 2B ↑ H H Z Z ↑ H L Z Active ↑ L H Active Z Output-enable table Inputs Outputs CLKENA1 CLKENA2 CLK A 1B 2B L H ↑ L L 2B0 *1 L H ↑ H H 2B0 *1 L L ↑ L L L L L ↑ H H L ↑ L ↑ H H H H L H X X H 1B0 *1 L 1B0 *1 H 1B0 *1 2B0 *1 A-to-B storage table (OEB = L) Inputs CLK SEL 1B 2B Output A X H X X A0 *1 X L X X A0 *1 ↑ H L X L ↑ H H X H ↑ L X L L B-to-A storage (OEA = L) H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. 2 HD74ALVCHR162269A Pin Arrangement 56 OEB2 OEA 1 OEB1 2 55 CLKENA2 2B3 3 54 2B4 GND 4 53 GND 2B2 5 52 2B5 2B1 6 51 2B6 VCC 7 50 VCC A1 8 49 2B7 A2 9 48 2B8 A3 10 47 2B9 GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 43 2B12 A7 15 42 1B12 A8 16 41 1B11 A9 17 40 1B10 GND 18 39 GND A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 VCC 22 35 VCC 1B1 23 34 1B6 1B2 24 33 1B5 GND 25 32 GND 1B3 26 31 1B4 NC 27 30 CLKENA1 SEL 28 29 CLK (Top view) 3 HD74ALVCHR162269A Absolute Maximum Ratings Item Supply voltage range Input voltage range *1, 2 Symbol Ratings Unit VCC –0.5 to 4.6 V VI –0.5 to 4.6 V –0.5 to VCC +0.5 Output voltage range *1, 2 Conditions Except I/O ports I/O ports VO –0.5 to VCC +0.5 V Input clamp current I IK –50 mA VI < 0 Output clamp current I OK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC Continuous current through I CC / IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) *3 PT 1 W Storage temperature range Tstg –65 to 150 °C Notes: TSSOP Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum power dissipation is calculated using a junction temperature of 150°C and board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High-level output current I OH — –6 mA — –8 VCC = 2.7 V — –12 VCC = 3.0 V — 6 — 8 VCC = 2.7 V — 12 VCC = 3.0 V Low-level output current I OL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating free-air temperature Ta –40 85 °C Note: Unused or floating control pins must be held high or low. 4 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCHR162269A Logic Diagram CLK C1 OEB1 1D C1 OEB2 1D CLKENA1 CLKENA2 SEL C1 SEL 1D OEA 1D C1 A1 C1 G1 1 1 1D 1B1 CE C1 1D 2B1 CE C1 1D 1 of 12 Channels 5 HD74ALVCHR162269A Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Input voltage VIH VIL Output voltage VOH Min Max Unit 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 I OH = –100 µA Min to Max VCC–0.2 — 2.3 1.9 — I OH = –4 mA, VIH = 1.7 V 2.3 1.7 — I OH = –6 mA, VIH = 1.7 V 2.7 2.2 — I OH = –4 mA, VIH = 2.0 V 2.7 2.0 — I OH = –8 mA, VIH = 2.0 V 3.0 2.4 — I OH = –6 mA, VIH = 2.0 V 3.0 2.0 — I OH = –12 mA, VIH = 2.0 V Min to Max — 0.2 I OL = 100 µA 2.3 — 0.4 I OL = 4 mA, VIL = 0.7 V 2.3 — 0.55 I OL = 6 mA, VIL = 0.7 V 2.7 — 0.4 I OL = 4 mA, VIL = 0.8 V 2.7 — 0.6 I OL = 8 mA, VIL = 0.8 V 3.0 — 0.55 I OL = 6 mA, VIL = 0.8 V 3.0 — 0.8 I OL = 12 mA, VIL = 0.8 V I IN 3.6 — ±5.0 I IN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V I OZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current I CC 3.6 — 40 µA VIN = VCC or GND 3.0 to 3.6 — 750 VOL Input current Off state output current *1 ∆I CC Notes: 1. 6 V Test Conditions µA VIN = VCC or GND One input at (V CC–0.6) V, other inputs at V CC or GND For I/O ports, the parameter I OZ includes the input leakage current. HD74ALVCHR162269A Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit 2.5±0.2 — — — MHz 2.7 — — — 3.3±0.3 135 — — t PLH 2.5±0.2 — — — t PHL 2.7 — — — 3.3±0.3 2.0 — 5.0 2.5±0.2 — — — 2.7 — — — 3.3±0.3 1.0 — 4.0 t ZH 2.5±0.2 — — — t ZL 2.7 — — — 3.3±0.3 2.0 — 5.0 2.5±0.2 — — — 2.7 — — — 3.3±0.3 1.0 — 4.5 t HZ 2.5±0.2 — — — t LZ 2.7 — — — 3.3±0.3 2.0 — 5.0 2.5±0.2 — — — 2.7 — — — 3.3±0.3 1.0 — 4.5 Maximum clock frequency f max Propagation delay time Output enable time Output disable time ns ns ns Input capacitance CIN 3.3 — 3.5 — pF Output capacitance CO 3.3 — 9.0 — pF From (Input) To (Output) CLK B CLK A CLK B CLK A CLK B CLK A 7 HD74ALVCHR162269A Switching Characteristics (Ta = –40 to 85°C) (cont) Item Symbol VCC (V) Min Typ Max Unit FROM (Input) Setup time t su 2.5±0.2 — — — ns A data before CLK↑ 2.7 — — — 3.3±0.3 1.0 — — 2.5±0.2 — — — B data before CLK↑ 2.7 — — — “H” or “L” 3.3±0.3 1.0 — — 2.5±0.2 — — — SEL before CLK↑ 2.7 — — — “H” or “L” 3.3±0.3 1.0 — — 2.5±0.2 — — — CLKENA1 or 2.7 — — — CLKENA2 before CLK↑ 3.3±0.3 1.0 — — “H” or “L” 2.5±0.2 — — — OE before CLK↑ 2.7 — — — “H” or “L” 3.3±0.3 1.0 — — 2.5±0.2 — — — 2.7 — — — 3.3±0.3 0.5 — — 2.5±0.2 — — — B data after CLK↑ 2.7 — — — “H” or “L” 3.3±0.3 0.5 — — 2.5±0.2 — — — SEL aftrer CLK↑ 2.7 — — — “H” or “L” 3.3±0.3 0.5 — — 2.5±0.2 — — — CLKENA1 or 2.7 — — — CLKENA2 after CLK↑ 3.3±0.3 0.5 — — “H” or “L” 2.5±0.2 — — — OE after CLK↑ 2.7 — — — “H” or “L” 3.3±0.3 0.5 — — 2.5±0.2 — — — 2.7 — — — 3.3±0.3 2.0 — — Hold time Pulse width 8 th tw “H” or “L” ns A data after CLK↑ “H” or “L” ns CLK “H” or “L” HD74ALVCHR162269A Test Circuit See the table below 500 Ω S1 OPEN GND *1 CL = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.15V OPEN OPEN GND GND 4.6 V 6.0 V Note: 1. CL includes probe and jig capacitance. 9 HD74ALVCHR162269A Waveforms – 1 tr tf VIH 90 % 90 % Vref CLK Vref 10 % 10 % GND VIH Data Input t PHL t PLH GND VOH Vref Output Vref VOL Waveforms – 2 VIH Vref Timing Input tsu GND th VIH Data Input Vref Vref GND tw VIH CLK Vref Vref GND 10 HD74ALVCHR162269A Waveforms – 3 Output Control VIH GND tr tf VIH 90 % 90 % Vref CLK 10 % Vref 10 % t ZL GND t LZ ≈V OH1 Vref Waveform - A VOL + 0.3 V t ZH Waveform - B t HZ VOH – 0.3 V Vref VOL VOH ≈V OL1 TEST VIH Vref VOH1 VOL1 Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.15V 2.3 V 2.7 V 1.2 V 2.3 V 1.5 V 3.0 V GND GND Note: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Zo = 50Ω, tr ≤ 2.5ns, tf ≤ 2.5ns. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The outputs are measured one at a time with one transition per measurement. 11 HD74ALVCHR162269A Package Dimensions Unit : mm +0.3 14.00 –0.1 29 6.10 +0.3 –0.1 56 1 0.50 28 0.20 +0.1 –0.05 0.08 M 8.10 ± 0.3 0.40 Max 0.15 ± 0.05 0.10 0.05 ± 0.05 1.2 Max 10° Max 0.50 ± 0.1 Hitachi code EIAJ code JEDEC code 12 TTP-56D — — Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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