HITACHI HD74ALVCH162501

HD74ALVCH162501
18-bit Universal Bus Transceivers with 3-state Outputs
ADE-205-182 (Z)
Preliminary
1st. Edition
December 1996
Description
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB
and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the low to
high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the
outputs are in the high impedance state. Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high, and
OEBA is active low). Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce
overshoot and undershoot.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
HD74ALVCH162501
Function Table *3
Inputs
Output B
OEAB
LEAB
CLKAB
A
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
H
L
H
X
B0
*1
H
L
L
X
B0
*2
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established, provided
that CLKAB was high before LEAB went low.
2. Output level before the indicated steady state input conditions were established.
3. A to B data flow is show; B to A flow is similar but uses OEBA, LEBA, and CLKBA.
HD74ALVCH162501
Pin Arrangement
OEAB 1
56 GND
LEAB 2
55 CLKAB
54 B1
A1 3
53 GND
GND 4
A2 5
52 B2
A3 6
VCC 7
51 B3
A4 8
49 B4
A5 9
48 B5
A6 10
47 B6
50 VCC
GND 11
46 GND
A7 12
45 B7
A8 13
44 B8
A9 14
43 B9
A10 15
42 B10
A11 16
41 B11
A12 17
40 B12
GND 18
39 GND
A13 19
38 B13
A14 20
37 B14
A15 21
36 B15
VCC 22
35 VCC
A16 23
34 B16
A17 24
33 B17
GND 25
32 GND
A18 26
31 B18
OEBA 27
30 CLKBA
LEBA 28
29 GND
(Top view)
HD74ALVCH162501
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
–0.5 to VCC +0.5
Output voltage
*1, 2
Conditions
Except I/O ports
I/O ports
VO
–0.5 to VCC +0.5
V
Input clamp current
I IK
–50
mA
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
TSSOP
±100
Maximum power dissipation
at Ta = 55°C (in still air) *3
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
Notes:
Stresses beyond those listed under “absolute maximum ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute maximum rated conditions for extended
periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output
clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of
150°C and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
I OH
—
–6
mA
—
–8
VCC = 2.7 V
—
–12
VCC = 3.0 V
—
6
—
8
VCC = 2.7 V
—
12
VCC = 3.0 V
Low level output current
I OL
mA
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
Conditions
VCC = 2.3 V
VCC = 2.3 V
Note: Unused control inputs must be held high or low to prevent them from floating.
HD74ALVCH162501
Logic Diagram
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
1D
C1
CLK
1D
C1
CLK
To seventeen other channels
54
B1
HD74ALVCH162501
Electrical Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V) *1
Input voltage
VIH
VIL
Output voltage
VOH
Min
Max
Unit
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
I OH = –100 µA
Min to Max VCC–0.2
—
2.3
1.9
—
I OH = –4 mA, VIH = 1.7 V
2.3
1.7
—
I OH = –6 mA, VIH = 1.7 V
3.0
2.4
—
I OH = –6 mA, VIH = 2.0 V
2.7
2.0
—
I OH = –8 mA, VIH = 2.0 V
3.0
2.0
—
I OH = –12 mA, VIH = 2.0 V
Min to Max —
0.2
I OL = 100 µA
2.3
—
0.4
I OL = 4 mA, VIL = 0.7 V
2.3
—
0.55
I OL = 6 mA, VIL = 0.7 V
3.0
—
0.55
I OL = 6 mA, VIL = 0.8 V
2.7
—
0.6
I OL = 8 mA, VIL = 0.8 V
3.0
—
0.8
I OL = 12 mA, VIL = 0.8 V
I IN
3.6
—
±5
I IN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
3.6
—
±500
VIN = 0 to 3.6 V
I OZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current I CC
3.6
—
40
µA
VIN = VCC or GND
3.0 to 3.6
—
750
µA
VIN = one input at (VCC–0.6)
V,
other inputs at V CC or GND
VOL
Input current
Off state output current
*2
∆I CC
V
Test Conditions
µA
VIN = VCC or GND
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended
operating conditions.
2. For I/O ports, the parameter I OZ includes the input leakage current.
HD74ALVCH162501
Switching Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
2.5±0.2
150
—
—
MHz
2.7
150
—
—
3.3±0.3
150
—
—
t PLH
2.5±0.2
1.2
—
5.9
t PHL
2.7
—
—
5.2
3.3±0.3
1.0
—
4.5
2.5±0.2
1.6
—
6.8
2.7
—
—
6.0
3.3±0.3
1.3
—
5.2
2.5±0.2
1.7
—
7.2
2.7
—
—
6.3
3.3±0.3
1.4
—
5.5
t ZH
2.5±0.2
1.1
—
6.8
t ZL
2.7
—
—
6.0
3.3±0.3
1.0
—
5.2
2.5±0.2
1.4
—
7.3
2.7
—
—
6.7
3.3±0.3
1.1
—
5.6
t HZ
2.5±0.2
2.2
—
6.9
t LZ
2.7
—
—
6.2
3.3±0.3
1.4
—
5.5
2.5±0.2
2.0
—
6.0
2.7
—
—
5.1
3.3±0.3
1.3
—
4.7
Maximum clock frequency f max
Propagation delay time
Output enable time
Output disable time
ns
ns
ns
FROM
(Input)
TO
(Output)
A or B
B or A
LE
A or B
CLK
A or B
OEAB
B
OEBA
A
OEAB
B
OEBA
A
Input capacitance
CIN
3.3
—
4.0
—
pF
Control inputs
Output capacitance
CIN / O
3.3
—
8.0
—
pF
A or B ports
HD74ALVCH162501
Switching Characteristics (Ta = –40 to 85°C) (Cont)
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
FROM (Input)
Setup time
t su
2.5±0.2
2.2
—
—
ns
Data before CLK↑
2.7
2.1
—
—
3.3±0.3
1.7
—
—
2.5±0.2
1.9
—
—
Data before LE↓
2.7
1.6
—
—
CLK “H”
3.3±0.3
1.5
—
—
2.5±0.2
1.3
—
—
Data before LE↓
2.7
1.1
—
—
CLK “L”
3.3±0.3
1.0
—
—
2.5±0.2
0.6
—
—
2.7
0.6
—
—
3.3±0.3
0.7
—
—
2.5±0.2
1.4
—
—
Data after LE↓
2.7
1.7
—
—
CLK “H” or “L”
3.3±0.3
1.4
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
Hold time
Pulse width
th
tw
ns
ns
Data after CLK↑
LE “H”
CLK “H” or “L”
HD74ALVCH162501
• Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
C L = 50 pF
500 Ω
Load Circuit for Outputs
Symbol
t PLH / t PHL
t su / t h / t w
t ZH/ t HZ
t ZL / t LZ
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
OPEN
OPEN
GND
GND
4.6 V
6.0 V
Note: 1. C L includes probe and jig capacitance.
HD74ALVCH162501
• Waveforms – 1
tf
tr
90 %
Input
VIH
90 %
Vref
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
• Waveforms – 2
tr
VIH
90 %
Vref
Timing Input
10 %
tsu
GND
th
VIH
Data Input
Vref
Vref
GND
tw
VIH
Input
Vref
Vref
GND
HD74ALVCH162501
• Waveforms – 3
Output
Control
tf
tr
VIH
90 %
90 %
Vref
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈VOL1
TEST
VIH
Vref
VOH1
VOL1
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
2.3 V
2.7 V
1.2 V
2.3 V
1.5 V
3.0 V
GND
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
HD74ALVCH162501
Package Dimensions
Unit : mm
+0.3
14.00 –0.1
29
6.10 +0.3
–0.1
56
1
0.50 28
0.20 +0.1
–0.05
0.08 M
8.10 ± 0.3
0.40 Max
0.15 ± 0.05
0.10
0.05 ± 0.05
1.2 Max
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-56D
—
—
Cautions
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
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