HITACHI HD74HC162

HD74HC160/HD74HC161/
HD74HC162/HD74HC163
Synchronous Decade Counter (Direct Clear)
Synchronous 4-bit Binary Counter (Direct Clear)
Synchronous Decade Counter (Synchronous Clear)
Synchronous 4-bit Binary Counter (Synchronous Clear)
Description
The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the
HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waveform.
These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte
rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs
is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive
edge of clock the count operation will be unaffected.
All of these counters may be cleared by utilizing the clear input. The clear function on the HD74HC162
and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive
edge of clock while the clear input is held low.
The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the
counter is cleared immediately regardless of the clock.
Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy
cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the
Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows.
This pulse is approximately equal in duration to the high level portion of the Q A outputs. The Ripple Carry
output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
Features
•
•
•
•
High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
HD74HC160/HD74HC161/HD74HC162/HD74HC163
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Clock
Note:
Outputs
1
Load
Enable P
Enable T
Qn
L
X
X
X
Reset-clear
H
L
X
X
Load input data
H
H
H
H
Count
H
H
L
X
No count
H
H
X
L
No count
Clear*
1. 162 and 163 Only-160 and 161 are Asynchronous Clear Devices
Decade Counter
Binary Counter
Asynchronous clear
HD74HC160P
HD74HC161P
Synchronous clear
HD74HC162P
HD74HC163P
Pin Arrangement
Clear 1
16 VCC
A 3
A
CLR
Ripple
Carry
QA
B 4
Data
Inputs C 5
B
QB
13 QB
C
QC
12 QC
D 6
D
QD
11 QD
Enable P 7
P
Clock 2
CK
14 QA
Outputs
Load
T
10 Enable T
9 Load
GND 8
(Top view)
2
Ripple
15 Carry Output
HD74HC160/HD74HC161/HD74HC162/HD74HC163
DC Characteristics
Ta = –40 to
+85°C
Ta = 25°C
Item
Symbol
VCC (V) Min Typ Max Min
Max
Unit
Input voltage
VIH
2.0
1.5 —
—
1.5
—
V
4.5
3.15 —
—
3.15
—
6.0
4.2 —
—
4.2
—
2.0
—
—
0.5
—
0.5
4.5
—
—
1.35 —
1.35
6.0
—
—
1.8
—
1.8
2.0
1.9 2.0 —
1.9
—
4.5
4.4 4.5 —
4.4
—
6.0
5.9 6.0 —
5.9
—
4.5
4.18 —
—
4.13
—
I OH = –4 mA
6.0
5.68 —
—
5.63
—
I OH = –5.2 mA
2.0
—
0.0 0.1
—
0.1
4.5
—
0.0 0.1
—
0.1
6.0
—
0.0 0.1
—
0.1
4.5
—
—
0.26 —
0.33
I OL = 4 mA
6.0
—
—
0.26 —
0.33
I OL = 5.2 mA
VIL
Output voltage
VOH
VOL
Test Conditions
V
V
V
Vin = VIH or VIL I OH = –20 µA
Vin = VIH or VIL I OL = 20 µA
Input current
Iin
6.0
—
—
±0.1 —
±1.0
µA
Vin = VCC or GND
Quiescent supply
current
I CC
6.0
—
—
4.0
40
µA
Vin = VCC or GND, Iout = 0 µA
—
3
HD74HC160/HD74HC161/HD74HC162/HD74HC163
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
+85°C
Ta = 25°C
Item
Symbol
VCC (V) Min Typ Max Min
Max
Unit Test Conditions
Maximum clock
f max
2.0
—
—
5
—
4
MHz
4.5
—
—
25
—
20
6.0
—
—
29
—
23
Propagation delay t PLH
2.0
—
—
160 —
200
time
4.5
—
18
32
—
40
6.0
—
—
27
—
34
2.0
—
—
225 —
280
4.5
—
23
45
—
56
6.0
—
—
38
—
48
2.0
—
—
150 —
190
4.5
—
15
30
—
38
6.0
—
—
26
—
33
2.0
—
—
200 —
250
4.5
—
16
40
—
50
6.0
—
—
34
—
43
2.0
125 —
—
156
—
4.5
25
9
—
31
—
6.0
21
—
—
26
—
2.0
125 —
—
156
—
4.5
25
15
—
31
—
6.0
21
—
—
26
—
2.0
125 —
—
156
—
Clear to Clock
4.5
25
—
—
31
—
(HC162, HC163 only)
6.0
21
—
—
26
—
2.0
0
—
—
0
—
4.5
0
–7
—
0
—
6.0
0
—
—
0
—
2.0
100 —
—
125
—
4.5
20
7
—
25
—
6.0
17
—
—
21
—
frequency
Setup time
Hold time
Removal time
4
t PHL
t su
th
t rem
ns
Clock to Q
ns
Clear to Q
(HC160, HC161 only)
ns
Enable T to Ripple Carry output
ns
Clock to Ripple carry output
ns
Data to Clock
Load to Clock
ns
ns
HD74HC160/HD74HC161/HD74HC162/HD74HC163
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = –40 to
+85°C
Ta = 25°C
Item
Symbol
VCC (V) Min Typ Max Min
Max
Unit
Pulse width
tw
2.0
80
—
—
100
—
ns
4.5
16
6
—
20
—
6.0
14
—
—
17
—
Output rise/fall
t TLH
2.0
—
—
75
—
95
time
t THL
4.5
—
5
15
—
19
6.0
—
—
13
—
16
—
—
5
10
—
10
Input capacitance
Cin
Test Conditions
ns
pF
Function Table
Count Enable/Disable
Control Inputs
Result at Outputs
Load
Enable P
Enable T
QA to QD
Ripple Carry Output
H
H
H
Count
High when QA to QD are maximum
L
H
H
No count
X
L
H
No count
High when QA to QD are maximum
X
H
L
No count
L
X
L
L
No count
L
5
HD74HC160/HD74HC161/HD74HC162/HD74HC163
Timing Diagram
HD74HC160/HD74HC162
Sequence illustrated in waveforms.
1.
2.
3.
4.
Clear outputs to zero.
Preset to BCD seven.
Count to eight, nine, zero, one, two and three.
Inhibit
Clear(HC160)
(Asynchronous)
Clear(HC162)
(Synchronous)
Load
A
Data
Inputs
B
C
D
Clock(HC160)
Clock(HC162)
Count
Enables
Enable P
Enable T
QA
Outputs
QB
QC
QD
Ripple
Carry
Output
7
Clear Load
6
8
9
0
1
Count
2
3
Inhibit
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC161/HD74HC163
Sequence illustrated in waveforms.
1.
2.
3.
4.
Clear outputs to zero.
Preset to binary twelve.
Count to thirteen, fourteen, fifteen, zero, one and two.
Inhibit
Clear(HC161)
(Asynchronous)
Clear(HC163)
(Synchronous)
Load
A
Data
Inputs
B
C
D
Clock(HC161)
Clock(HC163)
Count
Enables
Enable P
Enable T
QA
Outputs
QB
QC
QD
Ripple
Carry
Output
12 13 14
Clear Load
15
0
Count
1
2
Inhibit
7
HD74HC160/HD74HC161/HD74HC162/HD74HC163
Logic Diagram
HD74HC160
Decade Counter with Asynchronous Clear
T1
CLR
C
C
Load
Load
P1
A
T2
CLR
C
C
Load
Load
P2
B
T3
CLR
C
C
Load
Load
P3
C
T4
CLR
C
C
Load
Load
P4
D
Enable P
VCC
Enable T
Clear
CLR
Clock
C
C
Load
Load
Load
8
QA
QA
QA
QB
QB
QB
QC
QC
QC
QD
QD
QD
Ripple
Carry
Output
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC161
4-bit Binary Counter with Asynchronous Clear
T1
CLR
C
C
Load
Load
P1
A
T2
CLR
C
C
Load
Load
P2
B
T3
CLR
C
C
Load
Load
P3
C
T4
CLR
C
C
Load
Load
P4
D
Enable P
QA
QA
QA
QB
QB
QB
QC
QC
QC
QD
QD
QD
Ripple
Carry
Output
Enable T
Clear
CLR
Clock
C
C
Load
Load
Load
9
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC162
Decade Counter with Synchronous Clear
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
Q
Q
B
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
Q
C
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
Q
D
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
A
P
Q
VCC
RCO
CK
LD
LD
LD·CLR
CLR
10
QD
Q
LD·CLR
CLR
QC
Q
CK
LD
QB
Q
T
CK
QA
CLR
HD74HC160/HD74HC161/HD74HC162/HD74HC163
HD74HC163
4-bit Binary Counter with Synchronous Clear
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
Q
Q
B
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
Q
C
T
CK
CK
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
Q
D
T
CR
CR
LD
LD
LD·CLR
LD·CLR
CLR
CLR
IN
A
QA
Q
QB
Q
QC
Q
QD
Q
P
RCO
T
CK
CK
CK
LD
LD
LD
LD·CLR
LD·CLR
CLR
CLR
CLR
11
Unit: mm
19.20
20.00 Max
1
7.40 Max
9
6.30
16
8
1.3
0.48 ± 0.10
2.54 Min 5.06 Max
2.54 ± 0.25
0.51 Min
1.11 Max
7.62
+ 0.13
0.25 – 0.05
0° – 15°
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
DP-16
Conforms
Conforms
1.07 g
Unit: mm
10.06
10.5 Max
9
1
8
1.27
*0.42 ± 0.08
0.40 ± 0.06
0.10 ± 0.10
0.80 Max
*0.22 ± 0.05
0.20 ± 0.04
2.20 Max
5.5
16
0.20
7.80 +– 0.30
1.15
0° – 8°
0.70 ± 0.20
0.15
0.12 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DA
—
Conforms
0.24 g
Unit: mm
9.9
10.3 Max
9
1
8
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
0.15
*0.22 ± 0.03
0.20 ± 0.03
1.27
0.11
0.14 +– 0.04
1.75 Max
3.95
16
0.10
6.10 +– 0.30
1.08
0° – 8°
0.67
0.60 +– 0.20
0.25 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DN
Conforms
Conforms
0.15 g
Unit: mm
4.40
5.00
5.30 Max
16
9
1
8
0.65
0.13 M
1.10 Max
0.65 Max
0.10
*Dimension including the plating thickness
Base material dimension
6.40 ± 0.20
0.07 +0.03
–0.04
0.20 ± 0.06
1.0
*0.17 ± 0.05
0.15 ± 0.04
0.08
*0.22 +– 0.07
0° – 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-16DA
—
—
0.05 g
Cautions
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
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