HD74HC190/HD74HC191 Synchronous Up/Down Decade Counter (Single Clock Line) Synchronous Up/Donw 4-bit Binary Counter (Single Clock Line) Description The HD74HC190 and HD74HC191 are synchronous, reverside up/down counters. The HD74HC190 is a 4-bit decade counter and the HD74HC191 is a 4-bit binary counter. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the Enable G input is low. A high at Enable G inhibits counting. The direction of the count is determined by the level of the Down/ Up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. These counters feature a fully independent clock circuit. Changes at the control inputs (D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. Two outputs have been made available to perform the cascading function. Ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately qual to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9 or 15) counting up. The ripple clock output produces a low-level output pulse under those same conditions but only while the clock input is low. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if paralle enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. HD74HC190/HD74HC191 Features • • • • • High Speed Operation: tpd (Clock to Q) = 22 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Pin Arrangement Inputs Outputs 16 VCC Data B 1 QB 2 QB QA 3 QA B A 15 Data A Inputs CK Ripple Clock Enable G 4 G Down/Up 5 Dn/Up Max/Min 14 Clock 13 Ripple Clock Inputs QC 6 QC QD 7 QD Load Outputs 12 Max/Min 11 Load Outputs D C 9 Data D GND 8 (Top view) 2 10 Data C Inputs HD74HC190/HD74HC191 Timing Chart HD74HC190 Illustrated below is the following sequence: 1. 2. 3. 4. Load (preset) to BCD seven. Count up to eight, nine (maximum), zero, one and two. Inhibit Count down to one, zero (minimum), nine, eight and seven. Load A B C D Clock Down/Up Enable G QA QB QC QD Max/Min Ripple Clock 7 8 9 0 Count Up 1 2 2 2 1 Inhibit 0 9 8 7 Count Down Load 3 HD74HC190/HD74HC191 HD74HC191 Illustrated below is the following sequence: 1. 2. 3. 4. Load (preset) to binary thirteen. Count up to fourteen, fifteen (maximum), zero, one and two. Inhibit Count down to one, zero (minimum), fifteen, fourteen and thirteen. Load A Data Inputs B C D Clock Down/Up Enable G QA QB QC QD Max/Min Ripple Clock 13 14 15 0 Count Up Load 4 1 2 Inhibit 2 1 0 15 14 13 Count Down HD74HC190/HD74HC191 Logic Diagram HD74HC190 Clock Ripple Clock Max/Min Output Down/Up Input A Enable G CK P CK A INCL Q CK P CK B INCL Q CK P CK C INCL Q CK P CK D INCL Q QA Q Input B QB Q Input C QC Q Input D QD Q Load 5 HD74HC190/HD74HC191 HD74HC191 Clock Ripple Clock Max/Min Output Down/Up Input A Enable G CK P CK A INCL Q CK P CK B INCL Q CK P CK C INCL Q CK P CK D INCL Q QA Q Input B QB Q Input C QC Q Input D Load 6 Q QD HD74HC190/HD74HC191 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –4 mA 6.0 5.68 — — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 4 mA 6.0 — — 0.26 — 0.33 I OL = 5.2 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA — 7 HD74HC190/HD74HC191 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 5 — 4 MHz 4.5 — — 25 — 20 6.0 — — 29 — 24 Propagation delay t PLH 2.0 — — 265 — 335 time 4.5 — 21 53 — 66 6.0 — — 45 — 56 2.0 — — 230 — 290 4.5 — 18 46 — 58 6.0 — — 39 — 49 2.0 — — 120 — 150 4.5 — 14 24 — 30 6.0 — — 20 — 26 2.0 — — 190 — 240 4.5 — 22 38 — 48 6.0 — — 32 — 41 2.0 — — 250 — 315 4.5 — 26 50 — 63 6.0 — — 43 — 54 2.0 — — 230 — 290 4.5 — 20 46 — 58 6.0 — — 39 — 49 2.0 — — 130 — 165 4.5 — 14 26 — 33 6.0 — — 22 — 28 2.0 — — 190 — 240 4.5 — 17 38 — 48 6.0 — — 32 — 41 2.0 80 — — 100 — 4.5 16 8 — 20 — 6.0 14 – — 17 — 2.0 0 — — 0 — 4.5 0 –6 — 0 — 6.0 0 — — 0 — frequency Pulse width Hold time 8 t PHL tw th ns Test Conditions Load to Q Data to Q Clock to RC Clock to Q Clock to max/min Down/up to RC G to RC Down/up to max/min ns ns HD74HC190/HD74HC191 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Setup time t su 2.0 100 — — 125 — ns 4.5 20 7 — 25 — 6.0 17 — — 21 — Output rise/fall t TLH 2.0 — — 75 — 95 time t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 — — 5 10 — 10 Input capacitance Cin Test Conditions ns pF 9 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Cautions 1. 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