HD74HC164 8-bit Parallel-out Shift Register Description This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flipflop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and resets the first flip-vlop to the low level at the next clock pulse. A high level on the input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the clear input. Features • • • • • High Speed Operation: tpd (Clock to Q) = 14.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max Function Table Inputs Outputs Clear Clock A B QA QB ········· QH L X X X L L ········· L H X X QAo QBo ········· QHo H L X L QAn ········· QGn H X L L QAn ········· QGn H H H H QAn ········· QGn QAo to Q Ho = Outputs remain unchanged. QAn to Q Gn = Data shifted from the previous stage on a positive edge at the clock input. HD74HC164 Pin Arrangement Serial Inputs A 14 VCC 1 A B 2 B QH 13 QH QA 3 QA QG 12 QG QB 4 QB QF 11 QF QC 5 QC QE 10 QE QD 6 QD GND 7 Outputs Outputs CK CLR (Top view) Timing Diagram Clock A B Clear QA QB QC QD QE QF QG QH 2 9 Clear 8 Clock HD74HC164 Logic Diagram Clock A B D Q D Q D Q D Q D Q D Q D Q D Q CLR CLR CLR CLR CLR CLR CLR CLR Clear QA QB QC QD QE QF QG QH 3 HD74HC164 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –4 mA 6.0 5.68 — — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 4 mA 6.0 — — 0.26 — 0.33 I OL = 5.2 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA 4 — HD74HC164 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Maximum clock f max 2.0 — — 5 — 4 MHz 4.5 — — 25 — 20 6.0 — — 29 — 24 Propagation delay t PHL 2.0 — — 160 — 200 time 4.5 — 14 32 — 40 6.0 — — 27 — 34 2.0 — — 160 — 200 4.5 — 15 32 — 40 6.0 — — 27 — 34 2.0 — — 175 — 220 4.5 — 17 35 — 44 6.0 — — 30 — 37 2.0 100 — — 125 — 4.5 20 1 — 25 — 6.0 17 — — 21 — 2.0 5 — — 5 — 4.5 5 0 — 5 — 6.0 5 — — 5 — 2.0 5 — — 5 — 4.5 5 0 — 5 — 6.0 5 — — 5 — 2.0 80 — — 100 — 4.5 16 8 — 20 — 6.0 14 — — 17 — 2.0 80 — — 100 — 4.5 16 5 — 20 — 6.0 14 — — 17 — frequency t PLH t PHL Setup time Hold time Removal time Pulse width t su th t rem tw Output rise/fall t TLH 2.0 — — 75 — 95 time t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 — — 5 10 — 10 Input capacitance Cin ns Test Conditions Clock to Q ns ns Clear to Q ns A, B to Clock ns Clock to A, B ns Clear to Clock ns Clock ns Clear ns pF 5 Unit: mm 19.20 20.32 Max 8 6.30 7.40 Max 14 1.30 7 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.39 Max 2.54 Min 5.06 Max 1 7.62 + 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 8 5.5 14 1 0.10 ± 0.10 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7 + 0.20 7.80 – 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 *0.40 ± 0.06 0.11 0.14 +– 0.04 0° – 8° 1.27 0.67 0.60 +– 0.20 0.15 0.25 M *Pd plating Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g Cautions 1. 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