HITACHI HD74LV595A

HD74LV595A
8-bit Shift Registers with 3-state Outputs
ADE-205-281 (Z)
1st Edition
April 1999
Description
This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register anf the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register anf the storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register state will always be one clock pulse ahead of the storage
register. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
HD74LV595A
Function Table
Inputs
SER
SRCLK
SRCLR
RCLK
G
Function
X
X
X
X
H
Force outputs into high-impedance state
X
X
X
X
L
Enable paralle output
X
X
L
X
X
Reset shift register
L
↑
H
X
X
Shift data into shift register
H
↑
H
X
X
Shift data into shift register
X
↓
H
X
X
Shift register remains unchanged
X
X
X
↑
X
Transfer shift register contents to latch
register
X
X
X
↓
X
Latch register remains unchanged
Note: H:
L:
X:
↑:
↓:
2
High level
Low level
Immaterial
Low to high transition
High to low transition
HD74LV595A
Pin Arrangement
QB 1
16 VCC
QC 2
15 QA
QD 3
14 SER
QE 4
13 G
QF 5
12 RCLK
QG 6
11 SRCLK
QH 7
10 SRCLR
9 QH'
GND 8
(Top view)
3
HD74LV595A
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range*
1
Output voltage range*
1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 7.0
V
VI
–0.5 to 7.0
V
VO
–0.5 to VCC + 0.5
V
–0.5 to 7.0
Conditions
Output: H or L
Output: Z or V CC: OFF
Input clamp current
I IK
–20
mA
VI < 0
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±25
mA
VO = 0 to VCC
Continuous current through
VCC or GND
I CC or IGND
±70
mA
Maximum power dissipation
at Ta = 25°C (in still air)*3
PT
785
mW
500
Storage temperature
Tstg
–65 to 150
SOP
TSSOP
°C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
4
HD74LV595A
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
2.0
5.5
V
Input voltage range
VI
0
5.5
V
Output voltage range
VO
0
VCC
V
0
5.5
—
–50
µA
VCC = 2.0 V
—
–2
mA
VCC = 2.3 to 2.7 V
—
–6
VCC = 3.0 to 3.6 V
—
–12
VCC = 4.5 to 5.5 V
—
50
µA
VCC = 2.0 V
—
2
mA
VCC = 2.3 to 2.7 V
—
6
VCC = 3.0 to 3.6 V
—
12
VCC = 4.5 to 5.5 V
0
200
0
100
VCC = 3.0 to 3.6 V
0
20
VCC = 4.5 to 5.5 V
–40
85
Output current
I OH
I OL
Input transition rise or fall rate
Operating free-air temperature
∆t /∆v
Ta
Conditions
H or L
High impedance state
ns/V
VCC = 2.3 to 2.7 V
°C
Note: Unused or floating inputs must be held high or low.
5
HD74LV595A
Logic Diagram
G
RCLK
SRCLR
SRCLK
(13)
(12)
(10)
(11)
(14)
SER
1D
3R
C1
R
C3
3S
2S
2R
3R
C2
R
C3
3S
2S
2R
3R
C2
R
C3
3S
2S
2R
3R
C2
R
C3
3S
2S
2R
3R
C2
R
C3
3S
2S
2R
3R
C2
R
C3
3S
2S
2R
3R
C2
R
C3
3S
2S
2R
3R
C2
R
C3
3S
(15)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(9)
6
QA
QB
QC
QD
QE
QF
QG
QH
QH'
HD74LV595A
Timing Diagram
SRCLK
SER
RCLK
SRCLR
G
QA
QB
QC
QD
QE
QF
QG
QH
QH'
SHIFT
HIGH IMPEDANCE
CLEAR
7
HD74LV595A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item
Symbol
VCC (V)*
Min
Typ
Max
Unit
Input voltage
VIH
2.0
1.5
—
—
V
2.3 to 2.7
VCC × 0.7
—
—
3.0 to 3.6
VCC × 0.7
—
—
4.5 to 5.5
VCC × 0.7
—
—
2.0
—
—
0.5
2.3 to 2.7
—
—
VCC × 0.3
3.0 to 3.6
—
—
VCC × 0.3
4.5 to 5.5
—
—
VCC × 0.3
Min to
Max
VCC – 0.1
—
—
2.3
2.0
—
—
IOH = –2 mA
3.0
2.48
—
—
IOH = –6 mA
4.5
3.8
—
—
IOH = –12 mA
Min to
Max
—
—
0.1
IOL = 50 µA
2.3
—
—
0.4
IOL = 2 mA
3.0
—
—
0.44
IOL = 6 mA
4.5
—
—
0.55
IOL = 12 mA
VIL
Output voltage
VOH
VOL
V
Test Conditions
IOH = –50 µA
Input current
IIN
0 to 5.5
—
—
±1
µA
VIN = 5.5 V or GND
Off-state
output current
IOZ
5.5
—
—
±5
µA
VO = VCC or GND
Quiescent
supply current
ICC
5.5
—
—
20
µA
VIN = VCC or GND, IO = 0
Output leakage
current
IOFF
0
—
—
5
µA
VI or VO = 0 to 5.5 V
Input
capacitance
CIN
3.3
—
3.5
—
pF
VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
8
HD74LV595A
Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
Maximum
fmax
65
80
—
45
—
MHz
CL = 15 pF
60
70
—
40
—
—
11.6
16.4
1.0
19.5
—
14.8
19.4
1.0
22.5
CL = 50 pF
—
10.5
15.3
1.0
18.0
CL = 15 pF
—
13.7
18.3
1.0
21.0
CL = 50 pF
—
11.2
16.2
1.0
18.2
CL = 15 pF
—
14.4
19.2
1.0
21.2
CL = 50 pF
tZH
—
10.3
14.8
1.0
17.5
tZL
—
12.2
17.7
1.0
20.5
tHZ
—
7.6
11.5
1.0
13.5
tLZ
—
14.4
18.2
1.0
19.2
tSU
5.5
—
—
5.5
—
10.0
—
—
10.5
—
SRCLK ↑ before
RCLK ↑
10.0
—
—
11.0
—
SRCLR low before
RCLK ↑
5.0
—
—
5.0
—
SRCLR high
(inactive) before
SRCLK ↑
2.0
—
—
2.0
—
0.5
—
—
0.5
—
SRCLK ↑ after
RCLK ↑
0.5
—
—
0.5
—
SRCLR low after
RCLK ↑
7.0
—
—
7.5
—
7.0
—
—
7.5
—
SRCLK high or low
6.0
—
—
6.5
—
SRCLR low
clock
frequency
Propagation
tPLH/tPHL
delay time
tPHL
Enable time
Disable time
Setup time
Hold time
Pulse width
th
tw
FROM
(Input)
TO
(Output)
SRCLK
QH '
RCLK
Q A – QH
SRCLK
QH'
G
QA – QH
CL = 50 pF
ns
ns
CL = 15 pF
CL = 15 pF
CL = 50 pF
ns
CL = 15 pF
CL = 50 pF
ns
ns
ns
SER before SRCLK ↑
SER after SRCLK ↑
RCLK high or low
9
HD74LV595A
• VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
Maximum
fmax
80
150
—
70
—
MHz
CL = 15 pF
55
130
—
50
—
—
8.8
13.0
1.0
15.0
—
11.3
16.5
1.0
18.5
CL = 50 pF
—
7.7
11.9
1.0
13.5
CL = 15 pF
—
10.2
15.4
1.0
17.0
CL = 50 pF
—
8.4
12.8
1.0
13.7
CL = 15 pF
—
10.9
16.3
1.0
17.2
CL = 50 pF
tZH
—
7.5
11.5
1.0
13.5
tZL
—
9.0
15.0
1.0
17.0
tHZ
—
5.9
11.7
1.0
13.5
tLZ
—
12.1
15.7
1.0
16.2
tSU
3.5
—
—
3.5
—
8.0
—
—
8.5
—
SRCLK ↑ before RCLK ↑
8.0
—
—
9.0
—
SRCLR low before RCLK
clock
frequency
Propagation
tPLH/tPHL
delay time
tPHL
Enable time
Disable time
Setup time
FROM
(Input)
TO
(Output)
SRCLK
QH '
RCLK
Q A – QH
SRCLK
QH'
G
QA – QH
CL = 50 pF
ns
ns
CL = 15 pF
CL = 15 pF
CL = 50 pF
ns
CL = 15 pF
CL = 50 pF
ns
SER before SRCLK ↑
↑
Hold time
Pulse width
10
th
tw
SRCLR high (inactive)
before SRCLK ↑
3.0
—
—
3.0
—
1.5
—
—
1.5
—
0.0
—
—
0.0
—
SRCLK ↑ after RCLK ↑
0.0
—
—
0.0
—
SRCLR low after RCLK ↑
5.0
—
—
5.0
—
5.0
—
—
5.0
—
SRCLK high or low
5.0
—
—
5.0
—
SRCLR low
ns
ns
SER after SRCLK ↑
RCLK high or low
HD74LV595A
Switching Characteristics (cont)
• VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
Maximum
fmax
135
185
—
115
—
MHz
CL = 15 pF
95
155
—
85
—
—
6.2
8.2
1.0
9.4
—
7.7
10.2
1.0
11.4
CL = 50 pF
—
5.4
7.4
1.0
8.5
CL = 15 pF
—
6.9
9.4
1.0
10.5
CL = 50 pF
—
5.9
8.0
1.0
9.1
CL = 15 pF
—
7.4
10.0
1.0
11.1
CL = 50 pF
tZH
—
4.8
8.6
1.0
10.0
tZL
—
8.3
10.6
1.0
12.0
tHZ
—
4.8
8.6
1.0
10.0
tLZ
—
7.6
11.0
1.0
11.0
tSU
3.0
—
—
3.0
—
5.0
—
—
5.0
—
SRCLK ↑ before RCLK ↑
5.0
—
—
5.0
—
SRCLR low before RCLK ↑
2.5
—
—
2.5
—
SRCLR high (inactive)
before SRCLK ↑
2.0
—
—
2.0
—
0.0
—
—
0.0
—
SRCLK ↑ after RCLK ↑
0.0
—
—
0.0
—
SRCLR low after RCLK ↑
5.0
—
—
5.0
—
5.0
—
—
5.0
—
SRCLK high or low
5.0
—
—
5.0
—
SRCLR low
clock
frequency
Propagation
tPLH/tPHL
delay time
tPHL
Enable time
Disable time
Setup time
Hold time
Pulse width
th
tw
FROM
(Input)
TO
(Output)
SRCLK
QH '
RCLK
Q A – QH
SRCLK
QH'
G
QA – QH
CL = 50 pF
ns
ns
CL = 15 pF
CL = 15 pF
CL = 50 pF
ns
CL = 15 pF
CL = 50 pF
ns
ns
ns
SER before SRCLK ↑
SER after SRCLK ↑
RCLK high or low
11
HD74LV595A
Output-skew Characteristics
• CL = 50 pF
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
VCC = (V)
Min
Max
Min
Max
Unit
Output skew
t sk (O)
2.3 to 2.7
—
2.0
—
2.0
ns
3.0 to 3.6
—
1.5
—
1.5
4.5 to 5.5
—
1.0
—
1.0
Note: Skew between any outputs of the same package switching in the same direction. This parameter is
warranted but not production tested.
Operating Characteristics
• CL = 50 pF
Ta = 25°C
Item
Symbol
VCC = (V)
Min
Typ
Max
Unit
Test Conditions
Power
dissipation
capacitance
CPD
3.3
—
32.7
—
pF
f = 10 MHz
5.0
—
33.1
—
Test Conditions
Noise Characteristics
• CL = 50 pF
Ta = 25°C
Item
Symbol
VCC = (V)
Min
Typ
Max
Unit
Quiet output,
maximum
dynamic VOL
VOL (P)
3.3
—
0.65
0.8
V
Quiet output,
minimum
dynamic VOL
VOL (V)
3.3
—
–0.59
–0.8
Quiet output,
minimum
dynamic VOH
VOH (V)
3.3
—
2.84
—
High-level
dynamic
input voltage
VIH (D)
3.3
2.31
—
—
Low-level
dynamic
inout voltage
VIL (D)
3.3
—
—
0.99
12
HD74LV595A
Test Circuit
Output
1 KΩ
S2
OPEN
GND
CL
VCC
TEST
t PLH / t PHL
S2
OPEN
t ZH/ t HZ
t ZL / t LZ
GND
VCC
Note: C L includes the probe and jig capacitance.
13
HD74LV595A
Waveform – 1
tr
tf
VCC
90%
50% VCC
10%
SRCLK
GND
tw
1/fmax
tPLH
QH'
tPHL
90%
50% VCC
10%
tTLH
tTHL
Waveform – 2
tw
SRCLR
VCC
50% VCC
GND
QH'
tPHL
50% VCC
tsu
VCC
50% VCC
SRCLK
GND
Waveform – 3
VCC
RCLK
50% VCC
GND
tPLH/tPHL
QA-QH
14
50% VCC
HD74LV595A
Waveform – 4
tf
tr
90 %
G
VCC
90 %
50 % V CC
50 % V CC
10 %
t ZL
10 %
0V
t LZ
VCC
50 % V CC
Waveform – A
t ZH
VOL + 0.3 V
t HZ
Waveform – B
50 % V CC
VOH – 0.3 V
VOL
VOH
0V
Waveform – 5
Valid
VCC
50% VCC
SER
GND
tsu
th
VCC
SRCLK
50% VCC
GND
Waveform – 6
VCC
50% VCC
SRCLK
GND
tsu
VCC
RCLK
50%
VCC
GND
tw
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns
2. Waveform-A is for an output with internal conditions such that the output is low except when disabled
by the output control.
3. Waveform-B is for an output with internal conditions such that the output is high except when disabled
by the output control.
4. The output are measured one at a time with one transition per measurement.
15
HD74LV595A
Package Dimensions
10.06
10.5 Max
9
1
8
1.27
0.42 ± 0.08
0.40 ± 0.06
0.10 ± 0.10
0.80 Max
0.22 ± 0.05
0.20 ± 0.04
2.20 Max
5.5
16
0.20
7.80 +– 0.30
1.15
0° – 8°
0.70 ± 0.20
0.15
0.12 M
Dimension including the plating thickness
Base material dimension
16
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DA
—
Conforms
0.24 g
HD74LV595A
Unit: mm
9.9
10.3 Max
9
1
8
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
0.15
*0.22 ± 0.03
0.20 ± 0.03
1.27
0.11
0.14 +– 0.04
1.75 Max
3.95
16
0.10
6.10 +– 0.30
1.08
0° – 8°
+ 0.67
0.60 – 0.20
0.25 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DN
Conforms
Conforms
0.15 g
17
HD74LV595A
5.0
5.3 Max
9
1
8
4.40
16
0.65
0.13 M
1.10 Max
0.65 Max
0.10
Dimension including the plating thickness
Base material dimension
18
6.40 ± 0.20
0.07 +0.03
–0.04
0.20 ± 0.06
1.0
0.17 ± 0.05
0.15 ± 0.04
0.08
0.22 +– 0.07
0° – 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-16DA
—
—
0.05 g
Cautions
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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