HITACHI HD74LV166A

HD74LV166A
Parallel-Load 8-bit Shift Register
ADE-205-268 (Z)
1st Edition
March 1999
Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the
register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded
asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge
of either clock inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V operation
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
HD74LV166A
Function Table
Inputs
Internal outputs
Output
CLR
SH/LD
CLK INH
CLK
SER
A ... H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
↑
X
a ... h
a
b
h
H
H
L
↑
H
X
H
QAn
QGn
H
H
L
↑
L
X
L
QAn
QGn
H
X
H
↑
X
X
QA0
QB0
QH0
Note: H: High level
L: Low level
↑: Low to high transition
X: Immaterial
a ... h: Parallel data
QA0 ... Q H0: Outputs remain unchanged.
QAn ... Q Gn : Data shifted from the previous stage on a positive edge at the clock input.
Pin Arrangement
16 VCC
SER 1
A 2
15 SH/LD
B 3
14 H
C 4
13 QH
D 5
12 G
CLK INH 6
11 F
CLK 7
10 E
9 CLR
GND 8
(Top view)
2
HD74LV166A
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range*
1
Output voltage range*
1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 7.0
V
VI
–0.5 to 7.0
V
VO
–0.5 to VCC + 0.5
V
–0.5 to 7.0
Conditions
Output: H or L
VCC: OFF
Input clamp current
I IK
–20
mA
VI < 0
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±25
mA
VO = 0 to VCC
Continuous current through
VCC or GND
I CC or IGND
±50
mA
Maximum power dissipation
at Ta = 25°C (in still air)*3
PT
785
mW
500
Storage temperature
Tstg
–65 to 150
SOP
TSSOP
°C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
3
HD74LV166A
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
2.0
5.5
V
Input voltage range
VI
0
5.5
V
Output voltage range
VO
0
VCC
V
H or L
Output current
I OH
—
–50
µA
VCC = 2.0 V
—
–2
mA
VCC = 2.3 to 2.7 V
—
–6
VCC = 3.0 to 3.6 V
—
–12
VCC = 4.5 to 5.5 V
—
50
µA
VCC = 2.0 V
—
2
mA
VCC = 2.3 to 2.7 V
—
6
VCC = 3.0 to 3.6 V
—
12
VCC = 4.5 to 5.5 V
0
200
0
100
VCC = 3.0 to 3.6 V
0
20
VCC = 4.5 to 5.5 V
–40
85
I OL
Input transition rise or fall rate
Operating free-air temperature
∆t /∆v
Ta
Note: Unused or floating inputs must be held high or low.
4
ns/V
°C
Conditions
VCC = 2.3 to 2.7 V
HD74LV166A
Logic Diagram
A
SER
R CP S
CD
Q
B
C
D
E
F
G
CLR
H SH/LD CLK CLK INH
R CP S
Q
CD
QH
5
HD74LV166A
Timing Diagram
CLK
CLK INH
CLR
SER
SH/LD
Parallel
Inputs
A
H
B
L
C
H
D
L
E
H
L
F
G
H
H
H
H
Output QH
Serial shift
Clear
6
Inhibit
Load
H
L
H
L
H
Serial shift
L
H
L
HD74LV166A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item
Symbol
VCC (V)*
Min
Typ
Max
Unit
Input voltage
VIH
2.0
1.5
—
—
V
2.3 to 2.7
VCC × 0.7
—
—
3.0 to 3.6
VCC × 0.7
—
—
4.5 to 5.5
VCC × 0.7
—
—
2.0
—
—
0.5
2.3 to 2.7
—
—
VCC × 0.3
3.0 to 3.6
—
—
VCC × 0.3
4.5 to 5.5
—
—
VCC × 0.3
Min to
Max
VCC – 0.1
—
—
2.3
2.0
—
—
IOL = –2 mA
3.0
2.48
—
—
IOL = –6 mA
4.5
3.8
—
—
IOL = –12 mA
Min to
Max
—
—
0.1
IOL = 50 µA
2.3
—
—
0.4
IOL = 2 mA
3.0
—
—
0.44
IOL = 6 mA
4.5
—
—
0.55
IOL = 12 mA
VIL
Output voltage
VOH
VOL
V
Test Conditions
IOL = –50 µA
Input current
IIN
0 to 5.5
—
—
±1
µA
VI = 5.5 V or GND
Quiescent
supply current
ICC
5.5
—
—
20
µA
VI = VCC or GND, IO = 0
Output leakage
current
IOFF
0
—
—
5
µA
VI or VO = 0 V to 5.5 V
Input
capacitance
CIN
3.3
—
1.7
—
pF
VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
7
HD74LV166A
Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
Maximum
clock
frequency
fmax
50
80
—
45
—
MHz
CL = 15 pF
40
65
—
35
—
—
12.2
19.8
1.0
22.0
—
15.3
23.3
1.0
26.0
CL = 50 pF
—
10.8
16.0
1.0
18.0
CL = 15 pF
—
14.2
19.5
1.0
22.0
CL = 50 pF
7.0
—
—
7.0
—
6.5
—
—
8.5
—
7.0
—
—
8.5
—
8.5
—
—
9.5
—
–0.5
—
—
0.0
—
–0.5
—
—
0.0
—
SER data after CLK ↑
–0.5
—
—
0.0
—
SH/LD high after CLK ↑
8.0
—
—
9.0
—
8.5
—
—
9.0
—
Propagation
delay time
tPLH/tPHL
tPHL
Setup time
Hold time
Pulse
width
8
tsu
th
tw
FROM
(Input)
TO
(Output)
CLK
QH
CL = 50 pF
ns
ns
CL = 15 pF
CLR
CLK INH before CLK ↑
Data before CLK ↑
ns
SH/LD high before CLK ↑
SER before CLK ↑
ns
ns
PAR data after SH/LD ↑
CLR low
CLK H or L
HD74LV166A
Switching Characteristics (cont)
• VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
Maximum
clock
frequency
fmax
65
115
—
55
—
MHz
CL = 15 pF
60
90
—
50
—
—
8.6
15.4
1.0
18.0
—
10.9
18.9
1.0
21.5
CL = 50 pF
—
7.9
12.5
1.0
15.0
CL = 15 pF
—
10.4
16.3
1.0
18.5
CL = 50 pF
5.0
—
—
5.0
—
5.0
—
—
6.0
—
5.0
—
—
6.0
—
5.0
—
—
6.0
—
0.0
—
—
0.0
—
0.0
—
—
0.0
—
SER data after CLK ↑
0.0
—
—
0.0
—
SH/LD high after CLK ↑
6.0
—
—
7.0
—
6.0
—
—
7.0
—
Propagation
delay time
tPLH/tPHL
tPHL
Setup time
Hold time
Pulse
width
tsu
th
tw
FROM
(Input)
TO
(Output)
CLK
QH
CL = 50 pF
ns
ns
CL = 15 pF
CLR
CLK INH before CLK ↑
Data before CLK ↑
ns
SH/LD high before CLK ↑
SER before CLK ↑
ns
ns
PAR data after SH/LD ↑
CLR low
CLK H or L
9
HD74LV166A
Switching Characteristics (cont)
• VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test
Conditions
Maximum
clock
frequency
fmax
110
165
—
90
—
MHz
CL = 15 pF
95
125
—
85
—
—
6.0
9.9
1.0
11.5
—
7.7
11.9
1.0
13.5
CL = 50 pF
—
5.4
8.6
1.0
10.0
CL = 15 pF
—
6.9
10.6
1.0
12.0
CL = 50 pF
3.5
—
—
3.5
—
4.5
—
—
4.5
—
4.0
—
—
4.0
—
4.0
—
—
4.0
—
1.0
—
—
1.0
—
1.0
—
—
1.0
—
SER data after CLK ↑
1.0
—
—
1.0
—
SH/LD high after CLK ↑
5.0
—
—
5.0
—
4.0
—
—
4.0
—
Propagation
delay time
tPLH/tPHL
tPHL
Setup time
Hold time
Pulse
width
10
tsu
th
tw
FROM
(Input)
TO
(Output)
CLK
QH
CL = 50 pF
ns
ns
CL = 15 pF
CLR
CLK INH before CLK ↑
Data before CLK ↑
ns
SH/LD high before CLK ↑
SER before CLK ↑
ns
ns
PAR data after SH/LD ↑
CLR low
CLK H or L
HD74LV166A
Operating Characteristics
•
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test Conditions
Power
dissipation
capacitance
CPD
3.3
—
36.1
—
pF
f = 10 MHz
5.0
—
37.5
—
Test Circuit
Measurement point
CL*
Note: C L includes the probe and jig capacitance.
11
HD74LV166A
Waveform
tW
VCC
CLR
50%VCC
50%VCC
tn
tn+1
tn
0V
tn+1
VCC
CLK
50%VCC
50%VCC
50%VCC
0V
tW
tsu
Data
50%VCC
50%VCC
th
tsu
50%VCC
th
VCC
50%VCC
50%VCC
0V
tPHL
tPHL
tPHL
VOH
Output QH
50%VCC
50%VCC
50%VCC
VOL
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
12
HD74LV166A
Package Dimensions
10.06
10.5 Max
9
1
8
1.27
0.42 ± 0.08
0.40 ± 0.06
0.10 ± 0.10
0.80 Max
0.22 ± 0.05
0.20 ± 0.04
2.20 Max
5.5
16
0.20
7.80 +– 0.30
1.15
0° – 8°
0.70 ± 0.20
0.15
0.12 M
Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DA
—
Conforms
0.24 g
13
HD74LV166A
Unit: mm
9.9
10.3 Max
9
1
8
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
0.15
*0.22 ± 0.03
0.20 ± 0.03
1.27
0.11
0.14 +– 0.04
1.75 Max
3.95
16
0.10
6.10 +– 0.30
1.08
0° – 8°
+ 0.67
0.60 – 0.20
0.25 M
*Dimension including the plating thickness
Base material dimension
14
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
FP-16DN
Conforms
Conforms
0.15 g
HD74LV166A
5.0
5.3 Max
9
1
8
4.40
16
0.65
0.20 ± 0.06
1.0
0.13 M
6.40 ± 0.20
0.10
Dimension including the plating thickness
Base material dimension
0.17 ± 0.05
0.15 ± 0.04
1.10 Max
0.65 Max
0.07 +0.03
–0.04
0.08
0.22 +– 0.07
0° – 8°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-16DA
—
—
0.05 g
15
Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
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written approval from Hitachi.
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products.
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