HM5116100 Series 16 M FP DRAM (16-Mword × 1-bit) 4 k Refresh ADE-203-646E (Z) Rev. 5.0 Nov. 1997 Description The Hitachi HM5116100 is a CMOS dynamic RAM organized 16,777,216-word × 1-bit. It employs the most advanced 0.5µm CMOS technology for high performance and low power. The HM5116100 offers Fast Page Mode as a high speed access mode. It is packaged in 26-pin plastic SOJ. Features • Single 5 V (±10%) • Access time: 60 ns/70 ns (max) • Power dissipation Active mode: 440 mW/385 mW (max) Standby mode 11 mW (max) • Fast page mode capability • Refresh cycles 4096 refresh cycles : 64 ms • 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh • Test function 16-bit parallel test mode Ordering Information Type No. Access time Package HM5116100S-6 HM5116100S-7 60 ns 70 ns 300-mil 26-pin plastic SOJ (CP-26/24DB) HM5116100 Series Pin Arrangement HM5116100S Series VCC 1 26 VSS Din 2 25 Dout NC 3 24 NC WE 4 23 CAS RAS 5 22 NC A11 6 21 A9 A10 8 19 A8 A0 9 18 A7 A1 10 17 A6 A2 11 16 A5 A3 12 15 A4 13 14 VSS VCC (Top view) Pin Description Pin name Function A0 to A11 Address input • Row/Refresh A0 to A11 • Column A0 to A11 Din Data input Dout Data output RAS Row address strobe CAS Column address strobe WE Read/write enable VCC Power supply VSS Ground NC No connection 2 HM5116100 Series Block Diagram RAS CAS WE Timing and control A0 Column decoder A1 to Column • • • address buffers • • • Row address buffers Row decoder A11 Din buffer Din Dout buffer Dout 16M array 3 HM5116100 Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Note Supply voltage VCC 4.5 5.0 5.5 V 1 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Note: 4 1. All voltage referred to VSS HM5116100 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM5116100 -6 Parameter -7 Symbol Min Max Min Max Unit Test conditions Operating current I CC1 — 80 — 70 mA t RC = min Standby current I CC2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 mA CMOS interface RAS, CAS ≥ V CC – 0.2V Dout = High-Z I CC3 — 80 — 70 mA t RC = min I CC5 — 5 — 5 mA RAS = VIH, CAS = VIL Dout = enable I CC6 — 80 — 70 mA t RC = min I CC7 — 70 — 60 mA t PC = min Input leakage current I LI –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V Output leakage current I LO –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –5 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 4.2 mA *1, *2 RAS-only refresh current*2 Standby current *1 CAS-before-RAS refresh current Fast page mode current *1, *3 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address, Data-in) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-out) CO — 7 pF 1, 2 Notes: 1. Capacitance measured with Booton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 5 HM5116100 Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)*1, *2, *16 Test Conditions • Input rise and fall time : 5 ns • Input timing reference levels : 0.8 V, 2.4 V • Output load : 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit Random read or write cycle time t RC 110 — 130 — ns RAS precharge time t RP 40 — 50 — ns CAS precharge time t CP 10 — 10 — ns RAS pulse width t RAS 60 10000 70 10000 ns CAS pulse width t CAS 15 10000 18 10000 ns Row address setup time t ASR 0 — 0 — ns Row address hold time t RAH 10 — 10 — ns Column address setup time t ASC 0 — 0 — ns Column address hold time t CAH 10 — 15 — ns RAS to CAS delay time t RCD 20 45 20 52 ns 3 RAS to column address delay time t RAD 15 30 15 35 ns 4 RAS hold time t RSH 15 — 18 — ns CAS hold time t CSH 60 — 70 — ns CAS to RAS precharge time t CRP 5 — 5 — ns Transition time (rise and fall) tT 3 50 3 50 ns 6 Notes 5 HM5116100 Series Read Cycle HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 ns 6, 7, 17 Access time from CAS t CAC — 15 — 18 ns 7, 8, 15, 17 Access time from address t AA — 30 — 35 ns 7, 9, 15, 17 Read command setup time t RCS 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — ns 10 Read command hold time to RAS t RRH 0 — 0 — ns 10 Column address to RAS lead time t RAL 30 — 35 — ns Column address to CAS lead time t CAL 30 — 35 — ns CAS to output in low-Z t CLZ 0 — 0 — ns Output data hold time t OH 3 — 3 — ns Output buffer turn-off time t OFF — 15 — 15 ns 11 Write Cycle HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — ns 12 Write command hold time t WCH 10 — 15 — ns Write command pulse width t WP 10 — 10 — ns Write command to RAS lead time t RWL 15 — 18 — ns Write command to CAS lead time t CWL 15 — 18 — ns Data-in setup time t DS 0 — 0 — ns 13 Data-in hold time t DH 10 — 15 — ns 13 7 HM5116100 Series Read-Modify-Write Cycle HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 130 — 153 — ns RAS to WE delay time t RWD 60 — 70 — ns 12 CAS to WE delay time t CWD 15 — 18 — ns 12 Column address to WE delay time t AWD 30 — 35 — ns 12 Notes Refresh Cycle HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 — 5 — ns CAS hold time (CBR refresh cycle) t CHR 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 0 — 0 — ns WE hold time (CBR refresh cycle) t WRH 10 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 5 — ns Fast Page Mode Cycle HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit Fast page mode cycle time t PC 40 — 45 — ns Fast page mode RAS pulse width t RASP — 100000 — 100000 ns 14 Access time from CAS precharge t CPA — 35 — 40 ns 7, 15, 17 RAS hold time from CAS precharge t CPRH 35 — 40 — ns 8 Notes HM5116100 Series Fast Page Mode Read-Modify-Write Cycle HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit Notes Fast page mode read-modify-write cycle time t PRWC 60 — 68 — ns WE delay time from CAS precharge t CPW 35 — 40 — ns 12 Notes Test Mode Cycle *16 HM5116100 -6 -7 Parameter Symbol Min Max Min Max Unit Test mode WE setup time t WTS 0 — 0 — ns Test mode WE hold time t WTH 10 — 10 — ns Refresh Cycle Parameter Symbol Max Unit Note Refresh period t REF 64 ms 4096 cycles 9 HM5116100 Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 8. Assume that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 9. Assume that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ t CWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 13. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 14. t RASP defines RAS pulse width in fast page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0, CA1, CA10 and CA11 for the 16M × 1 are don’t care during test mode. Test mode is set by performing a WEand-CAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 16 bits in parallel at Din and read out from Dout. If 16 bits are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CASbefore-RAS refresh cycle or RAS-only refresh cycle. 17. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout 10 HM5116100 Series Timing Waveforms*18 Read Cycle t RC t RAS t RP RAS t CSH t RCD t CRP t RSH t CAS tT CAS t RAD t ASR Address t RAH t RAL t CAL t CAH t ASC Column Row t RRH t RCH t RCS WE t CAC t AA t OH t OFF t RAC t CLZ Dout Dout 11 HM5116100 Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS 12 t WCS (min) HM5116100 Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD t CRP t RSH t CAS tT CAS t ASR Address t RAH Row t ASC t CAH Column t CWL t RWL t RCS t WP WE t DS t DH Din Din t CLZ t OFF Dout Invalid Dout 13 HM5116100 Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t CRP t RCD t CAS CAS t RAD t ASR Address t RAH Row t ASC t CAH Column t RCS t CWL t CWD t AWD t RWD t RWL t WP WE t DS Din t DH Din t CAC t OH t AA t OFF t RAC t CLZ Dout 14 Dout HM5116100 Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t RPC t CRP t CRP CAS t ASR Address t RAH Row t OFF High-Z Dout CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RC t RP t RAS t RP RAS t RPC t CP tT t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP t WRH WE Address t OFF Dout High-Z 15 HM5116100 Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASR Address t RAH t RAL t CAH t ASC Row Column t WRP t RCS t RRH t WRH t WRP t WRH WE t CAC t OH t AA t OFF t RAC t CLZ Dout 16 Dout HM5116100 Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t ASC t RAL t CAL t CAH t CRP CAS t RAD t ASR Address t RAH Row t ASC t CAL t CAH t ASC Column 1 t RCS t CAL t CAH Column 2 Column N t RCS t RCS t RCH tRRH t RCH tRCH WE t CAC t CPA t RAC t CLZ Dout t CPA t AA t AA t AA t OH t OFF Dout 1 t CAC t CLZ t OH t OFF Dout 2 t CAC t CLZ t OH t OFF Dout N 17 HM5116100 Series Fast Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS Address t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS 18 t WCS (min) HM5116100 Series Fast Page Mode Delayed Write Cycle t RASP t RP RAS tT t CSH t PC t RCD t CAS t CP t CAS t CP t RSH t CAS t CAH t ASC t CAH t ASC t CAH t CRP CAS t ASR Address t RAH Row t ASC Column 1 Column 2 Column N t RWL t CWL t RCS t WP t CWL t RCS t WP t CWL t RCS t WP WE t DH t DS t DH t DS t DH t DS Din Din 1 Din 2 t CLZ t OFF Din N t CLZ t OFF t CLZ t OFF Dout Invalid Dout Invalid Dout Invalid Dout 19 HM5116100 Series Fast Page Mode Read-Modify-Write Cycle t RP t RASP RAS tT t PRWC t RCD t CAS t CP t RSH t CAS t CP t CRP t CAS CAS t ASR Address t RAD t RAH t ASC Row t CAH t CAH t CAH t ASC Column 1 t ASC Column 2 Column N t RCS t RCS t AWD t RWD t RCS t CWL t RWL t CWL t CWL t AWD t AWD t WP t WP t WP WE t CWD t CWD t CPW t DS t DS t DS t DH t DH t DH t CWD t CPW Din 1 Din Din 2 t CAC t CAC t AA t RAC t CLZ Dout 20 Din N t CAC t CPA t OH t OFF Dout 1 t AA t CLZ t CPA t OH t OFF Dout 2 t AA t OH t CLZ Dout N t OFF HM5116100 Series Test Mode Cycle*16 Set Cycle** *,** Reset Cycle Test Mode Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din: H or L Test Mode Set Cycle t RC t RP t RAS t RP RAS t CSR t CHR tT t CRP CAS t RPC @ À À@ À@ t RPC t CP WE t WTS t WTH t CP Address t OFF Dout High-Z 21 HM5116100 Series Package Dimensions HM5116100S Series (CP-26/24DB) Unit: mm 1.30 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 2.54 Dimension including the plating thickness Base material dimension 22 2.65 ± 0.12 13 0.80 +0.25 –0.17 6 8 0.74 3.50 ± 0.26 1 8.51 ± 0.13 14 7.62 ± 0.13 26 16.90 17.27 Max 21 19 + 0.19 6.79 – 0.18 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) CP-26/24DB Conforms Conforms 0.8 g HM5116100 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 23 HM5116100 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 1.0 Oct. 14, 1996 Initial issue Y. Kasama M. Mishima 2.0 Dec. 10, 1996 Addition of HM5116100-5 Series Y. Kasama Y. Matsuno 3.0 Feb. 27, 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns Y. Kasama Y. Matsuno 4.0 Jun. 24, 1997 Deletion of HM5116100-5 Series Y. Kasama Y. Matsuno 5.0 Nov. 1997 Change of Subtitle 24