HB56A841BR Series, HB56A441BR Series 8,388,608-word × 40-bit High Density Dynamic RAM Module 4,194,304-word × 40-bit High Density Dynamic RAM Module ADE-203-731A (Z) Rev.1.0 Feb. 20, 1997 Description The HB56A841BR is a 8M × 40 dynamic RAM module, mounted 20 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package. The HB56A441BR is a 4M × 40 dynamic RAM module, mounted 10 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package. An outline of the HB56A841BR, HB56A441BR is 72-pin single in-line package. Therefore, the HB56A841BR, HB56A441BR make high density mounting possible without surface mount technology. The HB56A841BR, HB56A441BR provide common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features • 72-pin single in-line package Outline: 107.95 mm (Length) × 25.40 mm (Height) × 9.14/5.28 mm (Thickness) Lead pitch: 1.27 mm • Single 5 V (±5%) supply • High speed Access time: tRAC = 50/60/70ns (max) • Low power dissipation Active mode: 5.52/4.99/4.46 W (max) (HB56A841BR Series) 5.25/4.73/4.20 W (max) (HB56A441BR Series) Standby mode (TTL): 210 mW (max) (HB56A841BR Series) (TTL): 105 mW (max) (HB56A441BR Series) (CMOS): 105 mW (max) (HB56A841BR Series) (CMOS): 52.5 mW (max) (HB56A441BR Series) • Fast page mode capability • Refresh period 2048 refresh cycles: 32 ms • 3 variations of refresh RAS-only refresh CAS-before-RAS refresh This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Hidden refresh • TTL compatible Ordering Information Type No. Access time Package Contact pad HB56A841BR-5 HB56A841BR-6 HB56A841BR-7 50 ns 60 ns 70 ns 72-pin SIP socket type Gold HB56A441BR-5 HB56A441BR-6 HB56A441BR-7 50 ns 60 ns 70 ns 2 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Pin Arrangement 1Pin 36Pin 37Pin 72Pin Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 19 OE 37 DQ19 55 DQ28 2 DQ0 20 DQ8 38 DQ20 56 DQ29 3 DQ1 21 DQ9 39 VSS 57 DQ30 4 DQ2 22 DQ10 40 CAS0 58 DQ31 5 DQ3 23 DQ11 41 A10 59 VCC 6 DQ4 24 DQ12 42 NC 60 DQ32 61 DQ33 62 DQ34 63 DQ35 7 DQ5 25 DQ13 43 CAS1 (NC)* 8 DQ6 26 DQ14 44 RAS0 1 9 DQ7 27 DQ15 45 RAS1 (NC)* 10 VCC 28 A7 46 DQ21 64 DQ36 11 PD4 29 DQ16 47 WE 65 DQ37 12 A0 30 VCC 48 × 40 (VSS ) 66 DQ38 13 A1 31 A8 49 DQ22 67 PD0 14 A2 32 A9 50 DQ23 68 PD1 15 A3 33 NC 51 DQ24 69 PD2 16 A4 34 NC 52 DQ25 70 PD3 17 A5 35 DQ17 53 DQ26 71 DQ39 18 A6 36 DQ18 54 DQ27 72 VSS 2 Notes: 1. CAS1: HB56A841BR, NC: HB56A441BR 2. RAS1: HB56A841BR, NC: HB56A441BR 3 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Pin Description Pin name Function A0 to A10 Address inputs: • Row address: A0 to A10 • Column address: A0 to A10 • Refresh address: A0 to A10 DQ0 to DQ39 Data-in/Data-out CAS0, CAS1 Column address strobe RAS0, RAS1 Row address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground PD0 to PD4 Presence detect pin NC No connection Presence Detect Pin Arrangement (HB56A841BR) Function Pin No. Pin name 50 ns 60 ns 70 ns 67 PD0 NC NC NC 68 PD1 VSS VSS VSS 69 PD2 VSS NC VSS 70 PD3 VSS NC NC 11 PD4 VSS VSS VSS Presence Detect Pin Arrangement (HB56A441BR) Function Pin No. Pin name 50 ns 60 ns 70 ns 67 PD0 VSS VSS VSS 68 PD1 NC NC NC 69 PD2 VSS NC VSS 70 PD3 VSS NC NC 11 PD4 VSS VSS VSS 4 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Block Diagram (HB56A841BR) RAS1 CAS1 RAS0 CAS0 DQ0 DQ1 DQ2 DQ3 I/O I/O I/O I/O CAS RAS D0 I/O I/O I/O I/O CAS RAS D10 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O CAS RAS D1 I/O I/O I/O I/O CAS RAS D11 DQ8 DQ9 DQ10 DQ11 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS DQ16 DQ17 DQ18 DQ19 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS DQ24 DQ25 DQ26 DQ27 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS DQ32 DQ33 DQ34 DQ35 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS DQ36 DQ37 DQ38 DQ39 I/O I/O I/O I/O CAS RAS I/O I/O I/O I/O CAS RAS D2 D3 D4 D5 D6 D7 D8 D9 A0 to A10 D0 – D19 WE D0 – D19 OE D0 – D19 VCC VSS D12 D13 D14 D15 D16 D17 D18 D19 D0 – D19 0.22 µF × 10 pcs D0 – D19 Note: D0 – D19 : HM5117400 5 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Block Diagram (HB56A441BR) RAS0 CAS0 DQ0 DQ1 DQ2 DQ3 I/O I/O I/O I/O CAS RAS D0 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O CAS RAS D1 DQ8 DQ9 DQ10 DQ11 I/O I/O I/O I/O CAS RAS DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O CAS RAS DQ16 DQ17 DQ18 DQ19 I/O I/O I/O I/O CAS RAS DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O CAS RAS DQ24 DQ25 DQ26 DQ27 I/O I/O I/O I/O CAS RAS DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O CAS RAS DQ32 DQ33 DQ34 DQ35 I/O I/O I/O I/O CAS RAS DQ36 DQ37 DQ38 DQ39 I/O I/O I/O I/O CAS RAS D2 D3 D4 D5 D6 D7 D8 D9 A0 – A10 D0 – D9 WE D0 – D9 OE D0 – D9 VCC VSS D0 – D9 0.22 µF × 10 pcs D0 – D9 Note: D0 – D9 : HM5117400 6 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT −1.0 to +7.0 V Supply voltage relative to VSS VCC −1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation Pt 10 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg −55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VSS 0 0 0 V VCC 4.75 5.0 5.25 V 1 Input high voltage VIH 2.4 5.5 V 1 Input low voltage VIL −1.0 0.8 V 1 Note: Note 1. All voltage referred to VSS . 7 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V) (HB56A841BR) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current I CC1 1050 850 mA t RC = min 1, 2 Standby current I CC2 40 40 40 mA TTL interface, RAS, CAS = VIH, Dout = High-Z 20 20 20 mA CMOS interface, RAS, CAS ≥ V CC − 0.2 V, Dout = High-Z 950 RAS-only refresh current I CC3 1050 950 850 mA t RC = min 2 Standby current I CC5 100 100 100 mA RAS = VIH, CAS = VIL, Dout = enable 1 CAS-before-RAS refresh current I CC6 1050 950 850 mA t RC = min Fast page mode current I CC7 950 850 750 mA t PC = min Input leakage current I LI −10 10 −10 10 −10 10 µA 0 V ≤ Vin ≤ 5.5 V Output leakage current I LO −10 10 −10 10 −10 10 µA 0 V ≤ Vout ≤ 5.5 V, Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = −5 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA 1, 3 Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 8 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V) (HB56A441BR) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current I CC1 1000 800 mA t RC = min 1, 2 Standby current I CC2 20 20 20 mA TTL interface, RAS, CAS = VIH, Dout = High-Z 10 10 10 mA CMOS interface, RAS, CAS ≥ V CC − 0.2 V, Dout = High-Z 900 RAS-only refresh current I CC3 1000 Standby current I CC5 50 CAS-before-RAS refresh current I CC6 1000 900 800 mA t RC = min Fast page mode current I CC7 900 800 700 mA t PC = min Input leakage current I LI −10 10 −10 10 −10 10 µA 0 V ≤ Vin ≤ 5.5 V Output leakage current I LO −10 10 −10 10 −10 10 µA 0 V ≤ Vout ≤ 5.5 V, Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = −5 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA 900 50 800 mA t RC = min 2 50 RAS = VIH, CAS = VIL, Dout = enable 1 mA 1, 3 Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 9 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Capacitance (Ta = 25°C, VCC = 5 V ± 5%) (HB56A841BR) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 140 pF 1 Input capacitance (WE, OE) CI2 160 pF 1 Input capacitance (RAS, CAS) CI3 90 pF 1 I/O capacitance (DQ) CI/O 25 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. Capacitance (Ta = 25°C, VCC = 5 V ± 5%) (HB56A441BR) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 90 pF 1 Input capacitance (WE, OE) CI2 90 pF 1 Input capacitance (RAS, CAS) CI3 90 pF 1 I/O capacitance (DQ) CI/O 20 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 10 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series AC Characteristics (Ta = 0 to 70˚C, VCC = 5 V ±5%, VSS = 0 V) *1, *2, *18, *19 Test Conditions • • • • Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 90 110 130 ns RAS precharge time t RP 30 40 50 ns CAS precharge time t CP 7 10 10 ns RAS pulse width t RAS 50 10000 60 10000 70 10000 ns CAS pulse width t CAS 13 10000 15 10000 18 10000 ns Row address setup time t ASR 0 0 0 ns Row address hold time t RAH 7 10 10 ns Column address setup time t ASC 0 0 0 ns Column address hold time t CAH 7 10 15 ns RAS to CAS delay time t RCD 17 37 20 45 20 52 ns 3 RAS to column address delay time t RAD 12 25 15 30 15 35 ns 4 RAS hold time t RSH 13 15 18 ns CAS hold time t CSH 50 60 70 ns CAS to RAS precharge time t CRP 5 5 5 ns OE to Din delay time t OED 13 15 18 ns 5 OE delay time from Din t DZO 0 0 0 ns 6 CAS delay time from Din t DZC 0 0 0 ns 6 Transition time (rise and fall) t T 3 50 3 50 3 50 ns 7 Refresh period (2,048 cycles) 32 32 32 ms t REF Notes 11 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Read Cycle 50 ns Parameter Symbol Min Access time from RAS t RAC Access time from CAS 60 ns 70 ns Max Min Max Min Max Unit Notes 50 60 70 ns 8, 9 t CAC 13 15 18 ns 9, 10, 17 Access time from address t AA 25 30 35 ns 9, 11, 17 Access time from OE t OEA 13 15 18 ns 9, 20 Read command setup time t RCS 0 0 0 ns Read command hold time to t RCH CAS 0 0 0 ns 12 Read command hold time to t RRH RAS 5 5 5 ns 12 Column address to RAS lead time t RAL 25 30 35 ns Column address to CAS lead time t CAL 25 30 35 ns CAS to output in low-Z t CLZ 0 0 0 ns Output data hold time t OH 3 3 3 ns Output data hold time from OE t OHO 3 3 3 ns Output buffer turn-off time t OFF 13 15 15 ns 13 Output buffer turn-off to OE t OEZ 13 15 15 ns 13 CAS to Din delay time t CDD 13 15 18 ns 5 Write Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 0 0 ns 14 Write command hold time t WCH 7 10 15 ns Write command pulse width t WP 7 10 10 ns Write command to RAS lead t RWL time 13 15 18 ns Write command to CAS lead t CWL time 13 15 18 ns Data-in setup time t DS 0 0 0 ns 15 Data-in hold time t DH 7 10 15 ns 15 12 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Read-Modify-Write Cycle 50 ns Parameter Symbol Min 60 ns 70 ns Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 131 155 181 ns RAS to WE delay time t RWD 73 85 98 ns 14 CAS to WE delay time t CWD 36 40 46 ns 14 Column address to WE delay time t AWD 48 55 63 ns 14 OE hold time from WE t OEH 13 15 18 ns Refresh Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 5 5 ns CAS hold time (CBR refresh cycle) t CHR 7 10 10 ns WE setup time (CBR refresh cycle) t WRP 0 0 0 ns WE hold time (CBR refresh cycle) t WRH 7 10 10 ns RAS precharge to CAS hold t RPC time 5 5 5 ns Notes Fast Page Mode Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Fast page mode cycle time t PC 35 40 45 ns Fast page mode RAS pulse t RASP width 100000 Access time from CAS precharge t CPA 30 35 RAS hold time from CAS precharge t CPRH 30 35 100000 Notes 100000 ns 16 40 ns 9, 17 40 ns 13 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Fast Page Mode Read-Modify-Write Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Fast page mode readmodify-write cycle time t PRWC 76 85 96 ns WE delay time from CAS precharge t CPW 53 60 68 ns Notes 14 Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min) or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycle and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among tAA, t CAC or tCPA. 18. In delayed write or read-modify-write cycle, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH ≥ tCWL, the DQ pin will remain open circuit (high impedance); if t OEH ≤ tCWL, invalid data will be out at each DQ. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally causes large V CC / V SS line noise, which causes to degrade V IH min / V IL max level. 21. XXX: H or L (H: VIH (min) ≤ V IN ≤ V IH (max), L: VIL (min) ≤ V IN ≤ V IL (max)) 14 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 15 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Timing Waveforms*21 Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH t RAL t ASC t CAL t CAH Column Row t RRH t RCH t RCS WE t DZC t CDD High-Z Din t DZO t OEA t OED OE t OEZ t CAC t OHO t AA t OFF t RAC t CLZ Dout 16 This Material Copyrighted by Its Respective Manufacturer t OH Dout HB56A841BR Series, HB56A441BR Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD t CRP t RSH t CAS tT CAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH WE t DS Din Dout t DH Din High-Z* * t WCS t WCS (min) 17 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t RAH t ASC Row t CAH Column t CWL t RWL t WP t RCS WE t DZC Din t DS High-Z t DH Din t DZO t OEH t OED OE t OEZ t CLZ High-Z Dout Invalid Dout Read-Modify-Write Cycle*18 18 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR Address t RAH t ASC Row t CAH Column t RCS t CWD t CWL t AWD t RWL t RWD t WP WE t DZC t DH t DS High-Z Din Din t OED t DZO t OEH t OEA OE t CAC t OEZ t AA t RAC t OHO Dout Dout High-Z t CLZ 19 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t RPC t CRP t CRP CAS t ASR Address t RAH Row t OFF Dout 20 This Material Copyrighted by Its Respective Manufacturer High-Z HB56A841BR Series, HB56A441BR Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t RPC t CSR t CHR t RPC t CRP tT CAS t CP t WRP t WRH t CP WE Address t OFF High-Z Dout 21 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t WRP t RRH t WRH t WRP t WRH t RCS WE t DZC t CDD High-Z Din t DZO t OED t OEA OE t CAC t AA t RAC t OFF t OH t CLZ Dout 22 Printed from www.freetradezone.com, a service of Partminer, Inc. This Material Copyrighted by Its Respective Manufacturer Dout t OEZ t OHO HB56A841BR Series, HB56A441BR Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CRP t CAS CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH t CAL t ASC t CAH t CAL t ASC t CAH Column 1 Column 2 Column N t RCS t RCS t RCH t RCS t RRH t RCH t RCH WE t DZC Din t DZO t DZC t DZC t CDD t CDD High-Z High-Z t OED t DZO t OED t CDD High-Z t DZO t OED OE t RAC t AA t OH t OEA t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N 23 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Fast Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS Address t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS 24 This Material Copyrighted by Its Respective Manufacturer t WCS (min) HB56A841BR Series, HB56A441BR Series Fast Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CP t CSH t RCD t CRP t CP t PC t CAS t RSH t CAS t CAS CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t DH Din 2 t DZO t OED Din N t DZO t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout Invalid Dout Invalid Dout 25 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Fast Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL Column N t CPW t AWD t CWL t CPW t AWD t CWD t RCS t CWL t AWD t CWD t RCS t RWL t CWD WE t RCS t WP t t DZC DS t WP t t DZC DS t WP t t DZC DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OED t DZO t OEH t OEH t OEH Din N OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t OEZ t CLZ t OHO t OEA t CAC t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 26 This Material Copyrighted by Its Respective Manufacturer Dout 2 Dout N HB56A841BR Series, HB56A441BR Series Physical Outline HB56A841BR Series Unit: mm inch Front side 107.95 4.25 3.175 0.125 R1.57 R0.062 6.35 0.25 9.14 max 0.36 1 72 1.27 typ. 0.05 2.03 0.08 6.35 0.25 2.54 min. 0.10 A 6.35 0.25 44.45 1.75 44.45 1.75 3.17 min 0.125 Component area (Front) 10.16 0.40 25.40 1.00 2-Ø 5.72 min 0.225 101.19 3.98 + 0.10 1.27 – 0.08 + 0.004 0.05 – 0.003 R1.57 R0.062 Back side 1 72 Component area (Back) Deteil A 2.54 min 0.10 0.25 max 0.01 1.04 ± 0.03 0.041 ± 0.001 27 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series HB56A441BR Series Unit: mm inch Front side 107.95 4.25 101.19 3.98 3.175 0.125 R1.57 R0.062 6.35 0.25 5.28 max 0.208 1 72 1.27 typ. 0.05 2.03 0.08 6.35 0.25 2.54 min. 0.10 A 6.35 0.25 44.45 1.75 44.45 1.75 R1.57 R0.062 Back side 1 72 Deteil A 2.54 min 0.10 1.04 ± 0.03 0.041 ± 0.001 28 This Material Copyrighted by Its Respective Manufacturer 0.25 max 0.01 10.16 0.40 25.40 1.00 Component area 3.17 min 0.125 2-Ø + 0.10 1.27 – 0.08 + 0.004 0.05 – 0.003 HB56A841BR Series, HB56A441BR Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 29 This Material Copyrighted by Its Respective Manufacturer HB56A841BR Series, HB56A441BR Series Revision Record Rev. Date Contents of Modification 1.0 Feb. 20, 1997 Initial issue 30 This Material Copyrighted by Its Respective Manufacturer Drawn by Approved by