HB56D473EJ Series 4,194,304-word × 72-bit High Density Dynamic RAM Module ADE-203-725A (Z) Rev. 1.0 Feb. 27, 1997 Description The HB56D473EJ belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56D473EJ is a 4M × 72 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package and 8 pieces of 4-Mbit DRAM (HM514100) sealed in SOJ package, 1 pieces of 16bit BiCMOS line driver (74ABT16244) sealed in TSSOP package and 1 pieces of 20-bit BiCMOS line driver (74ABT16827) sealed in TSSOP package. An outline of the HB56D473EJ is 168-pin socket type package (dual lead out). Therefore, the HB56D473EJ makes high density mounting possible without surface mount technology. The HB56D473EJ provides common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features • 168-pin socket type package (Dual lead out) Outline: 133.35 mm (Length) × 25.40 mm (Height) × 9.00 mm (Thickness) Lead pitch: 1.27 mm • Single 5 V (±5%) supply • High speed Access time: tRAC = 60/70 ns (max) tCAC = 20/25 ns (max) • Low power dissipation Active mode: 12.5/11.3 W (max) Standby mode (TTL): 588 mW (max) (CMOS): 462 mW (max) • Buffered input except RAS and DQ • 4 byte interleave enabled, dual address input (A0/B0) • JEDEC standard outline buffered 8-byte DIMM • Fast page mode capability • 2,048 refresh cycles: 32 ms This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series • 2 variations of refresh RAS-only refresh CAS-before-RAS refresh • TTL compatible Ordering Information Type No. Access time Package Contact pad HB56D473EJ-6 HB56D473EJ-7 60 ns 70 ns 168-pin dual lead out socket type Gold Pin Arrangement Front side Back side 1 pin 10 pin 11 pin 85 pin 94 pin 95 pin 2 This Material Copyrighted by Its Respective Manufacturer 40 pin 41 pin 124 pin 125 pin 84 pin 168 pin HB56D473EJ Series Pin Arrangement Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 OE2 86 DQ36 128 NC 3 DQ1 45 RE2 87 DQ37 129 NC 4 DQ2 46 CE4 88 DQ38 130 CE5 5 DQ3 47 CE6 89 DQ39 131 CE7 6 VCC 48 WE2 90 VCC 132 PDE 7 DQ4 49 VCC 91 DQ40 133 VCC 8 DQ5 50 NC 92 DQ41 134 NC 9 DQ6 51 NC 93 DQ42 135 NC 10 DQ7 52 DQ18 94 DQ43 136 DQ54 11 DQ8 53 DQ19 95 DQ44 137 DQ55 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ20 97 DQ45 139 DQ56 14 DQ10 56 DQ21 98 DQ46 140 DQ57 15 DQ11 57 DQ22 99 DQ47 141 DQ58 16 DQ12 58 DQ23 100 DQ48 142 DQ59 17 DQ13 59 VCC 101 DQ49 143 VCC 18 VCC 60 DQ24 102 VCC 144 DQ60 19 DQ14 61 NC 103 DQ50 145 NC 20 DQ15 62 NC 104 DQ51 146 NC 21 DQ16 63 NC 105 DQ52 147 NC 22 DQ17 64 NC 106 DQ53 148 NC 23 VSS 65 DQ25 107 VSS 149 DQ61 24 NC 66 DQ26 108 NC 150 DQ62 25 NC 67 DQ27 109 NC 151 DQ63 26 VCC 68 VSS 110 VCC 152 VSS 27 WE0 69 DQ28 111 NC 153 DQ64 28 CE0 70 DQ29 112 CE1 154 DQ65 29 CE2 71 DQ30 113 CE3 155 DQ66 30 RE0 72 DQ31 114 NC 156 DQ67 31 OE0 73 VCC 115 NC 157 VCC 32 VSS 74 DQ32 116 VSS 158 DQ68 33 A0 75 DQ33 117 A1 159 DQ69 34 A2 76 DQ34 118 A3 160 DQ70 3 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 35 A4 77 DQ35 119 A5 161 DQ71 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 PD1 121 A9 163 PD2 38 A10 80 PD3 122 NC 164 PD4 39 NC 81 PD5 123 NC 165 PD6 40 VCC 82 PD7 124 VCC 166 PD8 41 NC 83 ID0 (NC) 125 NC 167 ID1 (VSS) 42 NC 84 VCC 126 B0 168 VCC Pin Description Pin name Function A0 to A10, B0 Address input • Row address : A0 to A10, B0 • Column address • Refresh address (D0 to D15) : A0 to10, B0 • Refresh address (M0 to M7) : A0 to A9, B0 : A0 to A10, B0 DQ0 to DQ71 Data-in/data-out RE0, RE2 Row address strobe (RAS) CE0 to CE7 Column address strobe (CAS) WE0, WE2 Read/Write enable OE0, OE2 Output enable VCC Power supply VSS Ground PD1 to PD8 Presence detect ID0, ID1 ID bit PDE Presence detect enable NC No connection 4 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Presence Detect Pin Assignment PDE = Low PDE = High Pin name Pin No. 60 ns 70 ns All PD1 79 1 1 High-Z PD2 163 1 1 High-Z PD3 80 0 0 High-Z PD4 164 1 1 High-Z PD5 81 0 0 High-Z PD6 165 1 0 High-Z PD7 82 1 1 High-Z PD8 166 1 1 High-Z Note: 1: High level (driver output) 0: Low level (driver output) 5 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Block Diagram RE0 RE2 OE0 OE2 WE0 WE2 CE0 CE4 DQ0 DQ1 DQ2 DQ3 I/O CAS I/O I/O I/O RAS WE DQ4 DQ5 DQ6 DQ7 I/O CAS I/O I/O I/O RAS WE DQ8 CAS Din/Dout RAS WE M0 DQ9 DQ10 DQ11 DQ12 I/O CAS I/O I/O I/O RAS WE DQ13 DQ14 DQ15 DQ16 I/O CAS I/O I/O I/O RAS WE DQ17 CAS Din/Dout RAS WE M1 OE D0 OE D1 CE1 DQ36 DQ37 DQ38 DQ39 I/O CAS I/O I/O I/O RAS WE DQ40 DQ41 DQ42 DQ43 I/O CAS I/O I/O I/O RAS WE DQ44 CAS Din/Dout RAS WE M4 DQ45 DQ46 DQ47 DQ48 I/O CAS I/O I/O I/O RAS WE DQ49 DQ50 DQ51 DQ52 I/O CAS I/O I/O I/O RAS WE DQ53 CAS Din/Dout RAS WE M5 DQ54 DQ55 DQ56 DQ57 I/O CAS I/O I/O I/O RAS WE DQ58 DQ59 DQ60 DQ61 I/O CAS I/O I/O I/O RAS WE DQ62 CAS Din/Dout RAS WE M6 DQ63 DQ64 DQ65 DQ66 I/O CAS I/O I/O I/O RAS WE DQ67 DQ68 DQ69 DQ70 I/O CAS I/O I/O I/O RAS WE DQ71 CAS Din/Dout RAS WE M7 OE D8 OE D9 CE5 OE D2 OE D3 CE2 OE D10 OE D11 CE6 DQ18 DQ19 DQ20 DQ21 I/O CAS I/O I/O I/O RAS WE DQ22 DQ23 DQ24 DQ25 I/O CAS I/O I/O I/O RAS WE DQ26 CAS Din/Dout RAS WE M2 DQ27 DQ28 DQ29 DQ30 I/O CAS I/O I/O I/O RAS WE DQ31 DQ32 DQ33 DQ34 I/O CAS I/O I/O I/O RAS WE DQ35 CAS Din/Dout RAS WE M3 OE D4 OE D5 CE3 OE D12 OE D13 CE7 OE D6 D7 OE OE D14 OE D15 PD1 to PD8 A0 D0 to D7, M0 to M3 VCC PD1 B0 D8 to D15, M4 to M7 VCC PD2 A1 to A10 D0 to D15, M0 to M7 VSS PD3 VCC PD4 VSS PD5 VCC VSS VCC VSS VCC PD6 VCC 0.22 µ F VSS D0 to D15, M0 to M7, 74ABT16244, 74ABT16827 26 pcs D0 to D15, M0 to M7, 74ABT16244, 74ABT16827 Note : D0 to D15 : HM5117400 M0 to M7 : HM514100 : 74ABT16244, 74ABT16827 6 This Material Copyrighted by Its Respective Manufacturer PD7 PD8 HB56D473EJ Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –0.5 to +7.0 V Supply voltage relative to VSS VCC –0.5 to +7.0 V Short circuit output current Iout 50 mA Power dissipation Pt 25 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VSS 0 0 0 V VCC 4.75 5.0 5.25 V 1 Input high voltage VIH 2.4 — 5.5 V 1 Input low voltage VIL –0.5 — 0.8 V 1 Note: Note 1. All voltage referred to VSS . 7 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V) 60 ns 70 ns Parameter Symbol Min Max Min Max Unit Test conditions Notes Operating current I CC1 — 2384 — 2144 mA t RC = min 1, 2 Standby current I CC2 — 112 — 112 mA TTL interface RAS, CAS = VIH Dout = High-Z — 88 — 88 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z RAS-only refresh current I CC3 — 2384 — 2144 mA t RC = min 2 Standby current I CC5 — 184 184 RAS = VIH, CAS = VIL Dout = enable 1 CAS-before-RAS refresh current I CC6 — 2384 — 2144 mA t RC = min Fast page mode current I CC7 — 2224 — 1984 mA t PC = min Input leakage current I LI –10 10 –10 10 µA 0 V ≤ Vin ≤ 5.5 V Output leakage current I LO –10 10 –10 10 µA 0 V ≤ Vout ≤ 5.5 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –5 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 4.2 mA — mA 1, 3 Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25°C, VCC = 5 V ± 5%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 20 pF 1 Input capacitance (CAS, WE, OE) CI2 — 20 pF 1 Input capacitance (RAS) CI3 — 99 pF 1 I/O capacitance (DQ0 to DQ7, DQ9 to DQ16, CI/O1 DQ18 to DQ25, DQ27 to DQ34, DQ36 to DQ43, DQ45 to DQ52, DQ54 to DQ61, DQ63 to DQ70) — 20 pF 1, 2 I/O capacitance (DQ8, DQ17, DQ26, DQ35, DQ44, DQ53, DQ62, DQ71) — 25 pF 1, 2 CI/O2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 8 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series AC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 5%, VSS = 0 V)*1, *2 Test Conditions • • • • Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write and Refresh Cycles (Common parameters) 60 ns 70 ns Parameter Symbol Min Max Min Max Unit Notes Random read or write cycle time t RC 110 — 130 — ns RAS precharge time t RP 40 — 50 — ns CAS precharge time t CP 10 — 10 — ns RAS pulse width t RAS 60 10000 70 10000 ns CAS pulse width t CAS 15 10000 20 10000 ns Row address setup time t ASR 5 — 5 — ns Row address hold time t RAH 10 — 10 — ns Column address setup time t ASC 0 — 0 — ns Column address hold time t CAH 15 — 15 — ns RAS to CAS delay time t RCD 20 40 20 45 ns 3 RAS to column address delay time t RAD 15 25 15 30 ns 4 RAS hold time t RSH 20 — 25 — ns CAS hold time t CSH 60 — 70 — ns CAS to RAS precharge time t CRP 15 — 15 — ns OE to Din delay time t OED 20 — 25 — ns 5, 18 OE delay time from Din t DZO 0 — 0 — ns 6, 18 CAS delay time from Din t DZC 0 — 0 — ns 6 Transition time (rise and fall) tT 3 50 3 50 ns 7 Refresh period (2,048 cycles) t REF — 32 — 32 ms 9 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Read Cycle 60 ns 70 ns Parameter Symbol Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 ns 8, 9 Access time from CAS t CAC — 20 — 25 ns 9, 10, 17 Access time from address t AA — 35 — 40 ns 9, 11, 17 Access time from OE t OEA — 20 — 25 ns 9, 18 Read command setup time t RCS 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — ns 12 Read command hold time to RAS t RRH 5 — 5 — ns 12 Column address to RAS lead time t RAL 35 — 40 — ns Column address to CAS lead time t CAL 30 — 35 — ns CAS to output in low-Z t CLZ 2 — 2 — ns Output data hold time t OH 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — ns 18 Output buffer turn-off time t OFF — 20 — 25 ns 13 Output buffer turn-off to OE t OEZ — 20 — 25 ns 13, 18 CAS to Din delay time t CDD 20 — 25 — ns 5 Write Cycle 60 ns 70 ns Parameter Symbol Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — ns 14 Write command hold time t WCH 15 — 15 — ns Write command pulse width t WP 10 — 10 — ns Data-in setup time t DS 0 — 0 — ns 15 Data-in hold time t DH 20 — 20 — ns 15 10 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Refresh Cycle 60 ns 70 ns Parameter Symbol Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 15 — 15 — ns CAS hold time (CBR refresh cycle) t CHR 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 5 — 5 — ns WE hold time (CBR refresh cycle) t WRH 10 — 10 — ns RAS precharge to CAS hold time t RPC 10 — 10 — ns Notes 11 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Fast Page Mode Cycle 60 ns 70 ns Parameter Symbol Min Max Min Max Unit Notes Fast page mode cycle time t PC 40 — 45 — ns Fast page mode RAS pulse width t RASP — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 40 — 45 ns 9, 17 RAS hold time from CAS precharge t CPRH 40 — 45 — ns Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS is not restrictive operating parameters. It is included in the data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. 15. These parameters are referred to CAS leading edge in early write cycle. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC or tCPA. 18. Parity bit of this item must not use (DQ8, DQ17, DQ26, DQ35, DQ44, DQ53, DQ62, DQ71). 19. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 12 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Timing Waveforms*19 Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH Row t RAL t ASC t CAL t CAH Column t RRH t RCH t RCS WE t DZC t CDD High-Z Din t DZO t OEA t OED OE t OEZ t CAC t OHO t AA t OFF t RAC t CLZ Dout t OH Dout 13 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Early Write Cycle t RC t RP t RAS RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t RAH Row t ASC t CAH Column t WP t WCS t WCH WE t DS Din Dout t DH Din High-Z* * t WCS 14 This Material Copyrighted by Its Respective Manufacturer t WCS (min) HB56D473EJ Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t RPC t CRP t CRP CAS t ASR t RAH Row Address t OFF Dout High-Z 15 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RC t RP t RAS t RP RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP WE Address t OFF Dout 16 This Material Copyrighted by Its Respective Manufacturer High-Z t WRH HB56D473EJ Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CRP t CAS CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH t CAL t ASC t CAH t CAL t ASC t CAH Column 1 Column 2 Column N t RCS t RCS t RCH t RCS t RRH t RCH t RCH WE t DZC Din t DZO t DZC t DZC t CDD t CDD High-Z High-Z t OED t DZO t OED t CDD High-Z t DZO t OED OE t RAC t AA t OH t OEA t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N 17 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series Fast Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t RSH t CAS t CP t CRP CAS t ASR t RAH Address Row t ASC t CAH t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t WP t WP t WP t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS 18 This Material Copyrighted by Its Respective Manufacturer t WCS (min) HB56D473EJ Series Physical Outline Unit: mm/inch Front side 133.35 5.250 3.00 0.118 9.00 max 0.354 max 4.00 min 0.157 min 127.35 5.014 3.00 0.118 Component area (Front) 1 84 B C 11.43 8.89 0.350 0.450 A 36.83 1.450 1.27 ± 0.10 0.050 ±0.004 54.61 2.150 Back side 85 1.00 0.039 6.35 0.250 3.175 0.125 2.00 ± 0.10 0.079 ± 0.004 3.175 0.125 3.125 ± 0.125 0.123 ± 0.005 3.125 ± 0.125 0.123 ± 0.005 1.00 ± 0.05 0.039 ± 0.002 Detail C Detail B 1.27 0.050 0.25 max 0.010 max 2.54 min 0.100 min Detail A 25.40 1.000 168 Component area (Back) 17.78 0.700 4.00 0.157 2 – φ 3.00 2 – φ 0.118 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 19 This Material Copyrighted by Its Respective Manufacturer HB56D473EJ Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 20 This Material Copyrighted by Its Respective Manufacturer Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 HB56D473EJ Series Revision Record Rev. Date Contents of Modification 1.0 Initial issue Feb. 27, 1997 Drawn by Approved by 21 This Material Copyrighted by Its Respective Manufacturer