M61530FP 4ch Electronic Volume with 5.1ch Analog Input REJ03F0058-0100Z Rev.1.0 Sep.19.2003 Description The M61530FP is a four-channel volume IC which is optimal for combination with the M61519FP two-channel electronic volume. A multi-channel system is easily configured with the aid of these two chips. Features Function names Features Main volume control 0 to −87 dB in 1-dB steps, −∞ Four independently controlled volumes (SL, SR, C, LFE) Low pass filter (LPF) On-chip operational amplifiers for configuration of post-filters through the addition of external C and R elements AGC Bass boost AGC circuit is included to prevent clipping <SW ch> HPF type, with on/off switch <SL/SR ch> Output gain control Input gain control 0, +6, +9, or +12 dB (four steps) <SW ch> 0, +5, +10 dB (three steps) <FL/FR ch> Microcomputer I/F Two-line serial data control Application Mini-component systems, micro-component systems, etc. Recommended Operating Conditions Power-supply voltage range: Vcc = 8 to 10 V Rated power-supply voltage: Vcc = 9 V Rev.1.0, Sep.19.2003, page 1 of 18 M61530FP System Block Diagram M 61530FP M61519FP LI N L-LPF Input selector RIN R-LPF Input selector Surround or DPL buffer Tone VOL Bass booster LOUT Tone VOL Bass booster ROUT 0,+5,+10dB FLIN FL-LPF FRIN FR-LPF SLIN SL-LPF 0,+5,+10dB +6dB SLchVOL SL_EXTIN SRIN SLOUT SR-LPF +6dB SRchVOL SR_EXTIN CIN Bass booster Bass booster SROUT C-LPF +6dB LFEIN SWIN Rev.1.0, Sep.19.2003, page 2 of 18 CchVOL COUT LFEchVOL AGC SW-LPF 0,+6, +9,+12dB SWOUT M61530FP Block diagram with pin connections FR_LPFOUT 1 FR_LPFIN 2 SL_EXTIN 3 FL input gain control 0,+5,+10dB FLch LPF amp FRch LPF amp 4 SL_LPFOUT 5 SL_LPFIN 41 FL_LPFIN FR input gain control 0,+5,+10dB 40 R_LPFIN SL ch volume SLVOLXY input SW SL_VOLIN 42 FL_LPFOUT Rch LPF amp 0 to -87dB,-∞ Lch LPF amp SLch LPF amp 39 R_LPFOUT 38 L_LPFOUT 37 L_LPFIN 6 +6dB SR_EXTIN VREF amp 7 SR_VOLIN 8 SR_LPFOUT 9 35 REFOUT 0 to -87dB,-∞ 34 FL_OUT SRch LPF amp FL output SW 33 FR_IN SR_LPFIN 10 +6dB C_VOLIN 11 C_LPFOUT 12 36 REFIN SRch volume SRVOL input SW Cch volume OFF FR output SW 0 to -87dB ,-∞ 31 SL_BB1 Cch LPF amp Bass booster ON/OFF C_LPFIN 13 +6dB LFE_VOLIN 14 32 FR_OUT ON 30 SL_BB2 LFEch volume 29 SL_OUT 0 to -87dB,-∞ Bass booster 28 SR_BB1 SW_IN 15 Bass booster ON/OFF 17 Microcomputer I/F CLOCK 18 GND 19 TEST 20 LFEMIX SW DATA SW MIX SW VCC 16 26 SR_OUT Bass booster 25 C_OUT 24 SW_OUT AGC SW output-gain control 0,+6,+9,+12dB 23 SW_LPFIN 22 SW_LPFOUT AGC 21 SWch LPF amp Rev.1.0, Sep.19.2003, page 3 of 18 27 SR_BB2 M61530FP Pin description Pin No. Pin Name Description 1 FR_LPFOUT 2 FR_LPFIN Configure a low-pass filter by adding external C and R elements to the input of the FR channel 3 4 SL_EXTIN SL_VOLIN SL channel external input pin SL channel volume input pin 5 6 SL_LPFOUT SL_LPFIN Configure a low-pass filter by adding external C and R elements to the input of the SL channel 7 8 SR_EXTIN SR_VOLIN SR channel external input pin SR channel volume input pin 9 10 SR_LPFOUT SR_LPFIN Configure a low-pass filter by adding external C and R elements to the input of SR channel 11 12 C_VOLIN C_LPFOUT C channel volume input pin Configure a low-pass filter by adding external C and R elements to the input of the C channel 13 14 C_LPFIN LFE_VOLIN LFE channel volume input pin 15 16 SW_IN VCC SW channel input pin Power-supply pin for internal analog and digital circuitry (VCC = 9 V) 17 18 DATA CLOCK DATA input pin for serial data transfer CLOCK input pin for serial data transfer 19 20 GND TEST GND pin for internal analog and digital circuitry Pin for setting the test mode (normally fixed low) 21 22 AGC SW_LPFOUT 23 24 SW_LPFIN SW_OUT C connection pin for setting attack/recovery time for AGC Configure a low-pass filter by adding external C and R elements to the input of the SW channel 25 26 C_OUT SR_OUT C channel output pin SR channel output pin 27 28 SR_BB2 SR_BB1 Pin for connecting external components that set bass-boost frequency characteristics for the SR channel 29 30 SL_OUT SL_BB2 31 32 SL_BB1 FR_OUT SL channel output pin Pin for connecting external components that set bass-boost frequency characteristics for the SL channel 33 34 FR_IN FL_OUT Pin for interfacing with the M61519FP surround circuit FL channel output pin 35 36 REFOUT REFIN Internal reference output pin Internal reference input pin 37 38 L_LPFI N L_LPFOUT Configure a low-pass filter by adding external C and R elements to the input of the L channel 39 40 R_LPFOUT R_LPFIN Configure a low-pass filter by adding external C and R elements to the input of the R channel 41 FL_LPFIN 42 FL_LPFOUT Configure a low-pass filter by adding external C and R elements to the input the of FL channel SW channel output pin FR channel output pin Rev.1.0, Sep.19.2003, page 4 of 18 M61530FP Absolute Maximum Ratings Parameter Symbol Ratings Unit Conditions Power-supply voltage VCC 10.5 V Internal power dissipation Pd 850 mW Ta≤25°C Thermal reduction rate Ambient operating temperature Kθ Topr 8.6 -20 to +75 mW/°C °C Ta>25°C Storage temperature Tstg -40 to +125 °C Thermal derating curve 1.0 Internal power dissipation pd [W] 0.85W 0.75 0.5 0.42 0.25 0 25 50 75 100 125 150 Ambient temperature Ta [°C] Recommended Operating Condition (Unless otherwise noted, Ta = 25°C) Limits Item Symbol Min. Typ. Max. Unit Power-supply voltage VCC 8 9 10 V Logical high level input voltage Logical low level input voltage VIH VIL 2.2 0 5.5 0.6 V V Rev.1.0, Sep.19.2003, page 5 of 18 Condition VCC=9V VCC=9V M61530FP Relation between DATA and CLOCK Latch condition CLOCK D0 D1 D2 D3 D13 D14 D15 DATA The data signal is read on the rising edges of the CLOCK signal The DATA line is driven high to latch D0 to D15 at this time 1. Data transmission The DATA signal is read on the rising edges of the CLOCK signal. The DATA line must always be low on the falling edge of the CLOCK signal during transmission of the DATA signal. 2. Data Latch Data for this IC is in 16-bits (D0 to D15) words. Latch the transmitted data by driving the DATA line high on the falling edge of the CLOCK signal after the transmission of D15. CLOCK and DATA timing (D0 to D15) (D15) L ATCH signal t cr DATA tSLD tHLD tSHD 75% CLOCK 25% tr tf tWHC Rev.1.0, Sep.19.2003, page 6 of 18 tWLC tHHD tSLD tHLD M61530FP Digital module timing Limits Item Symbol Min. Typ. Max. Unit Clock: Cycle time tcr 4 µS Clock: Pulse width (high) Clock: Pulse width (low) tWHC tWLC 1.6 1.6 Clock: Rising time Clock: Falling time tr tf 0.4 0.4 Data: Setup time (high), clock rising Data: Setup time (low), clock falling tSHD tSLD 0.8 0.8 Data: Hold time (high) Data: Hold time (low) tHHD tHLD 0.8 0.8 Rev.1.0, Sep.19.2003, page 7 of 18 M61530FP Data input format (Set all data shown below to the initial values every time power is turned on.) (1) D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14 (2) (8) (8) (1) SLch trim potentiometer SRch trim potentiometer FL/FR input gain control (3) (4) D15 (5) 0 0 D10b D11b D12b D13b D14 D15 FL/FR Input LFEMIX SWMIX output SW for SW SW SW SL/SR volume (2) D0b D1b D2b D3b D4b D5b D6b D7b (8) (8) Cch trim potentiometer LFEch trim volume D8b D9b (7) (6) Bass SW output gain control boost 0 0 0 0 1 D10c D11c D12c D13c D14 D15 (3) D0c D1c D2c D3c D4c D5c D6c D7c D8c (9) (9) SLch master volume SRch master volume D9c 0 0 0 0 1 0 D10d D11d D12d D13d D14 D15 (4) D0d D1d D2d D3d D4d D5d D6d D7d D8d (9) (9) Cch master volume LFEch master volume D9d 0 0 0 0 1 1 Code settings (1) FL/FR input gain control Setting D8a D9a 0dB +5dB 0 0 0 1 +10dB 1 0 : Initial setting (6) Bass boost (3) Input switch for SL/SR volume (5) SW MIX SW Setting D11a SL/SRch input External input 0 1 Setting ON OFF D13a Setting 0 1 OFF ON (2) FL/FR output SW (4) LFE MIX SW (7) SW output gain control Setting Setting Setting ON OFF D10a 0 1 ON OFF D12a 0 1 Note: Do not use data codes other than those specified above. Rev.1.0, Sep.19.2003, page 8 of 18 D9b D10b 0dB +6dB 0 0 0 1 +9dB +12dB 1 1 0 1 D8b 0 1 M61530FP (8) SL/SR/C/LFEch trim volume (9) SL/SR/C/LFEch master volume SLch D0a D1a D2a D3a SRch Cch D4a D0b D5a D1b D6a D2b D7a D3b SLch D0c D1c D2c D3c D4c SRch Cch D5c D0d D6c D1d D7c D2d D8c D3d D9c D4d D4b 0 D5b 0 D6b 0 D7b 0 D5d 0 D6d 0 D7d 0 D8d 0 D9d 0 -1dB -2dB 0 0 0 0 0 1 1 0 -2dB -4dB 0 0 0 0 0 0 0 1 1 0 -3dB -4dB 0 0 0 1 1 0 1 0 -6dB -8dB 0 0 0 0 0 1 1 0 1 0 -5dB -6dB 0 0 1 1 0 1 1 0 -10dB -12dB 0 0 0 0 1 1 0 1 1 0 -7dB -8dB 0 1 1 0 1 0 1 0 -14dB -16dB 0 0 0 1 1 0 1 0 1 0 -9dB -10dB 1 1 0 0 0 1 1 0 -18dB -20dB 0 0 1 1 0 0 0 1 1 0 -11dB -12dB 1 1 0 1 1 0 1 0 -22dB -24dB 0 0 1 1 0 1 1 0 1 0 -13dB -14dB 1 1 1 1 0 1 1 0 -26dB -28dB 0 0 1 1 1 1 0 1 1 0 -15dB 1 1 1 1 -30dB -32dB 0 1 1 0 1 0 1 0 1 0 -34dB -36dB 1 1 0 0 0 0 0 1 1 0 -38dB -40dB 1 1 0 0 0 1 1 0 1 0 -42dB -44dB 1 1 0 0 1 1 0 1 1 0 -48dB -52dB 1 1 0 1 1 0 1 0 1 0 -56dB -60dB 1 1 1 1 0 0 0 1 1 0 -64dB -68dB 1 1 1 1 0 1 1 0 1 0 -72dB -76dB 1 1 1 1 1 1 0 1 1 0 -∞dB 1 1 1 1 1 Attenu ation LFEch 0dB Attenu ation LFEch 0dB Note: When the sum of the trim potentiometer and master volume settings is –87 dB or less, the overall level is –87 dB (e.g. when the trim potentiometer is –15 dB and master volume is -76 dB, the total level becomes -87 dB). Note: Do not use data codes other than those specified above. Rev.1.0, Sep.19.2003, page 9 of 18 M61530FP Electrical characteristics Unless otherwise noted, Ta = 25°C, Vcc = 9 V, f = 1 kHz, input gain control = 0 dB, bass boost = off, trim/master volume = 0 dB, FL/FR output SW = on, SL/SR VOL input SW = SL/SR input, LFE MIXS SW = on, SW MIX= off, output gain control = 0 dB Limits Item Symbol Min. Typ. Max. Unit Condition Power supply Circuit current IACC 14 25 mA When no signal is detected, current flows to pin 16 I/O Max. input voltage VIM1 1.6 2.0 Vrms Pins 2, 37, 40, and 41: Input, pins 1, 38, 39, and 42: Output, RL = 10 kΩ, THD = 1% VIM2 0.8 1.0 Vrms Pins 6, 10, and 13: Input, pins 5, 9, and 12: Output, RL = 10 kΩ, THD = 1% VIM3 1.6 2.0 Vrms Pin 14: Input, pin 22: Output, RL = 10 kΩ, THD = 5%, f = 100 kHz Absolute max. input voltage AVIM 2.0 Note Vrms Pins 3, 7, 14, and 15: Input Max. output voltage VOM1 1.8 2.4 Vrms Pins 6 and 10: Input, pins 29 and 26: Output, RL = 10 kΩ, THD = 5%, bass boost = on, f = 100 Hz VOM2 1.6 2.0 Vrms Pin 13: Input, pin 25: Output, RL = 10 kΩ, THD = 5% VOM3 1.4 1.8 Vrms Gain between pins 14 and 22, Vi = 0.5 Vrms, FLAT, f = 100 Hz GV1 +2.3 +4.3 +6.3 dB Gain from pins 6 to 29, pin 10 to 26, and pins 13 to 25, Vi = 0.5 Vrms, FLAT GV2 -2 0 +2 dB Gain from pins 2 to 32 and 41 to 34, Vi = 0.5 Vrms, FLAT GV3 -2 0 +2 dB Gain from pin 14 to 22, Vi = 0.5 Vrms, FLAT, f = 100 Hz Vno1 6.0 12.0 µVrms 2.5 8.0 µVrms DIN-Audio, when no signal is present, Rg = 0 for pins 6 and 10, pins 29 and 26 are outputs 6.0 10.0 µVrms 2.0 4.0 µVrms 6.5 16.0 µVrms 6.5 16.0 µVrms THD1 0.003 0.2 % Pins 6 and 10: input, pins 29 and 26: output, bandwidth: 400 Hz to 30 kHz, Vo = 0.5 Vrms, RL = 10 kΩ THD2 0.003 0.1 % Pin 13: input, pin 25: output, bandwith: 400 Hz to 30 kHz, Vo = 0.5 Vrms, RL = 10 kΩ THD3 0.008 0.2 % Pin 14: input, pin 22: output, 30-kHz low-pass filter, Vo = 0.5 Vrms, RL = 10 kΩ, output gain control = 0 dB, when AGC is not operating, f = 100 Hz THD4 2 % Pin 14: input, pin 22: output, 30-kHz low-pass filter, RL = 10 kΩ, Vi = 700 mVrms, f = 100 Hz, when AGC is operating, output gain control = + 12 dB ATT -100 -87 dB Vo = 1 Vrms, pins 22, 25, 26, and 29 are outputs, JIS-A, volume = -∞ Bypass gain Output noise voltage Vno2 Vno3 Total harmonic distortion rate Volume max. attenuation Rev.1.0, Sep.19.2003, page 10 of 18 DIN-Audio, when no signal is present, Rg = 0 for pin 13, pin 25 is an output DIN-Audio, when no signal is detected, Rg = 0 for pin 14, pin 22 is an output, SW ch LPF: fc=300 Hz SL/SR ch volume = -∞ dB C ch volume = 0 dB C ch volume = -∞ dB LFE ch volume = 0 dB LFE ch volume = -∞ dB M61530FP Limits Item I/O AGC Symbol Min. Typ. Max. Unit Condition GVM1 +8 +10 +12 dB Gain from pin 2 to 32 and 41 to 34, Vi = 0.1 Vrms, FLAT, input gain control = + 10 dB GVM2 +10 +12 +14 dB Gain between pins 14 and 22, f = 100 Hz Vi = 0.1 Vrms, FLAT, output gain control = + 12 dB Crosstalk between channels CT -90 -55 dB Gain from pins 6 to 29, pins 10 to 26, pins 13 to 25, and pins 14 to 22, Vi = 0.5 Vrms, JIS-A, RL = 47 kΩ, Rg = 0 Ω, input on a channel other than the measurement target Attack time TAGCAT 40 ms Pin 14: input, pin 22: output, RL = 10 kΩ, output gain control = +12 dB Recovery time TAGCRE 850 ms Pin 14: input, pin 22: output, RL = 10 kΩ, output gain control = +12 dB Max. gain Note: The voltage on pins 3, 7, 14, and 15 must not exceed the the absolute maximum input-voltage range (2 Vrms). Rev.1.0, Sep.19.2003, page 11 of 18 Rev.1.0, Sep.19.2003, page 12 of 18 max:2Vrms LFEch Cch S-Rch SW-IN 15 14 13 11 12 10 7 8 9 6 3 4 5 2 1 41 42 40 39 37 38 TUNER +6dB +6dB +6dB 32 33 34 SRVOL input SW SLVOL input SW 0, +5,+10dB FR output SW 0, +5,+10dB FL output SW MIC IN MIC SW LFEchVOL 0 to -87dB,-∞ CchVOL 0 to -87dB,-∞ SRchVOL 0 to -87dB,-∞ SLchVOL 0 to -87dB,-∞ RECA SW SWMIX SW 21 AGC TEST 20 CLOCK 18 SWch OUT Cch OUT SRch OUT SLch OUT M61519FP Max. output voltage 2Vrms Master volume Master volume 36 REF 35 19 16 SW ch output noise (values for reference) (DIN-Audio) Output gain 0dB : 8 µ Vrms +6dB: 15 µ Vrms +12dB: 30 µ Vrms Tone control (bass/mid/treble) Tone control (bass/mid/treble) LOGIC 17 DATA 24 23 22 25 26 27 28 29 30 31 LPF fc =300Hz Bass booster Bass booster Spectrum analyzer Pre-tone control attenuator 0, +6,+9,+12dB Bypass Bypass Pre-tone-control attenuator M61519FP M 61530FP RECA1/INex1 LFEMIX SW RECA2/INex2 4-ch input selector + mute RECB1 RECB2 4-ch input selector + mute MIC IN Surround /DPL Buff S-Lch FRch Lch MD TAPE Vocal cut FLch Rch DVD CD Bass booster Bass booster Rch Lch M61530FP System block diagram M61530FP + M61519FP application example Note: In the above application, the voltage input to pin 14 (LFE ch) must not exceed the absolute maximum input voltage (2 Vrms). M61530FP Functional description (1) Equivalent circuit of the bass-boost circuit Input Output Q=4 (G=10dB) G0 0dB F0 R1 VI N C1 C2 VO +K R2 K=1 Note: Resistor R2 is within the IC. (R2 214kΩ ± 30%) fo = 1 2 π R1R2C1C2 Hz Q= R1R2C1C2 R1(C1+C2)+(1-K)R2C2 Amplitude characteristics of the second-order high-pass filter (reference) Q G0 1 0 to1dB 2 4 6dB 10dB 5 10 13dB 20dB Rev.1.0, Sep.19.2003, page 13 of 18 M61530FP Bass-boost characteristic curve R1 =680Ω, R2 = 214kΩ , C1 = C2 = 0.22 µ F (f0 60Hz ,Q 8.9) (2) AGC circuit LFEch MAX 2Vrms SW ch output gain control +26 dB (total: 0 dB) to +38 dB (total: +12 dB) LFEch volume SWch MAX 2Vrms SWOUT -26dB AGCout Waveform detector circuit AGCin Precaution on inputting the same phase to LFE ch and SW ch When C for setting the times = 1.0 µF, attack time = 40 ms, and recovery time = 850 ms The input voltage range for AGC operation is from the input voltage at which AGC operation starts (taking the output gain into consideration, LFEin + SWin when the output voltage is 1.8 Vrms) to the same voltage x 10 dB. 1.0µ AGC circuit Rev.1.0, Sep.19.2003, page 14 of 18 C for setting the attack and recovery times M61530FP Diagrams AGC input/output characteristics Output gain :+6dB Output gain :0dB +5.1dBV +10 (1.8Vrms: TYP) AGCout:SWout(dBV) AGCout:SWout(dBV) +5.1dBV +10 (1.8Vrms: TYP) 0 -10 -20 -20 +5.1dBV (1.8Vrms) -10 0 10dB 0 + 9.1dBV (2.85Vrms) -10 -0.9dBV (0.90Vrms) -20 -20 +10 AGCout:SWout(dBV) AGCout:SWout(dBV) +10 Output gain :+12dB +5.1dBV +10 (1.8Vrms:TYP) 10dB 0 +6.1dBV (2.02Vrms) -10 -3.9dBV (0.64Vrms) -20 -20 0 AGCin: LFEin+SWin(dBV) AGCin: LFEin+SWin(dBV) Output gain :+9dB -10 -10 0 +10 AGCin: LFEin+SWin(dBV) +5.1dBV +10 (1.8Vrms: TYP) 10dB 0 +3.1dBV (1.43Vrms) -10 -6.9dBV (0.45Vrms) -20 -20 -10 0 +10 AGCin: LFEin+SWin(dBV) System reset (a) Power-on operation Immediately after power is supplied, this IC generates a reset signal. • • • • Generation of the reset signal is governed by the time constant for the rise in power voltage when power is supplied. When VCC rises above roughly 5.5 V (1), the reset signal is transmitted (logic circuit is turned on). (1) The reset operation takes place in the period from reset signal transmission to (2) reset signal cancellation. Trst = “Timing A + about 20 µs” is the time up to reset cancellation (Timing A is time until VCC reaches 5.5 V) Rev.1.0, Sep.19.2003, page 15 of 18 M61530FP Reset timing diagram (1) Reset signal transmission V Reset operation (2) Reset signal cancellation VCC VDD (internal power supply) 5.5V VSS (internal power supply) t Trst About 20 µs A Reset cancellation (normal operation) As is shown in the above figure, the reset is cancelled after time Trst after the power-supply voltage has started to rise. The chip is then able to receive serial data. (b) Power-off operation (for reference) • The internal VDD and VSS voltages fall as VCC falls (the opposite trend to that in the above figure). • When the logic circuits are turned off, all setting data becomes invalid. Rev.1.0, Sep.19.2003, page 16 of 18 M61530FP Application Examle FL_LPFOUT 220p 10k 470 SL_VOLIN SLch IN 0 to -87dB,-∞ SL_LPFOUT 5 1000p 4.7k 47k 10µ 7 8 10µ SRch IN 1000p 2.2k 10k SRch LPF amp 12 10k 10µ 10µ Bass booster ON/OFF 47k 0 to -87dB,-∞ Bass booster FR_IN 100µ VREF out 10µ 10k 1M 0.047µ 1M 32 SL_BB1 10µ 10k 1M FLch OUT FRch OUT SL_BB2 0.22µ 0.22µ 680 10µ SLch OUT SR_BB1 0.22µ 28 15 Bass booster ON/OFF SR_BB2 16 27 DATA SR_OUT 17 CLOCK Lch IN 29 VCC Microcomputer Lch OUT 100µ SL_OUT LFEch volume SW_IN SWch IN 47k 10µ 36 30 +6dB LFE_VOLI N Rch OUT 31 Cch LPF amp 14 from M61519FP Max:2Vrms ON 13 1000p LFEch IN Max:2Vrms OFF FR output SW C_LPFIN 4.7k 2.2k 1000p FR_OUT Cch volume 0 to -87dB,-∞ C_LPFOUT 1000p 2.2k FL output SW +6dB 11 Cch IN 2.2k 33 C_VOLIN 10µ 2200p L_LPFIN 34 10 1000p 10µ 10µ 38 FL_OUT SR_LPFIN 4.7k Rch IN 47k 35 0 to -87dB,-∞ SR_LPFOUT 9 39 REFOUT SRch volume SRVOL input SW 10µ 2200p REFIN VREF amp SR_VOLIN 2.2k 1000p 37 +6dB Microcomputer I/F 18 LFEMIX SW SR_EXTIN SR_EXTIN from M61519FP Max:2Vrms 10µ Lch LPF amp SLch LPF amp 6 1000p 47k L_LPFOUT SL_LPFIN 2.2k 10k 10µ Rch LPF amp 470 2.2k R_LPFOUT SLch volume SLVOL input SW 4 10µ 10k 220p 40 47k 10µ 10µ R_LPFIN 3 SL_EXTIN FLch IN 220p 41 FR input gain control 0,+5,+10dB SL_EXTIN from M61519FP Max:2Vrms 42 FL_LPFIN 2 220p 47k 10µ FRch LPF amp FR_LPFIN SWMIX SW 10µ FL input gain control 0,+5,+10dB FLch LPF amp to M61519FP FRch IN 1 to M61519FP FR_LPFOUT TEST 20 680 10µ SRch OUT 10µ Cch OUT 26 Bass booster C_OUT 25 SW_OUT GND 19 0.22µ 24 AGC SW_LPFIN SW output gain control 0,+6,+9,+12dB 23 SW_LPFOUT AGC 2.2k 1k 0.22µ 0.1µ 10µ 22 21 SW ch OUT 1µ SWch LPF amp Note: The voltage input to pins 3, 7, 14, and 15 must not exceed the absolute maximum input voltage (2 Vrms). Rev.1.0, Sep.19.2003, page 17 of 18 HE G 1 42 Z1 e z y Detail G D JEDEC Code — MMP b 21 22 Weight(g) — Detail F A2 Lead Material Cu Alloy+42 Alloy L1 EIAJ Package Code SSOP42-P-450-0.80 E Rev.1.0, Sep.19.2003, page 18 of 18 A c A1 F L A A1 A2 b c D E e HE L L1 z Z1 y Symbol e1 b2 e1 I2 b2 Dimension in Millimeters Min Nom Max 2.4 — — — 0.05 — — 2.0 — 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 — 0.8 — 12.23 11.93 11.63 0.7 0.5 0.3 — 1.765 — — — 0.75 — — 0.9 0.15 — — — 0° 10 ° — 0.5 — — 11.43 — — 1.27 — Recommended Mount Pad e Plastic 42pin 450mil SSOP I2 42P2R-E M61530FP Package Dimensions Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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