HOLTEK HT6230

HT6230
Infrared Remote Encoder
Features
·
·
·
·
·
Operating voltage: 2.4V~5.2V
32 system codes, each system with
64 command codes
Programmable transmission codes
Biphase transmission method
Generated modulation output data
·
·
·
·
(1/2 system frequency and 1/4 duty cycle)
Single pin oscillator
429kHz resonator system clock
Test pins available
28-pin SOP package
·
·
·
Car door controllers
Security systems
Other remote control systems
Applications
·
·
Televisions and video cassette recorder
controllers
Garage door controllers
General Description
keys and to each key is assigned one programmable code. The code is programmable by mask
option. Legal and illegal key operation can be
distinguished.
The HT6230 is designed as infrared remote encoder, usually applied to TV systems. A total of
2048 different commands can be generated and
arranged into 32 systems where each system
contains 64 different commands. There are 96
Block Diagram
O S C
T T 1
T T 2
M S
Z IN 3
Z IN 0
R C
O S C
3 ´ 2 1
2
M o d e
S e le c tio n
O u tp u t
S ta g e
C O D E
M o d u la tio n
O u tp u t
S ta g e
C o n tro l
U n it
M C O D E
Z -k e y
P A L
D R S 7
X IN 7
X -k e y
E n c o d e r
X IN 0
P a r a lle l
T o S e r ia l
C o n v e rte r
D iv id e r
R e s e t
A c tio n
G e n e ra to r
T e s t
M o d e
Z -k e y
E n c o d e r
1 3
X -k e y
P A L
C o m m a n d
A n d
S y s te m
C o d e L a tc h
Z -D R S
P A L
K e y S c a n
D r iv e r
D e c o d e r
D R S 0
X -D R S
P A L
V S S
1
V D D
April 19, 2000
HT6230
Pin Assignment
Pad Assignment
4
2 5
X IN 4
Z IN 2
5
2 4
X IN 3
Z IN 3
6
2 3
X IN 2
M C O D E
7
2 2
X IN 1
C O D E
8
2 1
X IN 0
D R S 7
9
2 0
T T 1
D R S 6
1 0
1 9
T T 2
D R S 5
1 1
1 8
O S C
D R S 4
1 2
1 7
D R S 0
D R S 3
1 3
1 6
D R S 1
V S S
1 4
1 5
D R S 2
Z IN 2
2
Z IN 3
3
M C O D E
4
H T 6 2 3 0
2 8 S O P
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
5
D R S 7
6
D R S 6
7
(0 ,0 )
C O D E
1 1
1 2
1 3
1 4
D R S 2
D R S 1
D R S 0
2 0
X IN 2
1 9
X IN 1
1 8
X IN 0
1 7
T T 1
1 6
T T 2
1 5
O S C
D R S 4
1 0
V S S
9
D R S 3
8
D R S 5
X IN 3
Z IN 1
1
X IN 4
X IN 5
X IN 5
2 6
X IN 6
3
V D D
X IN 6
Z IN 0
M S
V D D
2 7
X IN 7
2 8
2
Z IN 1
1
M S
Z IN 0
X IN 7
2
Chip size: 1605 ´ 1910 (mm)
* The IC substrate should be connected to VDD in the
layout artwork.
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-570.19
-662.85
-662.85
-662.85
-662.85
-662.85
-662.85
-644.16
-429.58
-288.15
-98.77
107.68
249.11
463.69
817.68
442.16
300.74
120.29
-147.93
-395.02
-536.45
-817.68
-817.68
-817.68
-817.68
-817.68
-817.68
-817.68
15
16
17
18
19
20
21
22
23
24
25
26
27
28
605.12
653.07
653.07
653.07
653.07
653.07
561.23
419.80
278.37
136.94
-4.48
-145.91
-287.34
-428.76
-817.68
-75.59
65.84
207.26
437.29
578.71
817.68
817.68
817.68
817.68
817.68
817.68
817.68
817.68
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HT6230
Pad Description
Pad No.
Pad Name
I/O
Internal
Connection
Description
1~3
28
ZIN1~ZIN3
ZIN0
I
4
MCODE
O
Tri-state
CMOS
Generate modulation output data code with
1/12 system frequency and 1/4 duty cycle
5
CODE
O
Tri-state
CMOS
Generates output data code
6~10
DRS7~DRS3
O
Open Drain
NMOS
11
VSS
¾
¾
12~14
DRS2~DRS0
O
Open Drain
NMOS
15
OSC
I
CMOS
Oscillator input
CMOS
Switch to four operating modes:
0 0 normal mode
0 1 test mode 1
1 0 test mode 2
1 1 Reset
16~17
TT2~TT1
I
18~24
XIN0~XIN6
I
25
VDD
¾
26
XIN7
I
27
MS
I
CMOS with
Detect inputs from Z-key matrix
PMOS Pull-high
Drive for key scanning
Negative power supply, ground
Drive for key scanning
CMOS with
Detect inputs from X-key matrix
PMOS Pull-high
Positive power supply
¾
CMOS with
Detect input from X-key matrix
PMOS Pull-high
Select system mode (Two modes provided:
One-key system mode and Two-key system
mode)
CMOS
Approximate internal connection circuits
· Input terminal
P in : M S , T T 1 , T T 2 , O S C
V
D D
P in : X IN 0 ~ X IN 7 , Z IN 0 ~ Z IN 3
( w ith p u ll- h ig h r e s is to r )
V
D D
V
3
D D
April 19, 2000
HT6230
· Output terminal
P in : D R S 0 ~ D R S 7
P in : C O D E , M C O D E
V
D D
E N B
D A T A IN
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-25°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max. Unit
2.4
¾
5.2
V
VDD
Supply Voltage
¾
VOL1
DRS0~DRS7 Output
Voltage Low
3V
IOL1=0.3mA
¾
¾
0.3
V
VOL2
CODE, MCODE Output
Voltage Low
3V
IOL2=0.6mA
¾
¾
0.3
V
VOH
CODE, MCODE Output
Voltage High
3V
IOH=-0.4mA
VDD-0.3
¾
¾
V
RPH
XIN0~XIN7 and
ZIN0~ZIN3 Pull-high
3V
TT1=TT2=MS=Low
VI=0V
¾
27
¾
kW
¾
¾
429
¾
kHz
¾
30
50
100
kHz
fOSC
Oscillator Frequency
Operational
3V
Free-running
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April 19, 2000
HT6230
Functional Description
cent state both CODE and MCODE are high
impedance.
Key operation
When MS is low, the legal key operation is that
only one ZIN or XIN can be connected to one
DRS driver and if more than one XIN, ZIN or
both are pressed at the same time then the key
operation is recognized as illegal; hence, the oscillator will not start. When MS is high, the legal key operation is that exactly one ZIN and
one XIN are connected to two DRS drivers and
other cases of key operation are all considered
as illegal.
Key scan drivers
The key scan drivers DRS0 to DRS7 are open
drain NMOS and the outputs of these are all
low in quiescent state. When a legal key operation is detected, the debounce cycle starts and
at the end of the debounce cycle, the DRS outputs are high impedance. Furthermore, the
scanning cycle starts and DRS outputs take
turns to switch to low state.
However, when one XIN or ZIN is connected to
more than one DRS, the last key scan driver is
to generate output data code.
Programmable output data code
The output data code corresponding to each key
is programmable by hardware mask option.
The PAL circuit is necessary for this purpose.
Format of transmission code
The output pin CODE transmits the data code
as a code format, as shown at the bottom figure.
Operation mode
The method of transmitting one code bit is called
biphase transmission and is represented by the
following fig:
lo g ic 0
· One-key system mode
The device enters this mode by switching the
MS input pin to low state. The pull-high resistors are connected to all XIN and ZIN inputs
so that all sense inputs are at high state, until
pulled to low state by key operation. In this
mode the legal key operation is that only one
ZIN or XIN can be connected to one DRS.
When a sense input detects a low level, an enable signal is generated to latch the system or
command latches. If the sense input belongs
to ZIN, the corresponding system code is generated and the command code is defined as all
lo g ic 1
8
Where one code bit time is 3´2 ´TOSC. The output signal of the MCODE pin is the signal of the
generated output code modulated by 1/12 of the
system frequency with 1/4 duty cycle. In quieso n e c o d e
1
s ta rt
D e b o u n c e c y c le
( 1 6 b it- tim e )
S c a n
c y c le
1
S ta rt
b its
L S B
M S B
5 s y s te m
C o n tro l
b it
b its
C o d e 1
s ta rt
1 6 b it- tim e
M S B
L S B
6 c o m m a n d b its
C o d e 2
4 8 b it- tim e
1 6 b it- tim e
R e p e titio n tim e ( 6 4 b it- tim e )
Transmission code format
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April 19, 2000
HT6230
· During Tsep and debounce time, the device
logic 1. If the sense input comes from XIN, the
corresponding command code together with
the system code stored in the system latches
are generated.
will reset immediately if a key is released.
· During Scan cycle in Tcode, a reset will occur
if a key is released in three cases described below:
¨ When one of the key scan drivers is in the
low state
¨ Before that key has been detected
¨ When MS is high and there is no wired connection in Z-key matrix
· Two-key system mode
The device goes into this mode by switching
the MS input pin to high state. The pull-high
resistors are only connected to XIN inputs except the first scan cycle. In the first scan cycle,
there only exists pull-high resistors in ZIN inputs. In this mode, the legal key operation is
that exactly one XIN and one ZIN are connected to two DRS drivers. In the first scan
duration, it detects which key in Z-key matrix
is pressed and generates an enable signal to
latch the system latches. While in the second
scan duration, it detects which key in the
X-key matrix is pressed and generates an enabled signal to latch the command latches. After being latched, the system and command
codes are transmitted.
Test pins (TT1 and TT2)
There are four modes by the combination of TT1
and TT2.
Control bit
TT1
TT2
Mode
0
0
Normal mode
1
1
Reset
1
0
Test mode 1
0
1
Test mode 2
A control bit is added after two start bits and
will be complemented if one key is released. The
decoder can decide whether the next code is a
new command or not.
Oscillator
The embedded part of the oscillator is an
RC-oscillation circuit. The OSC pin is the input
terminal of the RC-oscillation circuit and is connected to an external ceramic resonator (429kHz).
A resistor of 6.8kW must be in series with the
resonator. The resonator and resistor are
grounded at one side.
Reset (after key release)
In a complete code repetition time, as shown in
the figure below, the following situation of key
release results in a reset action.
D e b o u n c e
tim e
C o d e 1
T c o d e
T s e p
C o d e 2
T c o d e
R e p e titio n tim e
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HT6230
Application Circuits
V
1
V
2
3
D D
4
In fra -R e d
5
6
4 7 9
7
1 k 9
8
9
1 0
1 1
1 2
1 3
1 4
X IN 7
V D D
M S
X IN 6
Z IN 0
X IN 5
Z IN 1
X IN 4
Z IN 2
X IN 3
Z IN 3
X IN 2
M C O D E
X IN 1
C O D E
X IN 0
D R S 7
T T 1
D R S 6
T T 2
D R S 5
O S C
D R S 4
D R S 0
D R S 3
D R S 1
V S S
D R S 2
D D
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
H T 6 2 3 0
2 8 S O P
w h e re
R e s o n a to r (4 2 9 k H z )
6 .8 k 9
p u s h - b u tto n s w itc h
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April 19, 2000
HT6230
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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April 19, 2000