HOLTEK HT82K96E

HT82K96E
8-Bit USB Multimedia Keyboard Encoder OTP MCU
Features
· Operating voltage:
· 4096´15 program memory ROM
fSYS=6M/12MHz: 4.4V~5.5V
· 160´8 data memory RAM
· Low voltage reset function
· HALT function and wake-up feature reduce power
· 32 bidirectional I/O lines (max.)
consumption
· 8-bit programmable timer/event counter with over-
· 8-level subroutine nesting
flow interrupt
· Up to 0.33ms instruction cycle with 12MHz system
· 16-bit programmable timer/event counter and over-
clock at VDD=5V
flow interrupts
· Bit manipulation instruction
· Crystal oscillator (6MHz or 12MHz)
· 15-bit table read instruction
· Watchdog Timer
· 63 powerful instructions
· 6 channels 8-bit A/D converter
· All instructions in one or two machine cycles
· PS2 and USB modes supported
· 20-pin SOP, 48-pin SSOP package
· USB1.1 low speed function
· 4 endpoints supported (endpoint 0 included)
General Description
mice, keyboards and joystick. A HALT feature is included to reduce power consumption.
This device is an 8-bit high performance RISC-like
microcontroller designed for USB product applications.
It is particularly suitable for use in products such as
Rev. 1.70
1
April 22, 2004
HT82K96E
Block Diagram
U S B D + /C L K
U S B D -/D A T A
V 3 3 O
T M R 1 C
U S B 1 .1
P S 2
M
T M R 1
U
fS
Y S
X
/4
P A 7 /T M R 1
B P
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
T M R 0
U
fS
/4
Y S
P A 6 /T M R 0
X
T M R 0 C
IN T C
E N /D IS
W D T S
In s tr u c tio n
R e g is te r
M
M P
U
X
W D T P r e s c a le r
D A T A
M e m o ry
P B C
T im in g
G e n e ra to r
S T A T U S
O S
R
V
V
C 1
E S
D D
S S
U
S Y S C L K /4
X
W D T O S C
P A 0 ~ P A 5
P A 6 /T M R 0
P A 7 /T M R 1
P B 0 /A N 0 ~ P B 5 /A N 5
P B 6 /V R L
P B 7 /V R H
A /D C o n v e rte r
P O R T C
P C
A C C
P D C
P D
Rev. 1.70
P O R T B
P B
S h ifte r
P C C
O S C 2
P O R T A
P A
M U X
A L U
M
P A 6
P A 7
P A C
In s tr u c tio n
D e c o d e r
W D T
2
P O R T D
P C 0 ~ P C 7
P D 0 ~ P D 7
April 22, 2004
HT82K96E
Pin Assignment
P C 5
1
4 8
P C 6
P C 4
2
4 7
P C 7
P A 3
3
4 6
P A 4
P A 2
4
4 5
P A 5
P A 1
5
4 4
P A 6 /T M R 0
P A 0
6
4 3
P A 7 /T M R 1
P C 0
7
4 2
N C
P C 1
8
4 1
N C
P C 2
9
4 0
N C
P C 3
1 0
3 9
N C
N C
1 1
3 8
P D 3
N C
1 2
3 7
P D 2
N C
1 3
3 6
P D 1
N C
1 4
3 5
P D 0
P A 3
1
2 0
P A 4
P D 4
1 5
3 4
O S C 1
P A 2
2
1 9
P A 5
P D 5
1 6
3 3
O S C 2
P A 1
3
1 8
P A 6 /T M R 0
P D 6
1 7
3 2
R E S
P A 0
4
1 7
P A 7 /T M R 1
P D 7
1 8
3 1
V S S
P C 0
5
1 6
O S C 1
V D D
1 9
3 0
P B 7 /V R H
P D 4
6
1 5
O S C 2
V 3 3 O
2 0
2 9
P B 6 /V R L
V D D
7
1 4
R E S
U S B D + /C L K
2 1
2 8
P B 5 /A N 5
V 3 3 O
8
1 3
V S S
U S B D -/D A T A
2 2
2 7
P B 4 /A N 4
U S B D + /C L K
9
1 2
P B 7 /V R H
P B 0 /A N 0
2 3
2 6
P B 3 /A N 3
U S B D -/D A T A
1 0
1 1
P B 6 /V R L
P B 1 /A N 1
2 4
2 5
P B 2 /A N 2
H T 8 2 K 9 6 E
2 0 S O P -A
H T 8 2 K 9 6 E
4 8 S S O P -A
Pin Description
Pin Name
PA0~PA5
PA6/TMR0
PA7/TMR1
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/VRL
PB7/VRH
PD0~PD7
Rev. 1.70
I/O
ROM Code
Option
Description
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by ROM code option. The input or output mode is controlled by PAC (PA control register).
Pull-high resistor options: PA0~PA7
Pull-low resistor options: PA0~PA5
Pull-low
CMOS/NMOS/PMOS options: PA0~PA7
Pull-high
I/O
Wake up options: PA0~PA7
Wake-up
CMOS/NMOS/PMOS PA6 and PA7 are pin-shared with TMR0 and TMR1 input, respectively.
PA0~PA5 can be used as USB mouse X1, X2, Y1, Y2, Z1, Z2 input for
mouse hardware wake-up function
PA6, PA7 can be used as USB mouse button input for mouse hardware
wake-up function
I/O
I/O
Pull-high
Analog input
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined
by pull-high options).
The PB can be used as analog input of the analog to digital converter
(determined by options).
PB6, PB7 can be used as USB mouse button input for mouse Hardware
wake-up function
Pull-high
Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high option).
PD4 can be used as USB mouse button input for mouse hardware
wake-up function
3
April 22, 2004
HT82K96E
Pin Name
VSS
PC0~PC7
I/O
ROM Code
Option
¾
¾
Description
Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by
pull-high options).
PC0 can be used as USB mouse IRPT control pin for mouse hardware
wake-up function
I/O
Pull-high
RES
I
¾
Schmitt trigger reset input. Active low
VDD
¾
¾
Positive power supply
V33O
O
¾
3.3V regulator output
USBD+/CLK
I/O
¾
USBD+ or PS2 CLK I/O line
USB OR PS2 function is controlled by software control register
USBD-/DATA
I/O
¾
USBD- or PS2 DATA I/O line
USB or PS2 function is controlled by software control register
OSC1
OSC2
I
O
¾
OSC1, OSC2 are connected to an 6MHz or 12MHz Crystal/resonator
(determined by software instructions) for the internal system clock.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD
Ta=25°C
Parameter
Operating Voltage
Test Conditions
VDD
¾
Min.
Typ.
Max.
Unit
fSYS=6MHz
4.4
¾
5.5
V
fSYS=12MHz
4.4
¾
5.5
V
Conditions
IDD1
Operating Current (6MHz Crystal)
5V
No load, fSYS=6MHz
¾
6.5
12
mA
IDD2
Operating Current (12MHz Crystal)
5V
No load, fSYS=12MHz
¾
7.5
16
mA
ISTB1
Standby Current (WDT Enabled)
5V
No load, system HALT,
USB suspend
¾
¾
250
mA
ISTB2
Standby Current (WDT Disabled)
5V
No load, system HALT,
USB suspend
¾
¾
230
mA
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
0.8
V
VIH1
Input High Voltage for I/O Ports
5V
¾
2
¾
5
V
VIL2
Input Low Voltage (RES)
5V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
5V
¾
0.9VDD
¾
VDD
V
IOL1
I/O Port Sink Current for PB, PC1~PC7, PD
5V
VOL=3.4V
12
17
¾
mA
IOL2
I/O Port Sink Current for PB, PC1~PC7, PD
5V
VOL=0.4V
2
4
¾
mA
IOL3
I/O Port Sink Current for PA
5V
VOL=0.4V
5
10
¾
mA
Rev. 1.70
4
April 22, 2004
HT82K96E
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
IOL4
I/O Port Sink Current for PC0
5V
VOL=0.4V
10
25
¾
mA
IOH1
I/O Port Source Current for PC0
5V
VOH=3.4V
-8
-16
¾
mA
IOH2
I/O Port Source Current for PA, PB,
5V
PC1~PC7, PD
VOH=3.4V
-2
-5
¾
mA
RPH
Pull-high Resistance for PA, PB, PC, PD
5V
¾
25
50
80
kW
RPL
Pull-low Resistance for PA1~PA5
5V
¾
15
30
45
kW
VLVR
Low Voltage Reset
¾
¾
3
3.4
4.0
V
VV33O
3.3V Regulator Output
5V
IV33O=-5mA
3.0
3.3
3.6
V
EA/D
A/D Conversion Error
5V
Total error
¾
1
2
LSB
A.C. Characteristics
Symbol
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
Min.
Typ. Max.
Unit
fSYS
System Clock (Crystal OSC)
5V
¾
6
¾
12
MHz
fTIMER
Timer I/P Frequency (TMR0/TMR1)
5V
¾
0
¾
12
MHz
5V
¾
15
31
70
ms
tWDTOSC Watchdog Oscillator
tWDT1
Watchdog Time-out Period (WDT OSC)
5V
Without WDT prescaler
4
8
16
ms
tWDT2
Watchdog Time-out Period (System Clock)
¾
Without WDT prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
Wake-up from HALT
¾
1024
¾
tSYS
tSST
System Start-up Timer Period
¾
Power-up, Watchdog
Time-out from normal
¾
1024
¾
tWDTOSC
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
64
¾
tA/D
Note: tA/D=
Rev. 1.70
1
, fA/D=A/D clock source frequencies (6MHz, 3MHz, 1.5MHz, 0.75MHz)
fA /D
5
April 22, 2004
HT82K96E
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupts, the PC manipulates
the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
Program Counter - PC
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
USB interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 overflow
0
0
0
0
0
0
0
0
1
1
0
0
Skip
PC+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.70
@7~@0: PCL bits
6
April 22, 2004
HT82K96E
· Location 00CH
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
· Table location
Certain locations in the program memory are reserved
for special usage:
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, one page=256 words) and ²TABRDL
[m]² (the last page) transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is
well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining
1-bit words are read as ²0². The Table Higher-order
byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main routine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is
supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 008H .
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
U S B In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.70
7
April 22, 2004
HT82K96E
B a n k 0
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
0 0 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
T M R 1 H
1 0 H
T M R 1 L
1 1 H
T M R 1 C
Data Memory - RAM for Bank 0
1 2 H
P A
The data memory is designed with 190´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory (160´8). Most are read/write, but some are read
only.
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
The special function registers include the indirect addressing registers (R0;00H, R1;02H), Bank register
(BP, 04H), Timer/Event Counter 0 (TMR0;0DH),
Timer/Event Counter 0 control register (TMR0C;0EH),
Timer/Event Counter 1 higher order byte register
(TMR1H;0FH), Timer/Event Counter 1 lower order byte
register (TMR1L;10H), Timer/Event Counter 1 control
register (TMR1C;11H), program counter lower-order
byte register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointer (TBLP;07H), table higher-order byte register
(TBLH;08H), status register (STATUS;0AH), interrupt
control register (INTC;0BH), Watchdog Timer option
setting register (WDTS;09H), I/O registers (PA;12H,
PB;14H, PC;16H, PD;18H), I/O control registers
(PAC;13H, PBC;15H, PCC;17H, PDC;19H). USB/PS2
status and control register (USC;1AH), USB endpoint
interrupt status register (USR;1BH), system clock control register (SCC;1CH). A/D converter status and control register (ADSC;1DH) and A/D converter result
register (ADR;1EH). The remaining space before the
20H is reserved for future expanded usage and reading
these locations will get ²00H². The general purpose
data memory, addressed from 20H to BFH, is used for
data and control information under instruction commands.
Rev. 1.70
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
U S C
1 B H
U S R
1 C H
S C C
1 D H
A D S C
1 E H
A D R
S p e c ia l P u r p o s e
D A T A M E M O R Y
: U n u s e d
R e a d a s "0 0 "
1 F H
2 0 H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(1 6 0 B y te s )
B F H
Bank 0 RAM Mapping
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
8
April 22, 2004
HT82K96E
Data Memory - RAM for Bank 1
The indirect addressing pointer (MP1) can access
Bank0 or Bank1 RAM data according the value of BP is
set to 0 or 1 respectively.
The special function registers used in USB interface are
located in RAM bank 1. In order to access Bank1 register, only the Indirect addressing pointer MP1 can be
used and the Bank register BP should set to 1. The mapping of RAM bank 1 is as shown.
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
Accumulator
4 0 H
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
4 1 H
4 2 H
A W R
4 3 H
S T A L L
4 4 H
P IP E
4 5 H
S IE S
4 6 H
M IS C
Arithmetic and Logic Unit - ALU
4 7 H
4 8 H
F IF O 0
4 9 H
F IF O 1
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
4 A H
F IF O 2
4 B H
F IF O 3
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
4 C H
· Rotation (RL, RR, RLC, RRC)
U n d e fin e d , r e s e r v e d
fo r fu tu r e e x p a n s io n
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
F F H
The ALU not only saves the results of a data operation
but also changes the status register.
RAM Bank 1
Note:
Register 45H is defined for version C or later version
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results
in no operation.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended.
The indirect addressing pointer (MP0) always point to
Bank0 RAM addresses no matter the value of Bank
Register (BP).
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.
TO
5
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
¾
6
Unused bit, read as ²0²
¾
7
Unused bit, read as ²0²
Status Register
Rev. 1.70
9
April 22, 2004
HT82K96E
The TO flag can be affected only by system power-up, a
WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up.
USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of INTC) will be set.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· The USB resume signal from PC
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
· The access of the corresponding USB FIFO from PC
· The USB suspend signal from PC
· USB Reset signal
When PC Host access the FIFO of the HT82K96E, the
corresponding request bit of USR is set, and a USB interrupt is triggered. So user can easy to decide which
FIFO is accessed. When the interrupt has been served,
the corresponding bit should be cleared by firmware.
When HT82K96E receive a USB Suspend signal from
Host PC, the suspend line (bit0 of USC) of the
HT82K96E is set and a USB interrupt is also triggered.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from
becoming full.
Also when HT82K96E receive a Resume signal from
Host PC, the resume line (bit3 of USC) of HT82K96E is
set and a USB interrupt is triggered.
Whatever there are USB reset signal is detected, the
USB interrupt is triggered.
The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (; bit 5 of INTC), caused by a timer 0 overflow.
When the interrupt is enabled, the stack is not full and
the T0F bit is set, a subroutine call to location 08H will
occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
Register
INTC
(0BH)
The internal timer/even counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (;bit 6 of INTC), caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and the T1F
is set, a subroutine call to location 0CH will occur. The
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EUI
Controls the USB interrupt (1= enabled; 0= disabled)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)
4
USBF
5
T0F
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)
7
¾
USB interrupt request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC Register
Rev. 1.70
10
April 22, 2004
HT82K96E
Oscillator Configuration
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
There is an oscillator circuits in the microcontroller.
O S C 1
O S C 2
C r y s ta l O s c illa to r
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
System Oscillator
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an external signal to conserve power.
Priority Vector
a
USB interrupt
1
04H
b
Timer/Event Counter 0 overflow
2
08H
c
Timer/Event Counter 1 overflow
3
0CH
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), USB interrupt request flag (USBF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), enable USB interrupt bit (EUI) and enable master interrupt
bit (EMI) constitute an interrupt control register (INTC)
which is located at 0BH in the data memory. EMI, EUI,
ET0I and ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request
flags (T0F, T1F, USBF) are set, they will remain in the
INTC register until the interrupts are serviced or cleared
by a software instruction.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determines the ROM code option. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by ROM code option. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
S y s te m
C lo c k /4
W D T
O S C
R O M
C o d e
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.70
11
April 22, 2004
HT82K96E
Power Down Operation - HALT
Once the internal WDT oscillator (RC oscillator with a
period of 31ms/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
8ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS)
can give different time-out periods. If WS2, WS1, and WS0
are all equal to 1, the division ratio is up to 1:128, and the
maximum time-out period is 1s/5V. If the WDT oscillator is
disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that
in the HALT state the WDT may stop counting and lose
its protecting purpose. In this situation the logic can only
be restarted by external logic. The high nibble and bit 3
of the WDTS are reserved for user¢s defined flags, which
can only be set to ²10000² (WDTS.7~WDTS.3).
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others remain in their original status.
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
WDTS Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the PC and SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three methods are
adopted; external reset (a low level to RES), software instruction and a ²HALT² instruction. The software instruction include ²CLR WDT² and the other set - ²CLR
WDT1² and ²CLR WDT2². Of these two types of instruction, only one can be active depending on the ROM
code option - ²CLR WDT times selection option². If the
²CLR WDT² is selected (i.e. CLRWDT times equal one),
any execution of the ²CLR WDT² instruction will clear
the WDT. In the case that ²CLR WDT² and ²CLR WDT²
are chosen (i.e. CLRWDT times equal two), these two
instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
The time-out periods defined in WDTS can used as
²wake-up period² in the Mouse Hardware wake-up function. Please reference to Mouse Hardware Wake-up
function description.
Rev. 1.70
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
12
April 22, 2004
HT82K96E
V
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the
program can distinguish between different ²chip resets².
TO PDF
R E S
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Reset Circuit
H A L T
S y s te m
R e s e t
Reset Configuration
The functional unit chip reset status are shown below.
V D D
tS
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
S T
S S T T im e - o u t
R e s e t
Timer/event Counter Off
Reset Timing Chart
Rev. 1.70
R e s e t
R E S
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
C h ip
W a rm
W D T
Note: ²u² stands for ²unchanged²
R E S
D D
13
Input/output Ports
Input mode
SP
Points to the top of the stack
April 22, 2004
HT82K96E
The states of the registers is summarized in the table.
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-Out
(HALT)*
USB-Reset
(Normal)
USB-Reset
(HALT)
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
00-0 1000
00-0 1000
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
Program
Counter
000H
000H
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
Register
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
WDTS
1000 0111
1000 0111
1000 0111
1000 0111
uuuu uuuu
1000 0111
1000 0111
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PIPE
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
MISC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
USC
11xx 0000
uuxx uuuu
11xx 0000
11xx 0000
uuxx uuuu
uu00 0u00
uu00 0u00
USR
0100 0000
uuuu uuuu
0100 0000
0100 0000
uuuu uuuu
01uu 0000
01uu 0000
SCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0u00 u000
0u00 u000
ADSC
1000 0000
uuuu uuuu
1000 0000
1000 0000
uuuu uuuu
1000 0000
1000 0000
ADR
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
xxxx xxxx
xxxx xxxx
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 1.70
14
April 22, 2004
HT82K96E
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 0. The internal clock
source is coming from fSYS/4.
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter
0 contains an 8-bit programmable count-up counter and
the clock may comes from an external source or from
fSYS/4.
The external clock input allows the user to count external events, measure time intervals or pulse widths.
Using the internal clock source, there is only 1 reference
time-base for Timer/Event Counter 1. The internal clock
source is coming from fSYS/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths.
The Timer/Event Counter 1 contains an 16-bit programmable count-up counter and the clock may come from
an external source or from the system clock divided by
4.
Label (TMR0C)
Bits
¾
0~2
Function
Unused bit, read as ²0²
TE
3
To define the TMR0 active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
5
Unused bit, read as ²0²
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
¾
TM0
TM1
TMR0C Register
Label (TMR1C)
Bits
¾
0~2
Function
Unused bit, read as ²0²
TE
3
To define the TMR1 active edge of Timer/Event Counter 1
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer 1 counting
(0=disabled; 1=enabled)
5
Unused bit, read as ²0²
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
¾
TM0
TM1
TMR1C Register
fS
Y S
D a ta B u s
/4
T M 1
T M 0
T M R 0
T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 0
Rev. 1.70
15
April 22, 2004
HT82K96E
D a ta B u s
fS
Y S /4
T M 1
T M 0
T M R 1
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
L o w B y te
B u ffe r
1 6 B its
T im e r /E v e n t C o u n te r
(T M R 1 H /T M R 1 L )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 1
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR0/TMR1 has received a transient from low to high (or high to low if the
TE bits is ²0²) it will start counting until the TMR0/TMR1
returns to the original level and resets the TON. The
measured result will remain in the Timer/Event Counter
0/1 even if the activated transient occurs again. In other
words, only one cycle measurement can be done. Until
setting the TON, the cycle measurement will function
again as long as it receives further transient pulse. Note
that, in this operating mode, the Timer/Event Counter
0/1 starts counting not according to the logic level but
according to the transient edges. In the case of counter
overflows, the counter 0/1 is reloaded from the
Timer/Event Counter 0/1 preload register and issues the
interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4
of TMR0C/TMR1C) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automatically after the measurement cycle is completed. But in
the other two modes the TON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1
is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the
corresponding interrupt services.
There are 2 registers related to the Timer/Event Counter
0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical registers are mapped to TMR0 location; writing TMR0 makes
the starting value be placed in the Timer/Event Counter
0 preload register and reading TMR0 gets the contents
of the Timer/Event Counter 0. The TMR0C is a
timer/event counter control register, which defines some
options.
There are 3 registers related to Timer/Event Counter 1;
TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing
TMR1L will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMR1H will
transfer the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L preload
registers, respectively. The Timer/Event Counter 1
preload register is changed by each writing TMR1H operations. Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destination and the
lower-order byte buffer, respectively. Reading the
TMR1L will read the contents of the lower-order byte
buffer. The TMR1C is the Timer/Event Counter 1 control
register, which defines the operating mode, counting enable or disable and active edge.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR0/TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the fSYS/4
(Timer0/Timer1). The pulse width measurement mode
can be used to count the high or low level duration of the
external signal (TMR0/TMR1). The counting is based on
the fSYS/4 (Timer0/Timer1).
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 preload register will also reload that data to the Timer/Event Counter 0/1. But if the Timer/Event Counter 0/1 is turned on,
data written to it will only be kept in the Timer/Event
Counter 0/1 preload register. The Timer/Event Counter
0/1 will still operate until overflow occurs (a Timer/Event
Counter 0/1 reloading will occur at the same time).
W h e n t h e Ti m e r / E ve n t C o u n t e r 0 / 1 ( r e a d i n g
TMR0/TMR1) is read, the clock will be blocked to avoid
errors. As clock blocking may results in a counting error,
this must be taken into consideration by the programmer.
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contents in the Timer/Event Counter 0/1 to FFH or
FFFFH. Once overflow occurs, the counter is reloaded
from the Timer/Event Counter 0/1 preload register and
generates the interrupt request flag (T0F/T1F; bit 5/6 of
INTC) at the same time.
Rev. 1.70
16
April 22, 2004
HT82K96E
Input/Output Ports
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high/low
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H,
14H, 16H or 18H) instructions.
There are 32 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are
mapped to the data memory of [12H], [14H], [16H] and
[18H] respectively. All of these I/O ports can be used for
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction ²MOV A,[m]² (m=12H,
14H, 16H or 18H). For output operation, all the data is
latched and remains unchanged until the output latch is
rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS/NMOS/PMOS output
or Schmitt trigger input with or without pull-high/low resistor structures can be reconfigured dynamically (i.e.
on-the-fly) under software control. To function as an input, the corresponding latch of the control register must
write ²1². The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
For output function, CMOS/NMOS/PMOS configurations can be selected (NMOS and PMOS are available
for PA only). These control registers are mapped to locations 13H, 15H, 17H and 19H.
Each line of port A has the capability of waking-up the
device.
There are pull-high/low (PA only) options available for
I/O lines. Once the pull-high/low option of an I/O line is
selected, the I/O line have pull-high/low resistor. Otherwise, the pull-high/low resistor is absent. It should be
noted that a non-pull-high/low I/O line operating in input
mode will cause a floating state.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P A O u tp u t
C o n fig u r a tio n
R e a d D a ta R e g is te r
P A W a k e -u p
P A 6 /T M R 0
P A 7 /T M R 1
P H
Q
D
C K
Q B
P A
P B
P B
P C
P D
P G
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D D
D a ta B it
Q
D
C K
0 ~
0 /A
6 /V
0 ~
0 ~
0 ~
P A
N
R
P C
P D
P G
5 , P A 6 /T M R 0 , P A 7 /T M R 1
0 ~ P B 5 /A N 5
L , P B 7 /V R H
7
7
2
Q B
S
P L
M
U
X
P A W a k e - u p O p tio n
A N 0 ~ A N 5 , V R L , V R H
Input/Output Ports
Rev. 1.70
17
April 22, 2004
HT82K96E
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR such as changing a battery, the LVR will automatically reset the device internally.
V
O P R
5 .5 V
The LVR includes the following specifications:
V
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
3 .0 V
· The LVR uses the ²OR² function with the external
0 .9 V
RES signal to perform chip reset.
Note:
V
L V R
3 .3 V
VOPR is the voltage range for proper chip operation at 4MHz system clock.
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the
reset mode.
Mouse Hardware Wake-Up Function
When the HT82K96E is used for USB mouse application, in order to decrease the power consumption of the
HT82K96E in suspend mode. The HT82K96E has built-in Mouse Hardware wake-up function. Once the HT82K96E
jump to suspend mode, and the HWKUPSB (bit7 of SCC) is set to 1. The HT82K96E will automatically switch the IRPT
control pin (PC0) and detect movement of the X1, X2, Y1, Y2, Z1, Z2, corresponding to (PA0~PA5) and the state of the
five button corresponding to PA6, PA7, PB6, PB7, and PD4. Once there are mouse movement or state change. The
HT82K96E will wake-up the MCU by I/O method, otherwise the MCU is in suspend mode.
How long the HT82K96E to turn on the IRPT, and the low pulse period of the PC0 is defined by bit0~3 of the WDTS
(wake-up period) and the bit0~bit2 of the SCC (LED_on period) respectively. The following diagram show the IRPT
control pin timing.
W a k e - u p P e r io d
L E D _ o n P e r io d
Rev. 1.70
18
April 22, 2004
HT82K96E
Suspend Wake-Up Remote Wake-Up
To Configure the HT82K96E as PS2 Device
If there is no signal on USB bus is over 3ms, the
HT82K96E will go into suspend mode . The Suspend
line (bit 0 of USC) will be set to 1 and a USB interrupt is
triggered to indicate the HT82K96E should jump to suspend state to meet the 500mA USB suspend current
spec.
The HT82K96E can be define as USB interface or PS2
interface by configuring the SPS2 (bit 4 of USR) and
SUSB (bit 5 of USR). If SPS2=1, and SUSB=0, the
HT82K96E is defined as PS2 interface, pin USBD- is
now defined as PS2 Data pin and USBD+ is now defined as PS2 Clk pin. The user can easy to read or write
the PS2 Data or PS2 Clk pin by accessing the corresponding bit PS2DAI (bit 4 of USC), PS2CKI (bit 5 of
USC), PS2DAO (bit 6 of USC) and S2CKO (bit 7 of
USC) respectively.
In order to meet the 500mA suspend current, the firmware should disable the USB clock by clear the
USBCKEN (bit3 of the SCC) to ²0². The suspend current is about 400mA.
The user should make sure that in order to read the data
properly, the corresponding output bit must set to 1. For
example, if it want to read PS2 Data by reading PS2DAI,
the PS2DAO should set to 1. Otherwise it always read 0.
Also the user can further decrease the suspend current
to 250mA by set the SUSP2 (bit4 of the SCC). But if the
SUSP2 is set, the user make sure cannot enable the
LVR OPT option, otherwise the HT82K96E will be reset.
If SPS2=0, and SUSB=1, the HT82K96E is defined as
USB interface. Both the USBD- and USBD+ is driving by
SIE of the HT82K96E. The user only write or read the
USB data through the corresponding FIFO.
When the resume signal is sent out by the host, the
HT82K96E will wake up the MCU by USB interrupt and
the Resume line (bit 3 of USC) is set. In order to make
HT82K96E work properly, the firmware must set the
USBCKEN (bit 3 of SCC) to 1 and clear the SUSP2 (bit4
of the SCC). Since the Resume signal will be cleared
before the Idle signal is sent out by the host and the Suspend line (bit 0 of USC) is going to ²0². So when the
MCU is detecting the Suspend line (bit0 of USC), the
Resume line should be remembered and token into consideration.
Both SPS2 and SUSB is default ²0².
To Configure the ADC Block
The HT82K96E has built-in a 8-bit A/D converter with 6
channels (PB0~PB5). In order to make the A/D converter more flexibility, there are two mode: External Reference voltage and Internal Reference voltage. It can
easy to configure by setting the ADREF (bit 6 of USR).
For External Reference voltage, the reference voltage
of the A/D converter comes from external PB6/VRL and
PB7/VRH pins. Otherwise, the reference voltage is
coming from the VDD and VSS of MCU.
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt is triggered. The following is the timing diagram
S U S P E N D
PB0~PB5 is the 6-channels input of the A/D converter, it
can easy to define which channel is converting by configuring ACS2~ACS0 (bit 2~0 of ADSC). Also there are
four converter clock source to be selected by setting
ADCS1 (bit 4 of ADSC), ADCS0 ( bit 3 of ADSC).
U S B R e s u m e S ig n a l
U S B _ IN T
Once the ADON (bit 6 of ADSC) is set and send the start
pulse through START (bit 5 of ADSC). The A/D converter will be in operation. There are EOCB (bit 7 of
ADSC) to indicate whether the A/D converter is busy or
not. The EOCB is clear when the conversion is completed. The user can read the converter data by reading
the register ADR. In order to meet 500uA suspend current spec. . The user should disable the A/D by clearing
ADON before jump to suspend mode.
The device with remote wake up function can wake-up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of USC). Once the USB Host receive the
wake-up signal from HT82K96E. it will send a Resume
signal to device. The timing as follow:
S U S P E N D
M in . 1 U S B C L K
R M W K
U S B R e s u m e S ig n a l
M in .2 .5 m s
U S B _ IN T
Rev. 1.70
19
April 22, 2004
HT82K96E
The following is A/D converter timing diagrams
N o rm a l M o d e
T 1
A D O N
0
A /D
S T A R T
0
D 7
0
C o n v e r s io n S ta r ts
A /D
A /D
D 0
A /D
C o n v e r s io n
C o n v e r s io n S ta r ts
A /D
0 o r 1
C o n v e r s io n T im e
0 o r 1
A /D
C o n v e r s io n
0 o r 1
C o n v e r s io n T im e
0 o r 1
1
E O C B
P o w e r_ d o w n
A /D
C o n v e r s io n F in is h e d
A /D
C o n v e r s io n F in is h e d
USB Interface and A/D Converter
There are 7 registers, including AWR (address + remote wake up; 42H in bank 1), STALL (43H in bank 1), PIPE (44H in
bank 1), MISC (46H in bank 1), FIFO0 (48H in bank 1), FIFO1 (49H in bank 1), FIFO2 (4AH in bank 1) and FIFO3 (4BH
in bank 1) used for the USB function. AWR register contains current address and a remote wake up function control bit.
The initial value of AWR is ²00H². The address value extracted from the USB command has not to be loaded into this
register until the SETUP stage being finished.
AWR
Bits
R/W
Function
WKEN
0
W
Remote wake-up enable/disable
AD6~AD0
7~1
W
USB device address
PIPE register represents whether the corresponding endpoint is accessed by host or not. This register is set only after
the time when host accesses the corresponding endpoint. Only the last accessed endpoint is shown in this register.
STALL register shows whether the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to ²1². The STALL will be cleared by USB reset signal.
STALL
Bits
R/W
STL0
0
W
Stall the endpoint 0
STL1
1
W
Stall the endpoint 1
STL2
2
W
Stall the endpoint 2
STL3
3
W
Stall the endpoint 3
¾
7~4
W
Unused bit, read as ²0²
PIPE
Bits
R/W
EP0RW
0
R
Endpoint 0 accessed
EP1RW
1
R
Endpoint 1 accessed
EP2RW
2
R
Endpoint 2 accessed
EP3RW
3
R
Endpoint 3 accessed
¾
7~4
R
Unused bit, read as ²0²
Rev. 1.70
Function
Function
20
April 22, 2004
HT82K96E
SIES. Register (for version C or later version) is used to indicate the present signal state which the SIE receives and
also defines whether the SIE has to change the device address automatically.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Func.
NMI
EOT
Setup
NAK
IN
OUT
F0_ERR
Adr_set
R/W
R/W
R
R
R
R
R/W
R/W
R/W
Reg_Adr
01000101B
SIES Register Table
Func. Name
R/W
Description
Adr_set
R/W
This bit is used to configure the SIE to automatically change the device address with the
value of the Address+Remote_WakeUp Register (42H).
When this bit is set to ²1² by F/W, the SIE will update the device address with the value
of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully
read the data from the device by the IN operation. The SIE will clear the bit after updating
the device address. Otherwise, when this bit is cleared to ²0², the SIE will update the device address immediately after an address is written to the Address+Remote_WakeUp
Register (42H)
Default 0
F0_Err
R/W
This bit is used to indicate that some errors have occurred when accessing the FIFO0.
This bit is set by SIE and cleared by F/W.
Default 0
Out
R/W
This bit is used to indicate that an OUT token (except for the OUT zero length) has been
received. The F/W clear the bit after the OUT data has been read. This bit will also be
cleared by the SIE after the next valid SETUP token is received.
Default 0
IN
R
This bit is used to indicate that the current signal the USB is receiving from the PC Host is
IN token.
NAK
R
This bit is used to indicate that the SIE is transmitting NAK signal to the Host in response
to the PC Host IN or OUT token.
Setup
R
This bit indicates that the current token is setup token. Don¢t care CRC or EOP error of
the setup token, this bit has be set to ²1². When suspend=¢1¢ & setup=¢1¢, it indicates that
something is wrong in the USB Interface. Firmware in-charge must to do something to
save the device and keep it in good condition.
EOT
R
End of transaction flag, normal status is 1. If suspend=¢1¢ line & =¢0¢ indicates that something is wrong in the USB Interface. Firmware in-charge must to do something to save
the device and keep it in good condition.
R/W
This bit is used to control whether the USB interrupt is output to the MCU in NAK response to the PC Host IN or OUT token.
1: only has USB interrupt, data is transmitted to the PC host or data is received from the
PC Host
0: always has USB interrupt if the USB accesses FIFO0
Default 0
NMI
SIES Function Table
Rev. 1.70
21
April 22, 2004
HT82K96E
MISC register combines a command and status to control desired endpoint FIFO action and to show the status of
wanted endpoint FIFO. The MISC will be cleared by USB reset signal.
MISC
Bits
R/W
Function
REQ
0
After setting other status of desired one in the MISC, endpoint FIFO can be reR/W quested by setting this bit to ²1². After job has been done, this bit has to be cleared to
²0²
TX
1
This bit defines the direction of data transferring between MCU and endpoint FIFO.
When the TX is set to ²1², this means that MCU wants to write data to endpoint
FIFO. After the job has been done, this bit has to be cleared to ²0² before terminatR/W
ing request to represent end of transferring. For reading action, this bit has to be
cleared to ²0² to represent that MCU wants to read data from endpoint FIFO and has
to be set to ²1² after the job done.
CLEAR
2
R/W Clear the requested endpoint FIFO, even the endpoint FIFO is not ready.
SELP1
SELP0
4
3
To define which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
R/W 01: endpoint FIFO1
10: endpoint FIFO2
11: endpoint FIFO3
SCMD
5
It is used to show that the data in endpoint FIFO is SETUP command. This bit has to
R/W be cleared by firmware. That is to say, even the MCU is busing, the device will not
miss any SETUP commands from host.
READY
6
R
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready to work.
LEN0
7
R/W
It is used to indicate that a 0-sized packet is sent from host to MCU. This bit should
be cleared by firmware.
MCU can communicate with endpoint FIFO by setting the corresponding registers, of which address is listed in the following table. After reading current data, next data will show on after 2ms. using to check endpoint FIFO status and response to MSIC register, if read/write action is still going on.
Registers
R/W
Bank
Address
Bit7~Bit0
FIFO0
R/W
1
48H
Data7~Data0
FIFO1
R/W
1
49H
Data7~Data0
FIFO2
R/W
1
4AH
Data7~Data0
FIFO3
R/W
1
4BH
Data7~Data0
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,
writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing
and clearing.
Actions
MiSC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay 2ms, check 41H®read* from FIFO0 register and
check not ready (01H)®03H®02H
Write FIFO1 sequence
0AH®0BH®delay 2ms, check 4BH®write* to FIFO1 register and
check not ready (0BH)®09H®08H
Check whether FIFO0 can be read or not
00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFO1 can be written or not
0AH®0BH®delay 2ms, check 4BH (ready) or 0BH (not ready)®0AH
Read 0-sized packet sequence form FIFO0
00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H
Write 0-sized packet sequence to FIFO1
0AH®0BH®delay 2ms, check 0BH®0FH®0DH®08H
Note:
*: There are 2ms existing between 2 reading action or between 2 writing action
Rev. 1.70
22
April 22, 2004
HT82K96E
The definitions of the USB/PS2 status and control register (USC; 1AH) are as shown.
USC
Bits
R/W
Function
SUSP
0
R
Read only, USB suspend indication. When this bit is set to ²1² (set by SIE), it indicates the USB bus enters suspend mode. The USB interrupt is also triggered on any
changing of this bit.
RMWK
1
W
USB remote wake up command. It is set by MCU to force the USB host leaving the
suspend mode. When this bit is set to ²1², 2ms delay for clearing this bit to ²0² is
needed to insure the RMWK command is accepted by SIE.
URST
2
R/W
USB reset indication. This bit is set/cleared by USB SIE. This bit is used to detect
which bus (PS2 or USB) is attached. When the URST is set to ²1², this indicates an
USB reset is occurred (The attached bus is USB) and an USB interrupt will be initialized.
RESUME
3
R
USB resume indication. When the USB leaves suspend mode, this bit is set to ²1²
(set by SIE). This bit will appear 20ms waiting for MCU to detect. When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to
detecting the suspend state, MCU should set USBCKEN and clear SUSP2 (in SCC
register) to enable the SIE detecting function. The RESUME will be cleared while
the SUSP is going ²0². When MCU is detecting the SUSP, the RESUME (causes
MCU to wake-up) should be remembered and token into consideration.
PS2DAI
4
R
Read only, USBD-/DATA input
PS2CKI
5
R
Read only, USBD+/CLK input
PS2DAO
6
W
Data for driving USBD-/DATA pin when work under 3D PS2 mouse function.
(Default=²1²)
PS2CKO
7
W
Data for driving USBD+/CLK pin when work under 3D PS2 mouse function.
(Default=²1²)
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
serial bus (PS2 or USB) and A/D converter operation modes. The endpoint request flags (EP0IF, EP1IF, EP2IF and
EP3IF) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request
flag will be set to ²1² and the USB interrupt will occur (if USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request flag has to be cleared to ²0².
USR
Bits
EP0IF
0
When this bit is set to ²1² (set by SIE), it indicates the endpoint 0 is accessed and an
R/W USB interrupt will occur. When the interrupt has been served, this bit should be
cleared by firmware.
EP1IF
1
When this bit is set to ²1² (set by SIE), it indicates the endpoint 1 is accessed and an
R/W USB interrupt will occur. When the interrupt has been served, this bit should be
cleared by firmware.
EP2IF
2
When this bit is set to ²1² (set by SIE), it indicates the endpoint 2 is accessed and an
R/W USB interrupt will occur. When the interrupt has been served, this bit should be
cleared by firmware.
EP3IF
3
When this bit is set to ²1² (set by SIE), it indicates the endpoint 3 is accessed and an
R/W USB interrupt will occur. When the interrupt has been served, this bit should be
cleared by firmware.
SPS2
4
R/W The PS2 function is selected when this bit is set to ²1². (Default=²0²)
SUSB
5
R/W The USB function is selected when this bit is set to ²1². (Default=²0²)
ADREF
6
The reference voltage of A/D converter is coming from the VDD and VSS of MCU
R/W when this bit is set ²1². Otherwise, the reference voltage of A/D converter comes
from external PB6/VRL and PB7/VRH pins. (Default=²1²)
FIFO-cntl
7
Rev. 1.70
R/W
W
Function
For ICE only, 0 for FIFO read (Default=²0²); 1 for FIFO write
23
April 22, 2004
HT82K96E
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB
clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK).
SCC
Bits
R/W
Led_on Period
2~0
To define low pulse period of IRPT (PC0) for mouse hardware function.
The time base is 31.25ms (1/32kHz). Default value is 000.
000: 2´base
001: 3´base
R/W
010: 5´base
011: 9´base
100: 17´base
101: 33´base
110: 65´base
111: 127´base
USBCKEN
3
R/W
SUSP2
4
This bit is used for decreasing power consumption in suspend mode.
R/W In normal mode clean this bit=0 (Default=²0²)
In HALT mode set this bit=1 for decreasing power consumption.
¾
5
R/W Undefined, should be cleared to ²0²
SYSCLK
6
This bit is used to specify the system oscillator frequency used by MCU. If a 6MHz
R/W crystal oscillator or resonator is used, this bit should be set to ²1². If a 12MHz crystal
oscillator or resonator is used, this bit should be cleared to ²0² (default).
7
Hardware HALT mode wake-up detect circuit active under power down mode. Low
active.
R/W ²0²: WDT timer overflow will wake-up MCU system
²1²: WDT timer overflow will start hardware wake-up detect circuit but not wake-up
MCU system.
HWKUPSB
Function
USB clock control bit. When this bit is set to ²1², it indicates that the USB clock is enabled. Otherwise, the USB clock is turned-off. (Default=²0²)
The A/D converter implemented in the MCU is a 6-channel 8-bit A/D converter. The reference voltage (high reference
voltage and low reference voltage) can be selected as coming from external pins (PB6/VRL and PB7/VRH) or internal
power supplies of MCU (VDD and VSS). The VRL and VRH are used to set the minimal and maximal boundaries of the
full-scale range of the A/D converter. If an analog inputs, VRL or VRH is not used for A/D conversion, it also can be used
as a general purpose I/O line. The ADSC (A/D converter status and control register) register is used to set the configurations and A/D clock sources of A/D converter and control the operation of A/D converter.
ADSC
Bits
Function
ACS2~ACS0
2~0
These 3 bits are use to select one of eight A/D converter channels for the conversion. The
A/D converter input channels AN0~AN5 are pin-shared with PB0~PB5. PB6/VRL and
PB7/VRH are used for the A/D converter reference inputs. ACS2,ACS1,ACS0 :
000/001/010/011/100/101/110/111: AN0/AN1/AN2/AN3/AN4/AN5/VRL/VRH
ADCS1
ADCS0
4
3
A/D converter clock source selection. ADCS1,ADCS0:
00: 6MHz
01: 3MHz
10: 1.5MHz
11: 0.75MHz
START
5
Start the A/D conversion. (0®1®0: start, 0®1: reset A/D converter and A/D data register)
ADON
6
This bit is used to control the enable/disable of A/D converter circuit. If this bit is set to ²1²
the A/D converter enters operating mode. Otherwise, the A/D converter will be turned-off
EOCB
7
End of A/D conversion indication. (0: end of A/D conversion)
The A/D converter data register is used to store the result of A/D conversion.
ADR
Bits
D7~D0
7~0
Rev. 1.70
Function
Result of A/D conversion
24
April 22, 2004
HT82K96E
Mask Options
The following table shows all kinds of mask option in the microcontroller. All of the mask options must be defined to ensure proper system functioning.
No.
Option
1
Chip lock bit (by bit)
2
PA0~PA7 pull-high resistor enabled/disabled (by bit)
3
PA0~PA5 pull down resistor enabled/disabled (by bit)
4
PB0~PB7 pull-high resistor enabled/disabled (by nibble)
5
PC0~PC7 pull-high resistor enabled/disabled (by nibble)
6
PD0~PD7 pull-high resistor enabled/disabled (by nibble)
7
LVR enable/disable
8
WDT enable/disable
9
WDT clock source: fSYS/4 or WDTOSC
10
²CLRWDT² instruction(s): 1 or 2
11
PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain (by bit)
12
PA0~PA7 wake-up enabled/disabled (by bit)
13
A/D converter enabled/disabled
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications
5 W
V D D
U S B -
0 .1 m F
U S B +
*
3 3 W
*
1 0 m F
P A 0 ~ P A 7
*
V D D
1 0 0 k W
V S S
0 .1 m F
P C 0 ~ P C 7
2 2 p F
**
5 W
X 1
2 2 p F
*
1 0 k W
0 .1 m F
*
P B 0 ~ P B 7
P D 0 ~ P D 7
*
R E S
0 .1 m F
4 7 p F *
3 3 W
U S B D -/D A T A
4 7 p F *
V S S
*
*
*
4 7 p F
3 3 W
U S B D + /C L K
H T 8 2 K 9 6 E
Note:
1 .5 k W
V 3 3 O
O S C 2
**
0 .1 m F
O S C 1
*
4 7 p F
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible
Components with * are used for EMC issue.
Components with ** are used for resonator only.
Rev. 1.70
25
April 22, 2004
HT82K96E
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.70
26
April 22, 2004
HT82K96E
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.70
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
27
April 22, 2004
HT82K96E
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
28
April 22, 2004
HT82K96E
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
29
April 22, 2004
HT82K96E
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
30
April 22, 2004
HT82K96E
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
April 22, 2004
HT82K96E
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
April 22, 2004
HT82K96E
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
33
April 22, 2004
HT82K96E
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
April 22, 2004
HT82K96E
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
35
April 22, 2004
HT82K96E
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
April 22, 2004
HT82K96E
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
April 22, 2004
HT82K96E
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
April 22, 2004
HT82K96E
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
April 22, 2004
HT82K96E
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.70
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
40
April 22, 2004
HT82K96E
Package Information
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 1.70
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
490
¾
510
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
41
April 22, 2004
HT82K96E
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
E
Symbol
Rev. 1.70
a
F
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
42
April 22, 2004
HT82K96E
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 1.70
43
April 22, 2004
HT82K96E
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.70
21.3
44
April 22, 2004
HT82K96E
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0±0.3
P
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
2.0 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
12.0±0.1
B0
Cavity Width
16.20±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.70
0.35±0.05
25.5
45
April 22, 2004
HT82K96E
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.70
46
April 22, 2004