HOLTEK HT46R23

HT46R23
8-Bit OTP Microcontroller
Features
· Operating voltage:
· Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 3.3V~5.5V
fSYS=8MHz: 4.5V~5.5V
at VDD=5V
· 8-level subroutine nesting
· 23 bidirectional I/O lines (max.)
· 8 channels 10-bit resolution (9-bit accuracy) A/D con-
· 1 interrupt input shared with an I/O line
verter
· 16-bit programmable timer/event counter with overflow
· 2-channel (6+2)/(7+1)-bit PWM output shared with
· On-chip crystal and RC oscillator
· Bit manipulation instruction
· Watchdog Timer
· 15-bit table read instruction
· 4096´15 program memory PROM
· 63 powerful instructions
· 192´8 data memory RAM
· All instructions in one or two machine cycles
· Supports PFD for sound generation
· Low voltage reset function
interrupt and 7-stage prescaler
two I/O lines
· I2C BUS (slave mode)
· HALT function and wake-up feature reduce power
consumption
· 24/28-pin SKDIP/SOP package
General Description
The device is an 8-bit high performance RISC-like
microcontroller designed for multiple I/O product applications. It is particularly suitable for use in products
such as washing machine controllers and home appliances. A HALT feature is included to reduce power consumption.
The program and option memories can be electrically
programmed, making this microcontroller suitable for
product development applications.
2
I C is a trademark of Philips Semiconductors.
Rev. 1.30
1
August 17, 2001
HT46R23
Block Diagram
P A 5 /IN T
In te rru p t
C ir c u it
M
T M R
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
U
P r e s c a le r
fS
Y S
P A 4 /T M R
X
T M R C
IN T C
P A 4
P A 3 /P F D
S Y S C L K /4
In s tr u c tio n
R e g is te r
M
M P
U
X
W D T
P r e s c a le r
D A T A
M e m o ry
P W
X
R C
P O R T D
P D 0 /P W
P D
O S C
M 0 ~ P D 1 /P W
M 1
M U X
In s tr u c tio n
D e c o d e r
8 -C h a n n e l
A /D C o n v e rte r
S T A T U S
A L U
S
S
P B C
S h ifte r
T im in g
G e n e ra to r
O S
R E
V D
V S
U
M
P D C
O S C 2
M
W D T
P A 3 , P A 5
A C C
C 1
L V R
P O R T B
P B 0 /A N 0 ~ P B 7 /A N 7
P B
P A C
O p tio n
P R O M
P A 0
P A 3
P A 4
P A 5
P A 6
P A 7
P O R T A
P A
I2 C B U S
S la v e M o d e
D
P C
~ P
/P
/T
/IN
/S
/S
A 2
F D
M R
T
D A
C L
P C 0 ~ P C 4
P C C
Pin Assignment
P B 5 /A N 5
1
2 8
P B 6 /A N 6
P B 4 /A N 4
2
2 7
P B 7 /A N 7
P B 5 /A N 5
1
2 4
P B 6 /A N 6
P A 3 /P F D
3
2 6
P A 4 /T M R
P B 4 /A N 4
2
2 3
P B 7 /A N 7
P A 2
4
2 5
P A 5 /IN T
P A 3 /P F D
3
2 2
P A 4 /T M R
P A 1
5
2 4
P A 6 /S D A
P A 2
4
2 1
P A 5 /IN T
P A 0
6
2 3
P A 7 /S C L
P A 1
5
2 0
P A 6 /S D A
P B 3 /A N 3
7
2 2
O S C 2
P A 0
6
1 9
P A 7 /S C L
P B 2 /A N 2
8
2 1
O S C 1
P B 3 /A N 3
7
1 8
O S C 2
P B 1 /A N 1
9
2 0
V D D
P B 2 /A N 2
8
1 7
O S C 1
P B 0 /A N 0
1 0
1 9
R E S
P B 1 /A N 1
9
1 6
V D D
V S S
1 1
1 8
P D 1 /P W M 1
P B 0 /A N 0
1 0
1 5
R E S
P C 0
1 2
1 7
P D 0 /P W M 0
V S S
1 1
1 4
P D 0 /P W M
P C 1
1 3
1 6
P C 4
P C 0
1 2
1 3
P C 1
P C 2
1 4
1 5
P C 3
H T 4 6 R 2 3
2 4 S K D IP -A /S O P -A
Rev. 1.30
H T 4 6 R 2 3
2 8 S K D IP -A /S O P -A
2
August 17, 2001
HT46R23
Pin Description
ROM Code
Option
Description
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: port option) or A/D input.
Once a PB line is selected as an A/D input (by using software control), the
I/O function and pull-high resistor are disabled automatically.
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6/SDA
PA7/SCL
I/O
Pull-high
Wake-up
PA3 or PFD
I/O or Serial Bus
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by ROM code option. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by
pull-high options: bit option). The PFD, TMR and INT are pin-shared with
PA3, PA4 and PA5, respectively. Once the I2C BUS function is used, the internal registers related to PA6 and PA7 can not be used.
VSS
¾
¾
PC0~PC4
I/O
Pull-high
Bidirectional 5-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: port option).
I/O
Pull-high
I/O or PWM
Bidirectional 2-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: port option). The PWM0/PWM1 output function are pin-shared with PD0/PD1 (dependent on PWM optios).
RES
I
¾
VDD
¾
¾
Pin Name
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PD0/PWM0
PD1/PWM1
OSC1
OSC2
I/O
I
O
Crystal
or RC
Negative power supply, ground.
Schmitt trigger reset input. Active low.
Positive power supply
OSC1, OSC2 are connected to an RC network or a Crystal (determined by
ROM code option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.30
3
August 17, 2001
HT46R23
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
VDD1
Operating Voltage
¾
fSYS=4MHz
3.3
¾
5.5
V
VDD2
Operating Voltage
¾
fSYS=8MHz
4.5
¾
5.5
V
IDD1
Operating Current (Crystal OSC)
3.3V No load, f
SYS=4MHz
ADC
disable
5V
¾
1.3
3
mA
¾
3.3
5
mA
IDD2
Operating Current (RC OSC)
3.3V No load, f
SYS=4MHz
ADC
disable
5V
¾
1.3
3
mA
¾
3.3
5
mA
IDD3
Operating Current
¾
4
8
mA
IADC
Only ADC Enable, Others Disable
¾
1
2
mA
¾
2
4
mA
ISTB1
Standby Current (WDT Enabled)
¾
¾
5
mA
¾
¾
10
mA
ISTB2
Standby Current (WDT Disabled)
¾
¾
1
mA
¾
¾
2
mA
VAD
A/D Input Voltage
¾
0
¾
VDD
V
VIL1
Input Low Voltage for I/O Ports, 3.3V
TMR and INT
5V
¾
0
¾
0.3VDD
V
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports, 3.3V
TMR and INT
5V
¾
0.7VDD
¾
VDD
V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
3.3V
¾
0
¾
0.4VDD
V
5V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
3.3V
¾
0.9VDD
¾
VDD
V
5V
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
2.7
3
3.3
V
IOL
I/O Port Sink Current
3.3V VOL=0.1VDD
4
8
¾
mA
VOL=0.1VDD
10
20
¾
mA
IOH
I/O Port Source Current
3.3V VOH=0.9VDD
-2
-4
¾
mA
VOH=0.9VDD
-5
-10
¾
mA
RPH
Pull-high Resistance
3.3V
¾
40
60
80
kW
5V
¾
10
30
50
kW
EAD
A/D Conversion Error
5V
¾
¾
±0.5
±1
LSB
Rev. 1.30
5V
3.3V
5V
3.3V
5V
3.3V
5V
No load, fsys=8MHz
ADC disable
No load
No load, system HALT
No load, system HALT
¾
5V
5V
4
August 17, 2001
HT46R23
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
400
¾
4000
kHz
5V
¾
400
¾
8000
kHz
3.3V
¾
400
¾
4000
kHz
5V
¾
400
¾
8000
kHz
3.3V
¾
0
¾
4000
kHz
5V
¾
0
¾
8000
kHz
VDD
Conditions
3.3V
fSYS1
System Clock (Crystal OSC)
fSYS2
System Clock (RC OSC)
fTIMER
Timer I/P Frequency (TMR)
tAD
A/D Clock Period
5V
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tWDTOSC
Watchdog Oscillator
3.3V
¾
43
86
168
ms
5V
¾
36
72
144
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
*tSYS
tINT
Interrupt Pulse Width
¾
1
¾
¾
ms
tHBUS
I2C BUS Clock Period
¾
64
¾
¾
*tSYS
Power-up, reset or
wake-up from HALT
¾
Connect to external
pull-high resistor 2kW
Note: *tSYS=1/fSYS
Rev. 1.30
5
August 17, 2001
HT46R23
Functional Description
Execution flow
cremented by one. The program counter then points to the
memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in program PROM are executed and its contents specify full range of program
memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are in-
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
0
1
0
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
0
1
1
0
0
I2C BUS Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
*0
PC+2
@3 @2 @1 @0
Program counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.30
@7~@0: PCL bits
6
August 17, 2001
HT46R23
· Location 00CH
Program memory - PROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
This area is reserved for the A/D converter interrupt
service program. If an A/D converter interrupt results
from an end of A/D conversion, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 00CH.
Certain locations in the program memory are reserved
for special usage:
· Location 010H
This area is reserved for the I2C BUS interrupt service
program. If the I2C BUS interrupt resulting from a
slave address is match or completed one byte of data
transfer, and if the interrupt is enable and the stack is
not full, the program begins execution at location
010H.
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
· Location 004H
· Table location
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Any location in the PROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 1 bit is read as ²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), which indicates the table location. Before accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the operation. These areas may function as normal program
memory depending upon the requirements.
· Location 008H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 0 8 H
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
0 0 C H
A /D
0 1 0 H
C o n v e r te r In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
H - B U S In te r r u p t S u b r o u tin e
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
F 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.30
7
August 17, 2001
HT46R23
Stack register - STACK
0 0 H
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R H
0 D H
T M R L
0 E H
T M R C
S p e c ia l P u r p o s e
D A T A M E M O R Y
0 F H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
1 0 H
1 1 H
Data memory - RAM
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
: U n u s e d
R e a d a s "0 0 "
1 C H
The data memory is designed with 224´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory (192´8). Most are read/write, but some are read
only.
1 D H
1 E H
IN T C 1
1 F H
The special function registers include the indirect addressing registers (00H;02H), timer/event counter
higher-order byte register (TMRH;0CH), timer/event
counter low-order byte register (TMRL;0DH),
timer/event counter control register (TMRC;0EH), program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC0;
0BH), PWM data register (PWM0;1AH, PWM1;1BH),
the I2C BUS slave address register (HADR;20H), the I2C
BUS control register (HCR;21H), the I2C BUS status register (HSR;22H), the I2C BUS data register (HDR;23H), the
A/D result lower-order byte register (ADRL;24H), the A/D
result higher-order byte register (ADRH;25H), the A/D control register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H,
PD;18H) and I/O control registers (PAC;13H, PBC;15H,
PCC;17H, PDC;19H). The remaining space before the
40H is reserved for future expanded usage and reading
these locations will get ²00H². The general purpose data
memory, addressed from 40H to FFH, is used for data
and control information under instruction commands.
Rev. 1.30
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
2 0 H
H A D R
2 1 H
H C R
2 2 H
H S R
2 3 H
H D R
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
3 F H
4 0 H
F F H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(1 9 2 B y te s )
RAM mapping
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
8
August 17, 2001
HT46R23
operations related to the status register may give different results from those intended. The TO flag can
be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PD flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
Indirect addressing register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] or [02H] will access data memory
pointed to by MP0[01H] or MP1[03H] respectively.
Reading location 00H or 02H itself indirectly will return
the result 00H. Writing indirectly result in no operation.
The memory pointer registers (MP0 and MP1 are 8-bit
registers).
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Interrupt
Arithmetic and logic unit - ALU
The device provides an external interrupt, an internal
timer/event counter interrupt, the A/D converter interrupt
and the I2C BUS interrupts. The interrupt control register
0 (INTC0;0BH) and interrupt control register 1
(INTC1;1EH) contains the interrupt control bits to set the
enable/disable and the interrupt request flags.
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC0 and INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must be prevented from becoming full.
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
also changes the status register.
Status register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PD), and watchdog time-out flag (TO).
It also records the status information and controls the
operation sequence.
With the exception of the TO and PD flags, bits in the
status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PD flag. In addition
Labels
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by system power-up or executing the ²CLR WDT² instruction. PD is set by executing the ²HALT² instruction.
TO
5
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
¾
6, 7
Unused bit, read as ²0²
Status register
Rev. 1.30
9
August 17, 2001
HT46R23
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
stack is not full and the HIF bit is set, a subroutine call to
location 10H will occur. The related interrupt request flag
(HIF) will be reset and the EMI bit cleared to disable further
interrupts.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET² or
²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit
4 of INTC0) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC0), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
No.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC0),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
Register Bit No. Label
INTC0
(0BH)
0
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ETI
Controls the timer/event
counter interrupt
(1= enabled; 0= disabled)
3
4
5
TF
6
ADF
7
¾
1
04H
Timer/event Counter Overflow
2
08H
c
A/D Converter Interrupt
3
0CH
4
10H
2
I C BUS Interrupt
Register Bit No. Label
External interrupt request flag
(1= active; 0= inactive)
Internal timer/event counter
request flag
(1= active; 0= inactive)
A/D converter request flag
(1= active; 0= inactive)
INTC1
(1EH)
Unused bit, read as ²0²
INTC0 register
2
The I C BUS interrupt is initialized by setting the I2C BUS
interrupt request flag (HIF; bit 4 of INTC1), caused by a
slave address match (HAAS=²1²) or one byte of data
transfer is completed. When the interrupt is enabled, the
Rev. 1.30
External Interrupt
b
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request
flag (ADF), the I2C BUS interrupt request flag (HIF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI),
enable I2C BUS interrupt bit (EHI) and enable master interrupt bit (EMI) constitute an interrupt control register 0
(INTC0) and an interrupt control register 1 (INTC1)
which are located at 0BH and 1EH in the data memory.
EMI, EEI, ETI, EADI, EHI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the
interrupt request flags (TF, EIF, ADF, HIF) are set, they
will remain in the INTC0 and INTC1 register until the interrupts are serviced or cleared by a software instruction.
Controls the A/D converter
EADI interrupt
(1= enabled; 0= disabled)
EIF
Priority Vector
a
d
Function
Controls the master (global)
EMI interrupt
(1= enabled; 0= disabled)
Interrupt Source
Function
Controls the I2C BUS interrupt
(1= enabled; 0= disabled)
0
EHI
1
¾
Unused bit, read as ²0²
2
¾
Unused bit, read as ²0²
3
¾
Unused bit, read as ²0²
4
HIF
5
¾
Unused bit, read as ²0²
6
¾
Unused bit, read as ²0²
7
¾
Unused bit, read as ²0²
I2C BUS interrupt request
flag (1= active; 0= inactive)
INTC1 register
10
August 17, 2001
HT46R23
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the system enters the power down mode, the system clock is
stopped, but the WDT oscillator still works with a period of
approximately 72ms/5V. The WDT oscillator can be disabled by ROM code option to conserve power.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
Watchdog Timer - WDT
The clock source of the WDT is implemented by an dedicated RC oscillator (WDT oscillator) or instruction clock
(system clock divided by 4) decided by ROM code options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location
with unpredictable results. The watchdog timer can be
disabled by a ROM code option. If the watchdog timer is
disabled, all the executions related to the WDT result in
no operation.
Oscillator configuration
There are two oscillator circuits in the microcontroller.
O S C 1
O S C 1
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C
O s c illa to r
Once an internal WDT oscillator (RC oscillator with period 72ms normally) is selected, it is divided by 212~215
(by ROM code option to get the WDT time-out period).
The minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the
WDT ROM code option, longer time-out periods can be
realized. If the WDT time-out is selected 215, the maximum time-out period is divided by 2 15 ~2 16 about
2.3s~4.7s.
System oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by the ROM code option. No matter what oscillator type
is selected, the signal provides the system clock. The
HALT mode stops the system oscillator and ignores an
external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accurate oscillator frequency is desired.
If the WDT oscillator is disabled, the WDT clock may still
cone from the instruction clock and operate in the same
manner except that in the halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
S y s te m
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. Whereas in the halt
mode, the overflow will initialize a ²warm reset² only the
PC and SP are reset to zero. To clear the contents of WDT,
three methods are adopted; external reset (a low level to
RES), software instructions, or a HALT instruction. The
software instructions include CLR WDT and the other set -
C lo c k /4
M a s k
o p tio n
s e le c t
W D T
O S C
fs
D iv id e r
fs/2
8
W D T P r e s c a le r
M a s k O p tio n
W D T C le a r
C K
R
T
C K
R
T
T im e - o
fs /2 1 5 ~
fs /2 1 4 ~
fs /2 1 3 ~
fs /2 1 2 ~
u t R e s e t
fs /2 1 6
fs /2 1 5
fs /2 1 4
fs /2 1 3
Watchdog Timer
Rev. 1.30
11
August 17, 2001
HT46R23
CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the ROM code
option - ²CLR WDT times selection option². If the ²CLR
WDT² is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In
case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e.
CLRWDT times equal two), these two instructions must be
executed to clear the WDT; otherwise, the WDT may reset
the chip because of time-out.
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
If the WDT time-out period is selected fs/212 (ROM code
option), the WDT time-out period ranges from
fs/212~fs/213, since the ²CLR WDT² or ²CLR WDT1² and
²CLR WDT2² instructions only clear the last two stages of
the WDT.
· RES reset during normal operation
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PD and TO flags, the
program can distinguish between different ²chip resets².
Power down operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
V D D
· WDT will be cleared and recounted again (if the WDT
R E S
clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
S T
S S T T im e - o u t
· The PD flag is set and the TO flag is cleared.
C h ip
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PD flags are examined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
the ²CLR WDT² instruction and is set when executing
the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others keep their original status.
R e s e t
Reset timing chart
V
D D
R E S
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the ROM code option. Awakening from an I/O
port stimulus, the program will resume execution of the
next instruction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
Rev. 1.30
tS
Reset circuit
H A L T
W a rm
R e s e t
W D T
R E S
O S C 1
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset configuration
12
August 17, 2001
HT46R23
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status
are shown below.
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
PC
000H
1
u
WDT time-out during normal operation
Interrupt
Disable
1
1
WDT wake-up HALT
WDT
Clear. After master reset, WDT
begins counting
Note: ²u² means ²unchanged²
Timer/event Counter Off
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
Input/output Ports
Input mode
SP
Points to the top of the stack
The registers states are summarized in the following table.
Register
Rese t(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Rese
(HALT)
WDT Time-out
(HALT)*
TMRL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PCC
Program
Counter
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PD
---- --11
---- --11
---- --11
---- --11
---- --uu
PDC
---- --11
---- --11
---- --11
---- --11
---- --uu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
HADR
xxxx xxx-
xxxx xxx-
xxxx xxx-
xxxx xxx-
uuuu uuu-
HCR
0--0 0---
0--0 0---
0--0 0---
0--0 0---
u--u u---
HSR
100- -0-1
100- -0-1
100- -0-1
100- -0-1
uuu- -u-u
HDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Rev. 1.30
13
August 17, 2001
HT46R23
Register
Rese t(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Rese
(HALT)
WDT Time-out
(HALT)*
ADRL
xx-- ----
xx-- ----
xx-- ----
xx-- ----
uu-- ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
--- --00
u--- --uu
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Timer/Event Counter
surement mode can be used to count the high or low level
duration of the external signal (TMR). The counting is based
on the fINT.
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
16-bit programmable count-up counter and the clock may
come from an external source or the system clock.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow
occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request
flag (TF; bit 5 of INTC0) at the same time.
Using the internal system clock, there is only one reference time-base. The internal clock source comes from
fSYS. The external clock input allows the user to count
external events, measure time intervals or pulse widths,
or to generate an accurate time base.
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR has received a
transient from low to high (or high to low if the TE bits is
²0²) it will start counting until the TMR returns to the original level and resets the TON. The measured result will
remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared automatically after the measurement cycle is completed.
There are three registers related to the timer/event counter; TMRH (0CH), TMRL (0DH), TMRC (0EH). Writing
TMRL will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMRH will
transfer the specified data and the contents of the
lower-order byte buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload register
is changed by each writing TMRH operations. Reading
TMRH will latch the contents of TMRH and TMRL counters to the destination and the lower-order byte buffer, respectively. Reading the TMRL will read the contents of the
lower-order byte buffer. The TMRC is the timer/event
counter control register, which defines the operating
mode, counting enable or disable and active edge.
The TM0, TM1 bits define the operating mode. The event
count mode is used to count external events, which means
the clock source comes from an external (TMR) pin. The
timer mode functions as a normal timer with the clock
source coming from the fINT clock. The pulse width meaP W M
(6 + 2 ) o r (7 + 1 )
c o m p a re
fS
Y S
T o P D 0 /P D 1 c ir c u it
8 - s ta g e p r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
1 /2
P F D
Timer/Event Counter
Rev. 1.30
14
August 17, 2001
HT46R23
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt
service.
A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trigger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding
latch of the control register must write ²1². The input
source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify-write² instruction.
In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will
also reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMRH) is
read, the clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this must be taken
into consideration by the programmer.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal. The timer prescaler is also
used as the PWM counter.
Label
Bits
(TMRC)
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 18H) instructions.
Function
To define the prescaler stages, PSC2,
PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
PSC0~
0~2
PSC2
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
3
To define the TMR active edge of timer/
event counter
(0=active on low to high;
1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
¾
5
Unused bit, read as ²0²
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TE
TM0
TM1
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 3-bit of port C and 6-bit of port D are
not physically implemented; on reading them a ²0² is returned whereas writing then results in a no-operation.
See Application note.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by timer/event
counter overflow signal. The input mode always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data
register only. The I/O functions of PA3 are shown below.
TMRC register
Input/output ports
I/O
I/P
Mode (Normal)
There are 23 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
Rev. 1.30
PA3
Note:
15
Logical
Input
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
Logical
Output
Logical
Input
PFD
(Timer on)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
August 17, 2001
HT46R23
V
C o n tr o l B it
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
D D
P U
P A 0
P A 3
P A 4
P A 5
P A 6
P B 0
P C 0
P D 0
P D 1
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
Q
C K
W r ite D a ta R e g is te r
~ P A 2
/P F D
/T M R
/IN T
, P A 7
/A N 0 ~ P B 7 /A N 7
~ P C 5
/P W M 0
/P W M 1
S
M
(P D 0 o r P W M 0 ) P A 3
(P D 1 o r P W M 1 ) P F D
M
R e a d D a ta R e g is te r
U
U
X
P F D E N
(P A 3 )
X
S y s te m W a k e -u p
( P A o n ly )
O P 0 ~ O P 7
IN T fo r P A 5 O n ly
T M R
fo r P A 4 O n ly
Input/output ports
The PA5 and PA4 are pin-shared with INT and TMR pins
respectively.
A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1. If the PWM function is
enabled, the PWM0/PWM1 signal will appear on
PD0/PD1 (if PD0/PD1 is operating in output mode). The
I/O functions of PD0/PD1 are as shown.
I/O
I/P
Mode (Normal)
PD0
PD1
Logical
Input
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
Logical
Output
Logical
Input
PWM0
PWM1
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
Modulation cycle i
(i=0~3)
PWM
Duty Cycle
i<AC
DC + 1
64
i³AC
DC
64
A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
The microcontroller provides 2 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1. The PWM channels have their data registers
denoted as PWM0 (1AH) and PWM1 (1BH). The frequency source of the PWM counter comes from fSYS.
The PWM registers are two 8-bit registers. The waveforms of PWM outputs are as shown. Once the
PD0/PD1 are selected as the PWM outputs and the output function of PD0/PD1 are enabled (PDC.0/PDC.1
=²0²), writing 1 to PD0/PD1 data register will enable the
PWM output function and writing ²0² will force the
PD0/PD1 to stay at ²0².
Rev. 1.30
AC (0~3)
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
The group 2 is denoted by AC which is the value of
PWM.0.
16
August 17, 2001
HT46R23
fS
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
P W M
m o d u la tio n p e r io d : 6 4 /fS
Y S
P W M
c y c le : 2 5 6 /fS
Y S
(6+2) PWM mode
fS
/2
Y S
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
P W M
c y c le : 2 5 6 /fS
Y S
(7+1) PWM mode
ADRL are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If
the users want to start an A/D conversion. Define PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0®1®0). At the end of A/D conversion, the EOC bit is
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
i<AC
DC + 1
128
i³AC
DC
128
Modulation cycle i
(i=0~1)
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
Modulation Frequency
FSYS/64 for (6+2) bits mode
FSYS/128 for (7+1) bits mode
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
[PWM]/256
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
A/D converter
The 8 channels and 10-bit resolution A/D (9-bit accuracy) converter are implemented in this microcontroller.
The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH
(25H), ADCR (26H) and ACSR (27H). The ADRH and
Rev. 1.30
17
August 17, 2001
HT46R23
converter circuit is power on. The EOC bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In
order to ensure the A/D conversion is completed, the
START should remain at ²0² until the EOC is cleared to
²0² (end of A/D conversion).
ACS2 ACS1 ACS0
The bit 7 of the ACSR is used for testing purposes only.
It can not be used by the users. The bit1 and bit0 of the
ACSR are used to select A/D clock sources.
Label
Bits
(ACSR)
ADCS0
ADCS1
¾
TEST
0
0
A0
0
0
1
A1
0
1
0
A2
0
1
1
A3
1
0
0
A4
1
0
1
A5
1
1
0
A6
1
1
1
A7
Analog input channel selection
When the A/D conversion is completed, the A/D interrupt request flag is set. The EOC bit is set to ²1² when
the START bit is set from ²0² to ²1².
Register
2~6 Unused bit, read as ²0²
7
0
Function
Selects the A/D converter clock
source
00= system clock¸2
01= system clock¸8
10= system clock¸32
11= undefined
0
1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL
D1 D0
¾
¾
¾
¾
¾
¾
ADRH
D9 D8 D7
D6
D5
D4
D3
D2
Note: *: D0~D9 is A/D conversion result data bit
LSB~MSB.
For test mode used only
ACSR register
Label
Bits
(ADCR)
Analog Channel
Function
ACS0
ACS1
ACS2
0
1
2
Defines the analog channel select.
PCR0
PCR1
PCR2
3
4
5
Defines the port B configuration select.
If PCR0, PCR1 and PCR2 are all zero,
the ADC circuit is power off to reduce
power consumption
EOC
6
Provides response at the end of the
A/D conversion.
(0= end of A/D conversion)
START
7
Starts the A/D conversion. (0®1®0
=start; 0®1® reset A/D converter)
ADCR register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
A0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
A1
A0
0
1
1
PB7
PB6
PB5
PB4
PB3
A2
A1
A0
1
0
0
PB7
PB6
PB5
PB4
A3
A2
A1
A0
1
0
1
PB7
PB6
PB5
A4
A3
A2
A1
A0
1
1
0
PB7
PB6
A5
A4
A3
A2
A1
A0
1
1
1
A7
A6
A5
A4
A3
A2
A1
A0
Port B configuration
Rev. 1.30
18
August 17, 2001
HT46R23
S T A R T
E O C
*7 6 T A D
*7 6 T A D
P C R 0 ~ P C R 2
0 0 0 B
1 0 0 B
1 0 0 B
0 0 0 B
A C S 0 ~ A C S 2
0 0 0 B
0 1 0 B
0 0 0 B
**X X X B
P o w e r
O n
R e s e t
1 : D
2 : S
***3
(E x
fS Y
N o te :
e fin
e le c
: S e
a m p
S /8 )
e P
t a
le c
le :
B c o n fig u
n a lo g c h a
t A D C c lo
4 c h a n n e
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
r a tio n
n n e l
c k
l, A N 2 ,
" * " A /D c o n v e r tin g tim e is 7 6 T A D
" * * " X X X B m e a n s d o n 't c a r e
" * * * " A D C c lo c k m u s t b e fS Y S /2 , fS
Y S
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e rte r
/8 , fS
Y S
1 : A ll P B lin e is d ig ita l in p u t
2 : A /D c o n v e r te r is p o w e r o ff
to r e d u c e p o w e r c o n s u m p tio n
E n d o f A /D
c o n v e rte r
/3 2
A/D conversion timing
Low voltage reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~3.3V, such as changing a battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
O P R
5 .5 V
V
The LVR includes the following specifications:
L V R
3 .3 V
· The low voltage (0.9V~3.3V) has to remain in their
3 .0 V
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0 .9 V
· The LVR uses the ²OR² function with the external RES
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
signal to perform chip reset.
V
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low voltage reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Rev. 1.30
19
August 17, 2001
HT46R23
I2C BUS Serial Interface
2
the next data byte, so the transmitter continue to write
data to the I2C BUS until the RXAK bit is set to ²1² and
the transmitter releases the SDA line, so that the master
can send the STOP signal to release the bus.
2
I C BUS is implemented in the device. The I C BUS is a
bidirectional two-wire lines. The data line and clock line
are implement in SDA pin and SCL pin. The SDA and
SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively.
The HADR bit7-bit1 define the device slave address. At
the beginning of transfer, the master must select a device by sending the address of the slave device. The bit
0 is unused and is not defined. If the I2C BUS receives a
start signal, all slave device notice the continuity of the
8-bit data. The front of 7 bits is slave address and the
first bit is MSB. If the address is match, the HAAS status
bit is set and generate an I2C BUS interrupt. In the ISR,
the slave device must check the HAAS bit to know the
I2C BUS interrupt comes from the slave address that
has match or completed one 8-bit data transfer. The last
bit of the 8-bit data is read/write command bit, it responds in SRW bit. The slave will check the SRW bit to
know if the master wants to transmit or receive data. The
device check SRW bit to know it is as a transmitter or receiver.
Using the I2C BUS, the device has two ways to transfer
data. One is in slave transmit mode, the other is in slave
receive mode. There are four registers related to I2C
BUS; HADR([20H]), HCR([21H]), HSR([22H]),
HDR([23H]). The HADR register is the slave address
setting of the device, if the master sends the calling address which match, it means that this device is selected.
The HCR is I2C BUS control register which defines the
device enable or disable the I2C BUS as a transmitter or
as a receiver. The HSR is I2C BUS status register, it responds with the I2C BUS status. The HDR is input/output data register, data to transmit or receive must be via
the HDR register.
The I2C BUS control register contains three bits. The
HEN bit define the enable or disable the I2C BUS. If the
data wants transfer via I2C BUS, this bit must be set.
The HTX bit defines whether the I2C BUS is in transmit
or receive mode. If the device is as a transmitter, this bit
must be set to ²1². The TXAK defines the transmit acknowledge signal, when the device received 8-bit data,
the device sends this bit to I2C BUS at the 9th clock. If
the receiver wants to continue to receive the next data,
this bit must be reset to ²0² before receiving data.
Bit0
Slave Address
¾
HADR register
Note: ²¾² means undefined
The HDR register is the I2C BUS input/output data register. Before transmitting data, the HDR must write the
data which we want to transmit. Before receiving data,
the device must dummy read data from HDR. Transmit
or Receive data from I2C BUS must be via the HDR register. At the beginning of the transfer of the I2C BUS, the
device must initial the bus, the following are the notes for
initialing the I2C BUS:
The I2C BUS status register contains 5 bits. The HCF bit
is reset to ²0² when one data byte is being transferred. If
one data transfer is completed, this bit is set to ²1². The
HASS bit is set ²1² when the address is match, and the
I2C BUS interrupt request flag is set to ²1². If the interrupt is enabled and the stack is not full, a subroutine call
to location 10H will occur. Writing data to the I2C BUS
control register clears HAAS bit. If the address is not
match, this bit is reset to ²0². The HBB bit is set to respond the I2C BUS is busy. It mean that a START signal
is detected. This bit is reset to ²0² when the I2C BUS is
not busy. It means that a STOP signal is detected and
the I2C BUS is free. The SRW bit defines the read/write
command bit, if the calling address is match. When
HAAS is set to ²1², the device check SRW bit to determine whether the device is working in transmit or receive mode. When SRW bit is set ²1², it means that the
master wants to read data from I2C BUS, the slave device must write data to I2C BUS, so the slave device is
working in transmit mode. When SRW is reset to ²0², it
means that the master wants to write data to I2C BUS,
the slave device must read data from the bus, so the
slave device is working in receive mode. The RXAK bit
is reset ²0² indicates an acknowledges signal has been
received. In the transmit mode, the transmitter checks
RXAK bit to know the receiver which wants to receive
Rev. 1.30
Bit7~Bit1
1: Write the I2C BUS address register (HADR) to define
its own slave address.
2: Set HEN bit of I2C BUS control register (HCR) bit 0 to
enable the I2C BUS.
Label
Bits
(HCR)
Function
HEN
7
To enable/disable I2C BUS function
(0= disable; 1= enable)
¾
6
Unused bit, read as ²0²
¾
5
Unused bit, read as ²0²
HTX
4
To define the transmit/receive mode
(0= receive mode; 1= transmit)
TXAK
3
To enable/disable transmit acknowledge
(0= acknowledge; 1= don¢t acknowledge)
¾
0~2 Unused bit, read as ²0²
HCR register
20
August 17, 2001
HT46R23
3: Set EHI bit of the interrupt control register 1 (INTC1)
bit 0 to enable the I2C BUS interrupt.
Label
Bits
(HSR)
Start signal
The START signal is generated only by the master device. The other device in the bus must detect the START
signal to set the I2C BUS busy bit (HBB). The START
signal is SDA line from high to low, when SCL is high.
Function
7
HCF is clear to ²0² when one data byte is
being transferred, HCF is set to ²1² indicating 8-bit data communication has
been finished.
HAAS
6
HAAS is set to ²1² when the calling addressed is matched, and I2C BUS interrupt will occur and HIF is set.
HBB
5
HBB is set to ²1² when I2C BUS is busy
and HBB is cleared to ²0² means that
the I2C BUS is not busy.
¾
4
Unused bit, read as ²0²
¾
3
Unused bit, read as ²0²
The master must select a device for transferring the
data by sending the slave device address after the
START signal. All device in the I2C BUS will receive the
I2C BUS slave address (7 bits) to compare with its own
slave address (7 bits). If the slave address is matched,
the slave device will generate an interrupt and save the
following bit (8th bit) to SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also
sets the status flag (HAAS), when the slave address is
matched.
SRW
2
SRW is set to ²1² when the master
wants to read data from the I2C BUS, so
the slave must transmit data to the master. SRW is cleared to ²0² when the
master wants to write data to the I2C
BUS, so the slave must receive data
from the master.
In interrupt subroutine, check HAAS bit to know whether
the I2C BUS interrupt comes from a slave address that is
matched or a data byte transfer is completed. When the
slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or
dummy read from HDR to release the SCL line.
¾
1
Unused bit, read as ²0²
0
RXAK is cleared to ²0² when the master
receives an 8-bit data and acknowledgment at the 9th clock, RXAK is set to ²1²
means not acknowledged.
HCF
RXAK
Slave address
SRW bit
The SRW bit means that the master device wants to
read from or write to the I2C BUS. The slave device
check this bit to understand itself if it is a transmitter or a
receiver. The SRW bit is set to ²1² means that the master wants to read data from the I2C BUS, so the slave de-
HSR register
S C L
S R W
S ta rt
1
S D A
0
1
1
0
1
0
A C K
1
D a ta
0
A C K
S to p
S C L
1
0
0
1
0
1
0
0
S D A
S = S
S A =
S R =
M = S
D = D
A = A
P = S
ta rt
S la
S R
la v
a ta
C K
to p
S
S A
( 1 b it)
v e A d d r
W b it ( 1
e d e v ic e
( 8 b its )
(R X A K
( 1 b it)
S R
M
e s s ( 7 b its )
b it)
s e n d a c lc n o w le d g e b it ( 1 b it)
b it fo r tr a n s m itte r ; T X A K
D
A
D
A
b it fo r r e c e iv e r 1 b it)
S
S A
S R
M
D
A
D
A
P
Slave address
Rev. 1.30
21
August 17, 2001
HT46R23
the 9th clock. The transmitter checks the acknowledge
bit (RXAK) to continue to write data to the I2C BUS or
change to receive mode and dummy read the HDR register to release the SDA line and the master sends the
STOP signal.
vice must write data to a bus as a transmitter. The SRW
is cleared to ²0² means that the master wants to write
data to the I2C BUS, so the slave device must read data
from the I2C BUS as a receiver.
Acknowledge bit
One of the slave device generates an acknowledge signal,
when the slave address is matched. The master device
can check this acknowledge bit to know if the slave device
accepts the calling address. If no acknowledge bit, the
master must send a STOP bit and end the communication.
When the I2C BUS status register bit 6 HAAS is high, it
means the address is matched, so the slave must check
SRW as a transmitter (set HTX) to ²1² or as a receiver
(clear HTX) to ²0².
S C L
S D A
Stop bit
S C L
Data byte
The data is 8 bits and is sent after the slave device has
acknowledges the slave address. The first bit is MSB
and the 8th bit is LSB. The receiver sends the acknowledge signal (²0²) and continues to receive the next one
byte data. If the transmitter checks and there¢s no acknowledge signal, then it release the SDA line, and the
master sends a STOP signal to release the I2C BUS.
The data is stored in the HDR register. The transmitter
must write data to the HDR before transmit data and the
receiver must read data from the HDR after receiving
data.
S D A
Start bit
S C L
S D A
S ta r t b it
Receive acknowledge bit
When the receiver wants to continue to receive the next
data byte, it generates an acknowledge bit (TXAK) at
Rev. 1.30
S to p b it
D a ta
s ta b le
D a ta
a llo w
c h a n g e
Data stable and data allow change
22
August 17, 2001
HT46R23
2
T h e I C
B U S in itia l p r o g r a m
flo w
c h a r t a s fo llo w s :
2
I C B U S In itia l S ta r t
W r ite S la v e
A d d re s s to
H A D R
S E T H E N
D is a b le
2
I C B U S
In te rru p t= ?
C L R E H I
P o llin g H IF to g o
to H -B U S IS R
E n a b le
S E T E H I
W a it In te r r u p t
G o to O th e r
G o to O th e r
Rev. 1.30
23
August 17, 2001
HT46R23
2
T h e I C B U S IS R p ro g ra m
flo w c h a r t a s fo llo w s :
IS R
N o
S ta rt
H A S S = 1
?
H T X = 1
?
Y e s
N o
S R W = 1
?
Y e s
R e a d F ro m
H D R
N o
Y e s
R E T I
S E T H T X
Y e s
C L R
C L R
H T X
T X A K
C L R
C L R
H T X
T X A K
R X A K = 1
?
N o
W r ite to H D R
D u m m y R e a d
F ro m H D R
R E T I
R E T I
W r ite to H D R
D u m m y R e a d
F ro m H D R
R E T I
Rev. 1.30
R E T I
24
August 17, 2001
HT46R23
ROM code option
The following shows ten kinds of ROM code option in the HT46R23. ALL the ROM code options must be defined to ensure proper system function.
No.
ROM Code Option
1
OSC type selection. This option is to decide if an RC or crystal oscillator is chosen as system clock.
2
WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable the
WDT.
3
CLRWDT times selection. This option defines how to clear the WDT by instruction. ²One time² means that the
CLR WDT instruction can clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared.
4
Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the
capability to wake-up the chip from a HALT.
5
Pull-high selection. This option is to decide whether a pull-high resistance is visible or not in the input mode of
the I/O ports. PA0~PA7, can be independently selected.
6
PFD selection:
PA3: level output or PFD output
7
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
8
WDT time-out period selection. There are four types of selection: WDT clock source divided by 212, 213, 214 and
215
9
Low voltage detector selection: Enable or disable LVD function.
10
I2C BUS selection:
PA6 and PA7: I/O or I2C BUS function
Rev. 1.30
25
August 17, 2001
HT46R23
Application Circuits
O S C 1
P A 0 ~ P A 2
O S C 2
P A 4 /T M R
O S C
C ir c u it
P A 3 /P F D
S e e b e lo w
P A 5 /IN T
5 V
V D D
1 0 0 k W
0 .1 m F
P A 6 /S D A
P A 7 /S C L
H T 4 6 R 2 3
R E S
P C 0 ~ P C 4
0 .1 m F
V S S
P B 0 /A N 0
P B 7 /A N 7
P D 0 /P W M 0
P D 1 /P W M 1
V
D D
O S C 1
R
O S C
fS
Y S /4
R C s y s te m o s c illa to r
3 0 k W < R O S C < 7 5 0 k W
O S C 2
O S C 1
C 1
C 2
O S C 2
C r y s ta l s y s te m o s c illa to r
C 1 = C 2 = 3 0 0 p F , if fS Y S < 1 M H z
O th e r w is e , C 1 = C 2 = 0
N o te : T h e r e s is ta n c e a n d c a p a c ita n c e fo r r e s e t c ir c u it s h o u ld b e d e s ig n e d
to e n s u r e th a t th e V D D is s ta b le a n d r e m a in s in a v a lid r a n g e o f th e
o p e r a tin g v o lta g e b e fo r e b r in g in g R E S to h ig h .
Rev. 1.30
26
August 17, 2001
HT46R23
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.30
27
August 17, 2001
HT46R23
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
None
TO,PD
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: 8 bits immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the register occurs, the execution cycle of instructions will be delayed by one more cycle
(four system clocks).
(2)
: If a skipping to next instruction occurs, the execution cycle of instructions will be delayed by one more cycle
(four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.30
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared.
Otherwise the TO and PD flags remain unchanged.
28
August 17, 2001
HT46R23
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator.
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory.
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator.
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator.
Description
The contents of the accumulator and the specified data are added, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory.
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
29
August 17, 2001
HT46R23
AND A,[m]
Logical AND accumulator with data memory.
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator.
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation. The
result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator.
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call.
Description
The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this
onto the stack. The indicated address is then loaded. Program execution continues with the
instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory.
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
30
August 17, 2001
HT46R23
CLR [m].i
Clear bit of data memory.
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer.
Description
The WDT and the WDT Prescaler are cleared (re-counting from 0). The power down bit (PD)
and time-out bit (TO) are cleared.
Operation
WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer.
Description
The TO, PD flags, WDT and the WDT Prescaler has cleared (re-counting from 0), if the other
preclear WDT instruction has been executed. Only execution of this instruction without the
other preclear instruction just sets the indicated flag which implies this instruction has been
executed and the TO and PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer.
Description
The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting from 0), if the other
preclear WDT instruction has been executed. Only execution of this instruction without the
other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory.
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which
previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
31
August 17, 2001
HT46R23
CPLA [m]
Complement data memory and place result in the accumulator.
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which
previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored
in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition.
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry
(AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment
is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or
C) is set; otherwise the original value remains unchanged. The result is stored in the data
memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory.
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator.
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator.
The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
32
August 17, 2001
HT46R23
HALT
Enter power down mode.
Description
This instruction stops program execution and turns off the system clock. The contents of the
RAM and registers are retained. The WDT and prescaler are cleared. The power down bit
(PD) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
TC2
¾
TC1
TO
PD
OV
Z
AC
C
¾
0
1
¾
¾
¾
¾
INC [m]
Increment data memory.
Description
Data in the specified data memory is incremented by 1.
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator.
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator.
The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump.
Description
Bits of the program counter are replaced with the directly-specified address unconditionally,
and control is passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator.
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
33
August 17, 2001
HT46R23
MOV A,x
Move immediate data to the accumulator.
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory.
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation.
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory.
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a
bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator.
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation. The
result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator.
Description
Data in the data memory (one of the data memory) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
34
August 17, 2001
HT46R23
RET
Return from subroutine.
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator.
Description
The program counter is restored from the stack and the accumulator loaded with the specified
8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt.
Description
The program counter is restored from the stack, and interrupts are enabled by setting the EMI
bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left.
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator.
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
35
August 17, 2001
HT46R23
RLC [m]
Rotate data memory left through carry.
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator.
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in
the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right.
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator.
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry.
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit right.
Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
36
August 17, 2001
HT46R23
RRCA [m]
Rotate right through carry and place result in the accumulator.
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the
carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator.
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator.
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0.
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction
(2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0.
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles).
Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
37
August 17, 2001
HT46R23
SET [m]
Set data memory.
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m].i
Set bit of data memory.
Description
Bit ²i² of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0.
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next
instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0.
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles).
Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit ²i² of the data memory is not 0.
Description
If bit ²i² of the specified data memory is not 0, the next instruction is skipped. If bit ²i² of the
data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
38
August 17, 2001
HT46R23
SUB A,[m]
Subtract data memory from the accumulator.
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator.
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator.
Description
The immediate data specified by the code is subtracted from the contents of the accumulator,
leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory.
Description
The low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator.
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing
the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
39
August 17, 2001
HT46R23
SZ [m]
Skip if data memory is 0.
Description
If the contents of the specified data memory are 0, the following instruction, fetched during the
current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0.
Description
The contents of the specified data memory are copied to the accumulator. If the contents is 0,
the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the
next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit ²i² of the data memory is 0.
Description
If bit ²i² of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction
(2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory.
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to
the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory.
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the
data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
40
August 17, 2001
HT46R23
XOR A,[m]
Logical XOR accumulator with data memory.
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator.
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator.
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.30
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
41
August 17, 2001
HT46R23
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
Holmate Technology Corp.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
Copyright Ó 2001 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.30
42
August 17, 2001