HOLTEK HTG13J0

HTG13J0
4-Bit Microcontroller
Features
·
·
·
·
·
·
·
·
·
·
·
·
·
Operating voltage: 2.4V~3.3V
Eight input lines
Three output lines
Five working registers
RC oscillator for system clock
8K´8 program ROM
160´4 data RAM
40´8 segment LCD driver, 1/5 bias, 1/8 duty
8-bit programmable timer with built-in frequency source
·
·
·
·
Internal timer overflow interrupt
16 kinds of programmable sound effect
One-level subroutine nesting
Halt function and wake up feature reduce
power consumption
Halt instruction
8-bit table read instruction
Up to 4.0msec instruction cycle
(1.0MHz system clock), at VDD=3V
96 powerful instructions
General Description
The HTG13J0 is a processor from Holtek s
4-bit stand alone single chip microcontroller
specially designed for LCD product applications. It is especially suited for applications re-
quiring low power consumption system with
many LCD segments, such as calculator, scale,
subsystem controller, hand-held LCD products
and electronic appliances.
1
May 19, 1999
HT13J0
Block Diagram
T im e r
S ta c k
A L U
O S C I
P A
O S C O
A C C
P C
P A 3
P P
P P 0
P P 1
P P 2
P P 3
P S
P S 0
P S 1
P S 2
P S 3
R E S
T E S T 1
T E S T 2
C o n tro l
a n d
T im in g
C ir c u it
R O M
R 0
T 1 D
R 1
In s tr u c tio n
D e c o d e r
V D D
P A 0
P A 1
P A 2
R 2
V S S
R 3
R 4
S o u n d
E ffe c t
B Z
B Z
T e m p o ra ry
D a ta R A M
D is p la y
D a ta
R A M
L C D
D r iv e r
C O M 7
C O M 1
C O M 0
S E G 3 9
S E G 3 8
S E G 2
S E G 1
S E G 0
Notes: ACC: Accumulator
PC: Program counter
R0~R4: Working registers
PA0~PA2: Output port
PP, PS: Input ports
PA3: ROM bank switch
2
May 19, 1999
HT13J0
Pad Assignment
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
BZ
1
BZ
2
VDD
OSCI
3
4
52
SEG18
51
SEG19
50
SEG20
49
SEG21
48
SEG22
47
SEG23
SEG24
OSCO
5
46
T512
6
45
SEG25
COM7
COM6
7
44
SEG26
43
SEG27
COM5
9
COM4
10
42
SEG28
COM3
11
41
SEG29
COM2
12
40
SEG30
COM1
13
39
SEG31
COM0
14
38
SEG32
TEST1
15
37
SEG33
TEST2
16
36
SEG34
PS2
17
PS1
18
35
SEG35
34
SEG36
PS0
8
19
SEG37
PA0
SEG39
PA1
Chip size: 2746 ´ 3552 (mm)
SEG38
PA2
26 27 28 29 30 31 32 33
PP3
25
RES
24
PP1
23
PP2
22
PP0
21
PS3
20
T1D
VSS
(0,0)
2
* The IC substrate should be connected to VSS in the PCB layout artwork.
3
May 19, 1999
HT13J0
Unit: mm
Pad Coordinates
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
-1244.25
-1244.25
-1203.75
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1244.25
-1206.45
-923.85
-671.40
-469.35
-217.35
22.95
232.20
371.70
511.20
650.70
790.20
929.70
1069.20
1208.70
1244.25
1244.25
1523.47
1256.62
1017.25
861.97
353.02
227.02
101.03
-24.98
-150.98
-276.98
-402.98
-528.97
-654.97
-780.97
-906.97
-1032.97
-1158.97
-1284.97
-1410.97
-1617.53
-1556.78
-1568.47
-1556.78
-1556.78
-1556.78
-1617.53
-1617.53
-1617.53
-1617.53
-1617.53
-1617.53
-1617.53
-1617.53
-1361.03
-1224.67
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1244.25
1228.95
1084.95
954.45
823.95
693.45
562.95
432.45
301.95
171.45
40.95
-89.55
-220.05
-350.55
-481.05
-611.55
-742.05
-872.55
-1003.05
-1080.67
-936.67
-792.67
-648.67
-504.67
-360.67
-216.68
-72.68
71.32
215.32
359.33
503.33
729.22
882.22
1035.22
1188.22
1341.22
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
1617.53
4
May 19, 1999
HT13J0
Pad Description
Pad No.
Pad name
I/O
Mask Option
Description
1
2
BZ
BZ
O
*
Sound effect output
3
VDD
I
¾
Positive power supply
4
5
OSCI
OSCO
I
O
¾
OSCI, OSCO are connected to resistor for internal system clock.
6
15
16
21
T512
TEST1
TEST2
T1D
O
I
I
O
¾
For test mode only
TEST1 and TEST2 must be open when the
chip is in normal operation (with internal pull
high resistor).
7~14
COM7~COM0
O
¾
Output for LCD panel common plate
17~19
22
PS2~PS0
PS3
I
Pull-high or
None
**
20
VSS
I
¾
Negative power supply, GND
23~25
PA2~PA0
O
CMOS or
NMOS
Open Drain
3-bit latch port for output only
26~29
PP0~PP3
I
Pull-high or
None
**
4-bit port for input only
30
RES
I
¾
Input to reset LSI
Reset is active at logical low level.
31~70
SEG39~SEG0
O
¾
LCD driver outputs for LCD panel segment
4-bit port for input only
*:
6 internal sources deriving from system clock can be selected as sound effect clock by mask option. If Holtek s sound library is invoked, only 128K and 64K is accepted.
**:
Each bit of input ports PS, PP can be a trigger source of HALT interrupt. That can be specified
by mask option.
Absolute Maximum Ratings
Supply Voltage .............................-0.3V to 5.5V
Storage Temperature ................-50°C to 125°C
Input Voltage ................VSS-0.3V to VDD+0.3V
Operating Temperature ..................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
5
May 19, 1999
HT13J0
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
VDD
Operating Voltage
¾
¾
2.4
¾
3.3
V
IDD
Operating Current
3V
No load, fSYS=500kHz
¾
200
500
mA
ISTB
Standby Current
3V
System halt
¾
¾
1
mA
VIL1
Input Low Voltage PS, PP
3V
¾
0
¾
0.6
V
VIH1
Input High Voltage PS, PP
3V
¾
2.1
¾
3.0
V
VIL2
Input Low Voltage RES
3V
¾
0
¾
0.6
V
VIH2
Input High Voltage RES
3V
¾
2.6
¾
3.0
V
IOL1
Port A, BZ and BZ
Output Sink Current
3V
VDD=3V, VOL=0.3V
1.5
3.0
¾
mA
IOH1
Port A, BZ and BZ
Output Source Current
3V
VDD=3V, VOH=2.7V
-0.8
-1.5
¾
mA
IOL2
Segment 0~7 Output
Sink Current
3V
VLCD=3V, VOL=0.3V
80
130
¾
mA
IOH2
Segment 0~7 Output
Source Current
3V
VLCD=3V, VOH=2.7V
-50
-90
¾
mA
IOL3
Segment 8~39 Output
Sink Current
3V
VLCD=3V, VOL=0.3V
40
80
¾
mA
IOH3
Segment 8~39 Output
Source Current
3V
VLCD=3V, VOH=2.7V
-30
-60
¾
mA
IOL4
Common Sink Current
3V
VLCD=3V, VOL=0.3V
60
120
¾
mA
IOH4
Common Source Current
3V
VLCD=3V, VOH=2.7V
-60
-120
¾
mA
RPH
Pull-high Resistance
3V
PS, PP, RES
50
¾
300
kW
6
May 19, 1999
HT13J0
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock
3V
R:680kW~5kW
32
¾
1000
kHz
fLCD
LCD Clock
3V
¾
¾
512*
¾
Hz
tCOM
LCD Common Period
¾
1/8 duty
¾
(1/fLCD)´8
¾
Sec
tCY
Cycle Time
¾
fSYS=1.0MHz
¾
4.0
¾
ms
tRES
Reset Pulse Width
¾
¾
5
¾
¾
ms
fSOUND
Sound Effect Clock
¾
¾
¾
64 or 128
**
¾
kHz
*: In general, fLCD is selected and optimized by Holtek according to fSYS and operating voltage.
**: Only these two clock signal frequencies are supported by the Holtek sound library.
7
May 19, 1999
HT13J0
Functional Description
After accessing a memory word to fetch an instruction code, the contents of the program
counter are incremented by 1 or 2, then the program counter will point to the memory word
containing the next instruction code.
Program counter - PC
The bit 13 of program memory is controlled by
PA3 which can change the address of the program. There are two banks of the program
memory, which are selected by PA3, every bank
is 4KB ROM. The instruction "UT PA,A" is used
to change the value of PA3. Then, low or high
4K ROM is selected accordingly. All instructions are not effective on crossing bank, unless
the value of PA3 is changed in advance.
When executing the jump instruction (JMP,
JNZ, JC,JTMR...), subroutine call, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program
transfer by loading the address corresponding
to each instruction.
The 12-bit program counter (PC) controls the
sequence in which the instructions stored in
program ROM are executed and its contents
specify a maximum of 4096 addresses.
Program Counter
Mode
PA3 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3
Initial
reset
PC2
PC1
PC0
1
0
0
0
0
0
0
0
0
0
0
0
0
Internal
interrupt
PA3
0
0
0
0
0
0
0
0
0
1
0
0
External
interrupt
PA3
0
0
0
0
0
0
0
0
1
0
0
0
Jump, call
instruction
PA3 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3
PC2
PC1
PC0
Conditional
branch
PA3
PC2
PC1
PC0
S2
S1
S0
Return from
PA3
subroutine
@
S11
PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3
S10
S9
S8
S7
S6
S5
S4
S3
Program counter
Notes: PC11~PC0: Instruction code bits
S11~S0: Stack register bits
@: PC11 keeps the current value
PA3: Bank value bits
8
May 19, 1999
HT13J0
· Location 1008H
Program memory - ROM
Activating the PS or PP input pins of the processor with the interrupts enabled during
HALT mode causes the program to jump to
this location.
The program memory is used to store program
instruction which is to be executed. It is organized with 8192 ´ 8 bits and addressed by the
program counter and PA3.
· Location 1n00H~1nFFH (n=current number)
Certain locations in bank 0 of the program
memory are reserved for specific usage:
and 1F00H~1FFFH.
The last 256 bytes of each page in the program memory, addressed from 1n00H to
1nFFH and 1F00H to 1FFFH can be used as a
loop up table. The instructions READ R4A,
READ MR0A, READF R4A, READF MR0A
can read the table and transfer the contents of
the table to ACC and R4 or transfer to ACC
and data memory addressed by register pair
"R1,R0" These area may function as normal
program memory depending on the requirement. Note that the page number n must be
greater than zero, some locations in page 1
are reserved for specific usage as mentioned.
· Location 0004H
This area are reserved for TIMER interrupt
service program. A timer interrupt resulting
from TIMER overflow, if interrupt is enabled
the CPU begins execution at location 0004H.
· Location 0008H
Activating the PS or PP input pins of the processor with the interrupts enabled during
HALT mode causes the program to jump to
this location.
· Location 0n00H~0nFFH (n=current number)
and 0F00H~0FFFH.
The last 256 bytes of each page in the program memory, addressed from 0n00H to
0nFFH and 0F00H to 0FFFH can be used as a
look up table. The instructions READ R4A,
READ MR0A, READF R4A, READF MR0A
can read the table and transfer the contents of
the table to ACC and R4 or transfer to ACC
and data memory addressed by register pair
R1,R0 . These area may function as normal
program memory depending on the requirement. Note that the page number n must be
greater than zero, some locations in page 0
are reserved for specific usage as mentioned.
The program memory (ROM) mapping is shown
below:
0000H
0003H
0004H
Timer interrupt subroutine of bank 0
0007H
0008H
External interrupt subroutine of bank 0
000BH
Page n look-up table (256 bytes) of bank 0
0F00H
0FFFH
1000H
Page F look-up table (256 bytes) of bank 0
Program ROM
Reset initial program
1003H
1004H
Timer interrupt subroutine of bank 1
Certain locations in bank 1 of the program
memory are reserved for specific usage:
1007H
1008H
External interrupt subroutine of bank 1
100BH
· Location 1000H
Page look-up table (256 bytes) of bank 1
This area are reserved for the initialization
program. After reset, the CPU always begins
execution at location 1000H.
1F00H
Page F look-up table (256 bytes) of bank 1
1FFFH
8 bits
· Location 1004H
This area is reserved for TIMER interrupt
service program. A timer interrupt resulting
from TIMER overflow, if interrupt is enabled,
the CPU begins execution at location 1004H.
Program memory
9
May 19, 1999
HT13J0
In the execution of an instruction, the program
counter is added before the executing phase. So
a careful manipulation of READ MR0A and
READ R4A is needed in the page margin.
00H
Temporary Data Area
(160 x 4)
A0H
Undefined Area
Stack register
Data RAM
B0H
The stack register is a group of registers used to
save the contents of the program counter (PC)
and is arranged in 13 bits ´ 1 level. One bit is
used to store the carry flag. An interrupt will
force the contents of the PC and the carry flag
onto the stack register. A subroutine call will
also cause the PC contents to be pushed onto
the stack; however the carry flag will not be
stored. At the end of a subroutine or an interrupt (indicated by a return instruction RET or
RETI), the contents of the stack register are returned to the PC.
FFH
Display Data Area
(80 x 4)
4 bits
Data memory
When data is written in the display area, the
LCD driver automatically reads it and
gene-rates an LCD driving signal.
Accumulator - ACC
The register ACC plays the most important role
in data manipulation and data transfer. It is
not only one of the sources of input to the ALU
but also the destination of the result due to
ALU. Data transfer can be performed between
ACC and other registers, data memory or I/O
ports.
Executing "RETI" instruction will restore the
carry flag from the stack register, but "RET"
does not.
Working registers - R0,R1,R2,R3,R4
These five registers are usually used to store
the frequently accessed data. The working register can be incremented (+1) or decremented
(-1). The JNZ Rn, address (n=0,1,4) instruction
makes efficient use of the working register as a
program loop counter. Also the register pairs of
R1, R0 and R3, R2 can be used as the data memory pointer, when the data memory transfer instruction is executed.
Arithmetic and logic unit - ALU
This circuit performs arithmetic and logic operation. The ALU provides the following functions:
Arithmetic operation (ADD, ADC, SUB, SBC,
DAA)
Data memory - RAM
· Logic operation (AND, OR, XOR)
The data memory is a static RAM organized
with 256 ´ 4 bit format and is used to store temporary data and display data. All of the data
memory locations are indirectly addressable through
the register pair "R1,R0" or "R3,R2".
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (JZ, JNZ, JC, JNC...)
· The ALU not only outputs the results of data
There are two areas in the data memory, temporary data area and display data area. Access to
the temporary data memory is made through
00H-9FH address, and access to the display
data memory is made through B0H-FFH address.
operation but also sets the status of carry flag
(C) in some instructions.
Timer
This is a programmable 8-bit count-up counter
internal frequency sources to aid the user in
counting and generate accurate time base.
The locations between the temporary and display
data areas are undefined and cannot be used.
10
May 19, 1999
HT13J0
The Timer is presettable and readable with
software instructions. "TIMER XXH", "MOV
TMRL,A" and "MOV TMRH,A" preload TIMER
value. "MOV A,TMRL" and "MOV A,TMRH"
read the contents of the TIMER to ACC.
If within a CALL subroutine, an interrupt occurs, the interrupt will be serviced after leaving
the CALL subroutine.
The interrupts are disabled by a hardware reset or a DI instruction. They remain disabled
until the EI instruction is executed.
The Timer is stopped by a hardware reset or
"TIMER OFF" instruction and started by a
TIMER ON instruction.
Each input port pin can be programmed by
mask option to have an external interrupt function in the HALT mode.
Once the Timer is started, it will increment to its
maximum count (FFH) and overflow to zero
(00H) and will not stop until there is a TIMER
OFF instruction or reset. When an overflow occurs, it will set the Timer Flag (TF) simultaneously. If interrupt is enabled, the Timer circuit
supports TF for internal interrupt. The state of
the TF is also testable with conditional instruction JTMR.
Initial reset
The HTG13J0 provide a RES pin for system initialization. Since the RES pin has internal pull
high resistor, only an external 0.1m~1m capacitor
is needed. If the reset pulse is generated externally, it must be held low for at least 5 ms.
When RES is active, the internal block will be
initialized as follows:
The Timer flag is cleared after the interrupt or
JTMR instruction is executed.
The frequency of internal frequency source can
be selected by mask option.
m
=
2n
Where n=0, 1, 2......13 except 6, by mask option
(the sixth stage is reserved for internal use).
PA3 and PC
1000H
TIMER
Stop
Timer flag
Reset (low)
SOUND
Sound off and One sing mode
Output Port A high (or floating state)
Interrupt
The HTG13J0 provide both internal and external interrupt modes. The DI and EI instructions are used to disable and enable the
interrupts. During halt mode, if the PP or PS
input pin is triggered on a high to low transition
in the enable interrupt mode and the program
is not within a CALL subroutine the external
interrupt is activated. This causes a subroutine
call to location 8 and resets the interrupt latch.
Interrupt
Disabled
BZ and BZ
output
High level
Halt
This is a special feature of HTG13J0. It will stop
the chip s normal operation and reduce power
consumption. When the instruction HALT is
executed, then either of the following will occur:
· The system clock will be stopped
Likewise when the timer flag is set in the enable interrupt mode and the program is not
within a CALL subroutine, the internal interrupt is activated. This causes a subroutine call
to location 4 and resets the timer flag.
· The contents of the on-chip RAM and regis-
When running under a CALL subroutine or DI,
the interrupt acknowledge is on hold until the
RET or EI instruction is invoked. The CALL instruction should not be used within an interrupt routine as unpredictable result may occur.
The system can leave the HALT mode by ways
of initial reset or external interrupt and
wake-up from the following entry of the program counter value.
ters remain unchanged
· LCD segments and commons keep VDD volt-
age (i.e. LCD becomes blank)
11
May 19, 1999
HT13J0
The following figure shows the mapping between display memory and LCD pattern.
Initial reset: 1000H.
Interrupt (enabled): 1008H or 0008H.
Interrupt (disabled): next address of HALT instruction.
DISPLAY MEMORY
FEH
In HALT mode, each bit of ports PP, PS, can be
used as external interrupt by mask option to
wake-up the system. This signal is active in
low-going transition.
Sound effect
FCH FAH F8H
B4
B2
B0
COM
BIT
0
0
1
1
2
2
3
3
HTG13J0 provides sound effect circuit which
offers up to 16 sounds with 3 effects of tone,
boom and noise. Holtek supports a sound library which have melody, alarm, machine gun
shooting, etc. That can meet various requirements.
FFH
Whenever the instruction "SOUND n" or
"SOUND A" is executed, the specified sound begin playing. Whenever "SOUND OFF" is executed, it terminates the singing sound
immediately.
FDH FBH F9H
B5
B3
B1
4
0
5
1
6
2
7
3
SEGMENT
0
1
2
3
37
38
39
There are two singing mode, SONE mode and
SLOOP mode, this is activated by "SOUND
ONE" and "SOUND LOOP". In SONE mode,
the sound that has been specified plays just
once. In SLOOP mode, the sound being specified keeps playing repeatedly.
To turn on/off the display, the programmer just
writes 1/0 to the corresponding bit of the display memory.
Since sound 0~11 contain 32 notes, sound
12~15 contain 64 notes, the later possess better
sound than the former.
The LCD display module may have any form as
long as the number commons is no more than 8
and the segment is no more than 40.
The frequency of sound effect circuit can be selected by mask option.
m
=
2m
Where m=0, 1, 2, 3, 4, 5
LCD driver output
LCD display memory
The output number of the LCD driver is 40 ´ 8.
That can directly drive an LCD with 1/8 duty
cycle and 1/5 bias. All LCD segments are random at the initial clear mode.
The bias voltage circuit of the LCD display is
built-in. No external resistor is needed.
The Holtek s sound library only supports
sound clock frequency 128K or 64K. If it is desired to utilize Holtek s sound library, proper
system clock and mask option should be selected.
The LCD driving clock frequency shall be fixed
in 512Hz. That can not be selected by the user,
and Holtek will set it according to the application.
LCD display memory
As mentioned in the data memory section, the
LCD display memory is embedded in the data
memory. It can be read and written to as normal data memory.
12
May 19, 1999
HT13J0
An example of an LCD driving waveform (1/8
duty and 1/5 bias) is shown below.
VDD
64Hz
1
2
3
4
5
6
7
8
1
2
3
4
internal bus
5
512Hz
VDD
4/5 VDD
COM0 3/5 VDD
2/5 VDD
1/5 VDD
GND
D
Q
CK
Q
mask option
VDD
4/5 VDD
COM1 3/5 VDD
2/5 VDD
1/5 VDD
GND
SEG0
Output port - PA0~PA2
VDD
4/5 VDD
3/5 VDD
2/5 VDD
1/5 VDD
GND
Output port PA0~PA2
A mask option is available to select whether the
output is a CMOS or open drain NMOS type.
After an initial clear, the output port PA defaults high for CMOS or floating for NMOS.
Oscillator circuit
Only one external resistor is needed for HTG13J0
oscillator circuit.
Note:
PA3 controls bit 13 of the program memory. Be
careful about PA3. When instruction "OUT PA,A"
is operated, port A is changed as well.
The system clock is also used as the reference signal of LCD driving clock, sound effect clock, and
internal TIMER frequency source.
One HTG13J0 machine cycle consists of a sequence of 4 states numbered T1 to T4. Each state
lasts for one oscillator period. The machine cycle
is 4ms, if the system frequency is up to 1.0MHz.
Mask option
Input ports PS, PP
· Each bit of input ports PS, PP with or without
The following options are available by mask option which must be selected prior to manufacturing.
pull-high resistor.
All ports can have internal pull high resistors
· Each bit of input ports PS, PP function as
VDD
HALT interrupt trigger.
· Each bit of output port PA0~PA2 with CMOS
wake-up
pull-high
mask
option
wake-up
mask
option
read control
or open drain NMOS.
· 8 bit programmable TIMER with internal fre-
quency sources. There are 13 (the sixth stage
is reserved for internal use) internal frequency sources which can be selected as
clocking signal.
internal bus
-
· Six kinds of sound clock frequency:
determined by mask option. Every bit of the input ports PP and PS can be specified to be a
trigger source to wake up the HALT interrupt
by mask option. A high to low transition on one
of these pins will wake up the device from a
HALT status.
m
fSYS/2 , m=0, 1, 2, 3, 4, 5
13
May 19, 1999
HT13J0
Application Circuits
C O M 0
P A 0
P A 1
P A 2
C O M 1
O U T P U T
P O R T
L C D
C O M 7
P a tte rn
(1 /5
P P 0
P P 1
P P 2
S E G M E N T
O U T P U T
B ia s , 1 /8 D u ty )
X 4 0
IN P U T
P O R T
P P 3
H T G 1 3 J 0
P S 0
B Z
P S 1
P S 2
P S 3
IN P U T
P O R T
B Z
R *
O S C I
O S C O
R E S
0 . 1 µF ~ 1 µF
R*: depends on the required system clock frequency (R=680kW~5kW, at VDD=3V)
14
May 19, 1999
HT13J0
Instruction Set Summary
Mnemonic
Description
Byte Cycle CF
Arithmetic
ADD A,[R1R0]
ADC A,[R1R0]
SUB A,[R1R0]
SBC A,[R1R0]
ADD A,XH
SUB A,XH
DAA
Add data memory to ACC
Add data memory with carry to ACC
Subtract data memory from ACC
Subtract data memory from ACC with borrow
Add immediate data to ACC
Subtract immediate data from ACC
Decimal adjust ACC for addition
1
1
1
1
2
2
1
1
1
1
1
2
2
1
Ö
Ö
Ö
Ö
Ö
Ö
Ö
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
Increment ACC
Increment register
Increment data memory
Increment data memory
Decrement ACC
Decrement register
Decrement data memory
Decrement data memory
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
¾
¾
¾
¾
¾
¾
¾
¾
Move register to ACC
Move ACC to register
Move data memory to ACC
Move data memory to ACC
Move ACC to data memory
Move ACC to data memory
Move immediate data to ACC
Move immediate data to R1 and R0
Move immediate data to R3 and R2
Move immediate data to R4
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
2
2
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Logic Operation
AND A,[R1R0]
OR A,[R1R0]
XOR A,[R1R0]
AND [R1R0],A
OR [R1R0],A
XOR [R1R0],A
AND A,XH
OR A,XH
XOR A,XH
Increment and
Decrement
INC A
INC Rn
INC [R1R0]
INC [R3R2]
DEC A
DEC Rn
DEC [R1R0]
DEC [R3R2]
Data Move
MOV A,Rn
MOV Rn,A
MOV A,[R1R0]
MOV A,[R3R2]
MOV [R1R0],A
MOV [R3R2],A
MOV A,XH
MOV R1R0,XXH
MOV R3R2,XXH
MOV R4,XH
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May 19, 1999
HT13J0
Mnemonic
Description
Byte Cycle CF
Rotate
RL A
RLC A
RR A
RRC A
Rotate ACC left
Rotate ACC left through the carry
Rotate ACC right
Rotate ACC right through the carry
1
1
1
1
1
1
1
1
Ö
Ö
Ö
Ö
Input port-i to ACC, port-i=PS,PP
Output ACC to port-A
1
1
1
1
¾
¾
Jump unconditional
Jump on carry=1
Jump on carry=0
Jump on timer out
Jump on ACC bit n=1, n=0,1,2,3
Jump on ACC is zero
Jump on ACC is not zero
Jump on register Rn not zero, n=0,1,4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
¾
¾
¾
¾
¾
¾
¾
¾
Subroutine call
Return from subroutine or interrupt
Return from interrupt service routine
2
1
1
2
1
1
¾
¾
Ö
Clear carry flag
Set carry flag
Enable interrupt
Disable interrupt
No operation
1
1
1
1
1
1
1
1
1
1
0
1
¾
¾
¾
Set 8 bits immediate data to TIMER
Set TIMER start counting
Set TIMER stop counting
Move low nibble of TIMER to ACC
Move high nibble of TIMER to ACC
Move ACC to low nibble of TIMER
Move ACC to high nibble of TIMER
2
1
1
1
1
1
1
2
1
1
1
1
1
1
¾
¾
¾
¾
¾
¾
¾
Input and Output
IN A,Pi
OUT PA,A
Branch
JMP addr
JC addr
JNC addr
JTMR addr
JAn addr
JZ A,addr
JNZ A,addr
JNZ Rn,addr
Subroutine
CALL addr
RET
RETI
Flag
CLC
STC
EI
DI
NOP
Timer
TIMER XXH
TIMER ON
TIMER OFF
MOV A,TMRL
MOV A,TMRH
MOV TMRL,A
MOV TMRH,A
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May 19, 1999
HT13J0
Mnemonic
Description
Byte Cycle CF
Table Read
READ R4A
READ MR0A
READF R4A
READF MR0A
Read ROM code of current page to R4 and ACC
Read ROM code of current page to M(R1,R0),ACC
Read ROM code of page F to R4 and ACC
Read ROM code of page F to M(R1,R0),ACC
1
1
1
1
2
2
2
2
¾
¾
¾
¾
Active SOUND channel n
Active SOUND channel with Accumulator
Turn on SOUND one mode
Turn on SOUND repeat mode
Turn off SOUND
2
1
1
1
1
2
1
1
1
1
¾
¾
¾
¾
¾
Enter power down mode
2
2
¾
Sound Control
SOUND n
SOUND A
SOUND ONE
SOUND LOOP
SOUND OFF
Miscellaneous
HALT
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May 19, 1999
HT13J0
Instruction Definitions
ADC A,[R1R0]
Add data memory contents and carry to accumulator
Machine Code
00001000
Description
The contents of the data memory addressed by the register pair "R1,R0"
and carry are added to the accumulator. Carry is affected.
Operation
ACC ¬ ACC+M(R1,R0)+C
ADD A,XH
Add immediate data to accumulator
Machine Code
01000000
Description
The specified data is added to the accumulator. Carry is affected.
Operation
ACC ¬ ACC+XH
ADD A,[R1R0]
Add data memory contents to accumulator
0000dddd
Machine Code
00001001
Description
The contents of the data memory addressed by the register pair R1,R0"
is added to the accumulator. Carry is affected.
Operation
ACC ¬ ACC+M(R1,R0)
AND A,XH
Logical AND immediate data to accumulator
Machine Code
01000010
Description
Data in the accumulator is logical AND with the immediate data specified by code.
Operation
ACC ¬ ACC "AND" XH
AND A,[R1R0]
Logical AND accumulator with data memory
0000dddd
Machine Code
00011010
Description
Data in the accumulator is logical AND with the data memory addressed
by the register pair "R1,R0".
Operation
ACC ¬ ACC "AND" M(R1,R0)
AND [R1R0],A
Logical AND data memory with accumulator
Machine Code
00011101
Description
Data in the data memory addressed by the register pair "R1,R0" is logical
AND with the accumulator
Operation
M(R1,R0) ¬ M(R1,R0) "AND" ACC
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HT13J0
CALL address
Subroutine call
Machine Code
1111aaaa
Description
The program counter bits 0 1 1 are saved in the stack. The program counter is then loaded from the directly-specified address.
Operation
Stack ¬ PC+2
PC ¬ address
CLC
Clear carry flag
Machine Code
00101010
Description
The carry flag is reset to 0
Operation
C¬0
DAA
Decimal Adjust accumulator
aaaaaaaa
Machine Code
00110110
Description
The accumulator value is adjusted to the BCD (Binary Code Decimal)
code, if the contents of the accumulator is greater than 9 or C (Carry flag)
is 1.
Operation
If ACC>9 or CF=1 then
ACC ¬ ACC+6, C ¬ 1
else
ACC ¬ ACC, C ¬ C
DEC A
Decrement accumulator
Machine Code
00111111
Description
Data in the accumulator is decremented by 1. Carry flag is not affected.
Operation
ACC ¬ ACC 1
DEC Rn
Decrement register
Machine Code
0001nnn1
Description
Data in the working register "Rn" is decremented by 1. Carry flag is not
affected.
Operation
Rn ¬ Rn 1; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4
DEC [R1R0]
Decrement data memory
Machine Code
00001101
Description
Data in the data memory specified by the register pair "R1,R0" is decremented by 1. Carry flag is not affected.
Operation
M(R1,R0) ¬ M(R1,R0) 1
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HT13J0
DEC [R3R2]
Decrement data memory
Machine Code
00001111
Description
Data in the data memory specified by the register pair "R3,R2" is decremented by 1. Carry flag is not affected.
Operation
M(R3,R2) ¬ M(R3,R2)-1
DI
Disable interrupt
Machine Code
00101101
Description
Internal time-out interrupt and external interrupt are disabled.
EI
Enable interrupt
Machine Code
00101100
Description
Internal time-out interrupt and external interrupt are enabled.
HALT
Halt system clock
Machine Code
00110111
Description
Turn off system clock, and enter power down mode.
Operation
PC ¬ (PC)+1
00111110
IN A,Pi
Input port to accumulator
Machine Code
0 0 1 1 0 0 1 1 PS
0 0 1 1 0 1 0 0 PP
Description
The data on port "Pi" is transferred to the accumulator.
Operation
ACC ¬ Pi; Pi=PS or PP
INC A
Increment accumulator
Machine Code
00110001
Description
Data in the accumulator is incremented by 1. Carry flag is not affected.
Operation
ACC ¬ ACC+1
INC Rn
Increment register
Machine Code
0001nnn0
Description
Data in the working register "Rn" is incremented by 1. Carry flag is not
affected.
Operation
Rn ¬ Rn+1; Rn=R0, R1, R2, R3, R4 for n=0, 1, 2, 3, 4
INC [R1R0]
Increment data memory
Machine Code
00001100
Description
Data in the data memory specified by the register pair "R1,R0" is incremented by 1. Carry flag is not affected.
Operation
M(R1,R0) ¬ M(R1,R0)+1
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HT13J0
INC [R3R2]
Increment data memory
Machine Code
00001110
Description
Data memory specified by the register pair "R3,R2" is incremented by 1.
Carry flag is not affected.
Operation
M(R3,R2) ¬ M(R3,R2)+1
JAn address
Jump if accumulator Bit n is set
Machine Code
100nnaaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address, bit 11 of the program counter and PA3 of the memory bank remain, if accumulator bit n is set to 1.
Operation
PC (bit 0~10) ¬ address, if ACC bit n=1 (n=0,1,2,3,)
PC ¬ PC+2, if ACC bit n=0
aaaaaaaa
JC address
Jump if carry is set
Machine Code
11000aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address, bit 11 of the program counter and PA3 of the memory bank remain, if C (Carry flag) is set to 1.
Operation
PC (bit 0~10) ¬ address, if C=1
PC ¬ PC+2, if C=0
JMP address
Direct Jump
Machine Code
1110aaaa
Description
Bits 0~11 of the program counter are replaced with the directly-specified
address.
Operation
PC ¬ address
JNC address
Jump if carry is not set
Machine Code
11001aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address, bit 11 of the program counter and PA3 of the memory bank remain, if C (Carry flag) is set to 0.
Operation
PC (bit 0~10) ¬ address, if C=0
PC ¬ PC+2, if C=1
aaaaaaaa
aaaaaaaa
aaaaaaaa
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HT13J0
JNZ A,address
Jump if accumulator is not 0
Machine Code
10111aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is not 0.
Operation
PC (bit 0~10) ¬ address, if ACC¹0
PC ¬ PC+2, if ACC=0
aaaaaaaa
JNZ Rn,address
Jump if register is not 0
Machine Code
10100aaa
10101aaa
11011aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address, bit 11 of the program counter and PA3 of the memory bank remain, if the register is not 0.
Operation
PC (bit 0~10) ¬ address, if Rn¹0; Rn=R0,R1,R4
PC ¬ PC+2, if Rn=0
a a a a a a a a R0
a a a a a a a a R1
a a a a a a a a R4
JTMR address
Jump if time-out
Machine Code
11010aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address, bit 11 of the program counter and PA3 of the memory bank remain, if the TF (Timer flag) is set to 1.
Operation
PC (bit 0~10) ¬ address, if TF=1
PC ¬ PC+2, if TF=0
JZ A,address
Jump if accumulator is 0
Machine Code
10110aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is 0.
Operation
PC (bit 0~10) ¬ address, if ACC=0
PC ¬ PC+2, if ACC¹0
MOV A,Rn
Move register to accumulator
Machine Code
0010nnn1
Description
Data in the working register "Rn" is moved to the accumulator.
Operation
ACC ¬ Rn; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4
MOV A,TMRH
Move timer to accumulator
aaaaaaaa
aaaaaaaa
Machine Code
00111011
Description
The high nibble data of Timer counter is loaded to the accumulator.
Operation
ACC ¬ TIMER (high nibble)
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HT13J0
MOV A,TMRL
Move timer to accumulator
Machine Code
00111010
Description
The low nibble data of Timer counter is loaded to the accumulator.
Operation
ACC ¬ TIMER (low nibble)
MOV A,XH
Move immediate data to accumulator
Machine Code
0111dddd
Description
The 4-bit data specified by code is loaded to the accumulator.
Operation
ACC ¬ XH
MOV A,[R1R0]
Move data memory to accumulator
Machine Code
00000100
Description
Data in the data memory specified by the register pair "R1,R0" is moved
to the accumulator.
Operation
ACC ¬ M(R1,R0)
MOV A,[R3R2]
Move data memory to accumulator
Machine Code
00000110
Description
Data in the data memory specified by the register pair "R3,R2" is moved
to the accumulator.
Operation
ACC ¬ M(R3,R2)
MOV R1R0,XXH
Move immediate data to R1 and R0
Machine Code
0101dddd
Description
The 8-bit data specified by code are loaded to the working registers R1
and R0, the high nibble of the data is loaded to R1, and the low nibble of
the data is loaded to R0.
Operation
R1 ¬ XH (high nibble)
R0 ¬ XH (low nibble)
MOV R3R2,XXH
Move immediate data to R3 and R2
Machine Code
0110dddd
Description
The 8-bit data specified by code are loaded to the working register R3 and
R2, the high nibble of the data is loaded to R3, and the low nibble of the
data is loaded to R2.
Operation
R3 ¬ XH (high nibble)
R2 ¬ XH (low nibble)
0000dddd
0000dddd
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May 19, 1999
HT13J0
MOV R4,XH
Move immediate data to R4
Machine Code
01000110
Description
The 4-bit data specified by code are loaded to the working register R4.
Operation
R4 ¬ XH
MOV Rn,A
Move accumulator to register
Machine Code
0010nnn0
Description
Data in the accumulator is moved to the working register "Rn".
Operation
Rn ¬ ACC; Rn=R0, R1, R2, R3, R4, for n=0, 1, 2, 3, 4
MOV TMRH,A
Move accumulator to timer
Machine Code
00111101
Description
The contents of the accumulator is loaded to the high nibble of timer
counter.
Operation
TIMER (high nibble) ¬ ACC
MOV TMRL,A
Move accumulator to timer
Machine Code
00111100
Description
The contents of the accumulator is loaded to the low nibble of timer counter.
Operation
TIMER (low nibble) ¬ ACC
0000dddd
MOV [R1R0],A
Move accumulator to data memory
Machine Code
00000101
Description
Data in the accumulator is moved to the data memory specified by the
register pair "R1,R0".
Operation
M(R1,R0) ¬ ACC
MOV [R3R2],A
Move accumulator to data memory
Machine Code
00000111
Description
Data in the accumulator is moved to the data memory specified by the
register pair "R3,R2".
Operation
M(R3,R2) ¬ ACC
NOP
No operation
Machine Code
00111110
Description
Do nothing, but one instruction cycle is delayed.
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May 19, 1999
HT13J0
OR A,XH
Logical OR immediate data to accumulator
Machine Code
01000100
Description
Data in the accumulator is logical OR with the immediate data specified
by code.
Operation
ACC ¬ ACC "OR" XH
OR A,[R1R0]
Logical OR accumulator with data memory
Machine Code
00011100
Description
Data in the accumulator is logical OR with the data memory addressed
by the register pair "R1,R0".
Operation
ACC ¬ ACC "OR" M(R1,R0)
OR [R1R0],A
Logical OR data memory with accumulator
Machine Code
00011111
Description
Data in the data memory addressed by the register pair "R1,R0" is logical
OR with the accumulator.
Operation
M(R1,R0) ¬ M(R1,R0) "OR" ACC
OUT PA,A
Output accumulator data to port A
Machine Code
0 0 1 1 0 0 0 0 PA
Description
The data in the accumulator is transferred to the port-A and latched.
Note: PA3 controls bit 13 of the program memory. Be careful about PA3
when port A is changed.
Operation
PA ¬ ACC
READ MR0A
Read ROM code of current page to M(R1,R0) and ACC
Machine Code
01001110
Description
The 8-bit ROM code (current page) addressed by ACC and R4 are moved
to the data memory M(R1,R0) and accumulator. The high nibble of the
ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is
loaded to the accumulator. The ROM code address are specified as
shown below:
Current page ® ROM code address bit 12~8
ACC ® ROM code address bit 7~4
R4 ® ROM code address bit 3~0
Operation
M(R1R0) ¬ ROM code (high nibble)
ACC ¬ ROM code (low nibble)
0000dddd
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HT13J0
READ R4A
Read ROM code of current page to R4 and accumulator
Machine Code
01001100
Description
The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) are
moved to the working register R4 and the accumulator. The high nibble
of the ROM code is loaded to R4 and the low nibble of the ROM code is
loaded to the accumulator. The ROM code address are specified below:
Current page ® ROM code address bit 12~8
ACC ® ROM code address bit 7~4
M(R1,R0) ® ROM code address bit 3~0
Operation
R4 ¬ ROM code (high nibble)
ACC ¬ ROM code (low nibble)
READF MR0A
Read ROM Code of page F to M(R1,R0) and ACC
Machine Code
01001111
Description
The 8-bit ROM code (page F) addressed by ACC and R4 are moved to the
data memory M(R1,R0) and accumulator. The high nibble of the ROM
code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded
to the accumulator.
page F ® ROM code address bit 12~8 are "PA3 1111"
ACC ® ROM code address bit 7~4
R4 ® ROM code address bit 3~0
Operation
M(R1,R0) ¬ high nibble of ROM code (page F)
ACC ¬ low nibble of ROM code (page F)
READF R4A
Read ROM code of page F to R4 and accumulator
Machine Code
01001101
Description
The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) are moved
to the working register R4 and the accumulator. The high nibble of the
ROM code is loaded to R4 and the low nibble of the ROM code is loaded to
the accumulator.
page F ® ROM code address bit 12~8 are "PA3 1111"
ACC ® ROM code address bit 7~4
M(R1,R0) ® ROM code address bit 3~0
Operation
R4 ¬ high nibble of ROM code (page F)
ACC ¬ low nibble of ROM code (page F)
RET
Return from subroutine or interrupt
Machine Code
00101110
Description
The program counter bits 0~11 are restored from the stack.
Operation
PC ¬ Stack
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HT13J0
RETI
Return from interrupt subroutine
Machine Code
00101111
Description
The program counter bits 0~11 are restored from the stack. The carry
flag before entering interrupt service routine is restored.
Operation
PC ¬ Stack
C ¬ C (before interrupt service routine)
RL A
Rotate accumulator left
Machine Code
00000001
Description
The contents of the accumulator are rotated left 1 bit. Bit 3 is rotated to
bit 0 and carry flag.
Operation
An+1 ¬ An; An: accumulator bit n (n=0, 1, 2)
A0 ¬ A3
C ¬ A3
RLC A
Rotate accumulator left through carry
Machine Code
00000011
Description
The contents of the accumulator are rotated left 1 bit. Bit 3 replaces the
carry bit; the carry bit is rotated into the bit 0 position.
Operation
An+1 ¬ An; An: Accumulator bit n (n=0, 1, 2)
A0 ¬ C
C ¬ A3
RR A
Rotate accumulator right
Machine Code
00000000
Description
The contents of the accumulator are rotated right 1 bit. Bit 0 is rotated to
bit 3 and carry flag.
Operation
An ¬ An+1; An: Accumulator bit n (n=0, 1, 2)
A3 ¬ A0
C ¬ A0
RRC A
Rotate accumulator right through carry
Machine Code
00000010
Description
The contents of the accumulator are rotated right 1 bit. Bit 0 replaces
the carry bit; the carry bit is rotated into the bit 3 position.
Operation
An ¬ An+1; An: Accumulator bit n (n=0,1,2)
A3 ¬ C
C ¬ A0
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HT13J0
SBC A,[R1R0]
Subtract data memory contents and carry from ACC
Machine Code
00001010
Description
The contents of the data memory addressed by the register pair "R1,R0"
and carry are subtracted from the accumulator. Carry is affected.
Operation
ACC ¬ ACC+M(R1,R0)+CF
SOUND A
Active SOUND channel with accumulator
Machine Code
01001011
Description
The activated sound begins playing in accordance with the contents of
the accumulator when the specified sound channel is matched.
SOUND LOOP
Turn on sound repeat mode
Machine Code
01001001
Description
The activated sound plays repeatedly.
SOUND OFF
Turn off sound
Machine Code
01001010
Description
The singing sound will terminate immediately.
SOUND ONE
Turn on sound one mode
Machine Code
01001000
Description
The activated sound plays only one time.
SOUND n
Active SOUND Channel n
Machine Code
0000nnnn
Description
The specified sound begins playing and overwriting the previous singing
sound. (n=0~15)
01000101
STC
Set carry flag
Machine Code
00101011
Description
The carry flag is set to1.
Operation
C¬1
SUB A,XH
Subtract immediate data from accumulator
Machine Code
01000001
Description
The specified data is subtracted from the accumulator. Carry is affected.
Operation
ACC ¬ ACC+XH+1
0000dddd
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SUB A,[R1R0]
Subtract data memory contents from accumulator
Machine Code
00001011
Description
The contents of the data memory addressed by the register pair "R1,R0"
is subtracted from the accumulator. Carry is affected.
Operation
ACC ¬ ACC+M(R1,R0)+1
TIMER OFF
Set timer to stop counting
Machine Code
00111001
Description
The Timer stops counting, when the "TIMER OFF" instruction is executed.
TIMER ON
Set timer to start counting
Machine Code
00111000
Description
The Timer starts counting, when the "TIMER ON" instruction is executed.
TIMER XXH
Set immediate data to timer counter
Machine Code
01000111
Description
The 8-bit data specified by code is loaded to the Timer counter.
Operation
TIMER ¬ XXH
XOR A,XH
Logical XOR immediate data to accumulator
Machine Code
01000011
Description
Data in the accumulator is Exclusive-OR with the immediate data specified by code.
Operation
ACC ¬ ACC "XOR" XH
XOR A,[R1R0]
Logical XOR accumulator with data memory
Machine Code
00011011
Description
Data in the accumulator is Exclusive-OR with the data memory addressed by the register pair "R1,R0".
Operation
ACC ¬ ACC "XOR" M(R1,R0)
XOR [R1R0],A
Logical XOR data memory with accumulator
Machine Code
00011110
Description
Data in the data memory addressed by the register pair "R1,R0" is logically Exclusive-OR with the accumulator.
Operation
M(R1,R0) ¬ M(R1,R0) "XOR" ACC
dddddddd
0000dddd
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HT13J0
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Microelectronics Enterprises Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright 1999 by HOL TEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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